[people/ms/u-boot.git] / arch / arm / dts / uniphier-ph1-ld4.dtsi

/*
 * Device Tree Source for UniPhier PH1-LD4 SoC
 *
 * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+	X11
 */

/include/ "uniphier-common32.dtsi"

/ {
	compatible = "socionext,ph1-ld4";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
			next-level-cache = <&l2>;
		};
	};

	clocks {
		arm_timer_clk: arm_timer_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <50000000>;
		};

		iobus_clk: iobus_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <100000000>;
		};
	};
};

&soc {
	l2: l2-cache@500c0000 {
		compatible = "socionext,uniphier-system-cache";
		reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
		interrupts = <0 174 4>, <0 175 4>;
		cache-unified;
		cache-size = <(512 * 1024)>;
		cache-sets = <256>;
		cache-line-size = <128>;
		cache-level = <2>;
	};

	port0x: gpio@55000008 {
		compatible = "socionext,uniphier-gpio";
		reg = <0x55000008 0x8>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	port1x: gpio@55000010 {
		compatible = "socionext,uniphier-gpio";
		reg = <0x55000010 0x8>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	port2x: gpio@55000018 {
		compatible = "socionext,uniphier-gpio";
		reg = <0x55000018 0x8>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	port3x: gpio@55000020 {
		compatible = "socionext,uniphier-gpio";
		reg = <0x55000020 0x8>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	port4: gpio@55000028 {
		compatible = "socionext,uniphier-gpio";
		reg = <0x55000028 0x8>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	port5x: gpio@55000030 {
		compatible = "socionext,uniphier-gpio";
		reg = <0x55000030 0x8>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	port6x: gpio@55000038 {
		compatible = "socionext,uniphier-gpio";
		reg = <0x55000038 0x8>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	port7x: gpio@55000040 {
		compatible = "socionext,uniphier-gpio";
		reg = <0x55000040 0x8>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	port8x: gpio@55000048 {
		compatible = "socionext,uniphier-gpio";
		reg = <0x55000048 0x8>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	port9x: gpio@55000050 {
		compatible = "socionext,uniphier-gpio";
		reg = <0x55000050 0x8>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	port10x: gpio@55000058 {
		compatible = "socionext,uniphier-gpio";
		reg = <0x55000058 0x8>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	port11x: gpio@55000060 {
		compatible = "socionext,uniphier-gpio";
		reg = <0x55000060 0x8>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	port12x: gpio@55000068 {
		compatible = "socionext,uniphier-gpio";
		reg = <0x55000068 0x8>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	port13x: gpio@55000070 {
		compatible = "socionext,uniphier-gpio";
		reg = <0x55000070 0x8>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	port14x: gpio@55000078 {
		compatible = "socionext,uniphier-gpio";
		reg = <0x55000078 0x8>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	port16x: gpio@55000088 {
		compatible = "socionext,uniphier-gpio";
		reg = <0x55000088 0x8>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	i2c0: i2c@58400000 {
		compatible = "socionext,uniphier-i2c";
		status = "disabled";
		reg = <0x58400000 0x40>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <0 41 1>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_i2c0>;
		clocks = <&iobus_clk>;
		clock-frequency = <100000>;
	};

	i2c1: i2c@58480000 {
		compatible = "socionext,uniphier-i2c";
		status = "disabled";
		reg = <0x58480000 0x40>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <0 42 1>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_i2c1>;
		clocks = <&iobus_clk>;
		clock-frequency = <100000>;
	};

	/* chip-internal connection for DMD */
	i2c2: i2c@58500000 {
		compatible = "socionext,uniphier-i2c";
		reg = <0x58500000 0x40>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <0 43 1>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_i2c2>;
		clocks = <&iobus_clk>;
		clock-frequency = <400000>;
	};

	i2c3: i2c@58580000 {
		compatible = "socionext,uniphier-i2c";
		status = "disabled";
		reg = <0x58580000 0x40>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <0 44 1>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_i2c3>;
		clocks = <&iobus_clk>;
		clock-frequency = <100000>;
	};

	sd: sdhc@5a400000 {
		compatible = "socionext,uniphier-sdhc";
		status = "disabled";
		reg = <0x5a400000 0x200>;
		interrupts = <0 76 4>;
		pinctrl-names = "default", "1.8v";
		pinctrl-0 = <&pinctrl_sd>;
		pinctrl-1 = <&pinctrl_sd_1v8>;
		clocks = <&mio_clk 0>;
		bus-width = <4>;
	};

	emmc: sdhc@5a500000 {
		compatible = "socionext,uniphier-sdhc";
		status = "disabled";
		reg = <0x5a500000 0x200>;
		interrupts = <0 78 4>;
		pinctrl-names = "default", "1.8v";
		pinctrl-0 = <&pinctrl_emmc>;
		pinctrl-1 = <&pinctrl_emmc_1v8>;
		clocks = <&mio_clk 1>;
		bus-width = <8>;
		non-removable;
	};

	usb0: usb@5a800100 {
		compatible = "socionext,uniphier-ehci", "generic-ehci";
		status = "disabled";
		reg = <0x5a800100 0x100>;
		interrupts = <0 80 4>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usb0>;
		clocks = <&mio_clk 3>, <&mio_clk 6>;
	};

	usb1: usb@5a810100 {
		compatible = "socionext,uniphier-ehci", "generic-ehci";
		status = "disabled";
		reg = <0x5a810100 0x100>;
		interrupts = <0 81 4>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usb1>;
		clocks = <&mio_clk 4>, <&mio_clk 6>;
	};

	usb2: usb@5a820100 {
		compatible = "socionext,uniphier-ehci", "generic-ehci";
		status = "disabled";
		reg = <0x5a820100 0x100>;
		interrupts = <0 82 4>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usb2>;
		clocks = <&mio_clk 5>, <&mio_clk 6>;
	};

	aidet@61830000 {
		compatible = "simple-mfd", "syscon";
		reg = <0x61830000 0x200>;
	};
};

&refclk {
	clock-frequency = <24576000>;
};

&serial0 {
	clock-frequency = <36864000>;
};

&serial1 {
	clock-frequency = <36864000>;
};

&serial2 {
	clock-frequency = <36864000>;
};

&serial3 {
	interrupts = <0 29 4>;
	clock-frequency = <36864000>;
};

&mio_clk {
	compatible = "socionext,uniphier-ld4-mio-clock";
};

&mio_rst {
	compatible = "socionext,uniphier-ld4-mio-reset";
};

&peri_clk {
	compatible = "socionext,uniphier-ld4-peri-clock";
};

&peri_rst {
	compatible = "socionext,uniphier-ld4-peri-reset";
};

&pinctrl {
	compatible = "socionext,uniphier-ld4-pinctrl";
};

&sys_clk {
	compatible = "socionext,uniphier-ld4-clock";
};

&sys_rst {
	compatible = "socionext,uniphier-ld4-reset";
};
Commit	Line	Data
509eb678 MY	1	/*
	2	* Device Tree Source for UniPhier PH1-LD4 SoC
	3	*
edcfaeb8	4	* Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
509eb678	5	*
13b2ba1a	6	* SPDX-License-Identifier: GPL-2.0+ X11
509eb678 MY	7	*/
509eb678 MY	8
8f06243a	9	/include/ "uniphier-common32.dtsi"
509eb678 MY	10
509eb678 MY	11	/ {
6462cded	12	compatible = "socionext,ph1-ld4";
509eb678 MY	13
509eb678 MY	14	cpus {
509eb678	15	#address-cells = <1>;
f5fd7afc	16	#size-cells = <0>;
509eb678 MY	17
	18	cpu@0 {
	19	device_type = "cpu";
	20	compatible = "arm,cortex-a9";
	21	reg = <0>;
4e1f81d4	22	next-level-cache = <&l2>;
509eb678 MY	23	};
	24	};
	25
edcfaeb8 MY	26	clocks {
	27	arm_timer_clk: arm_timer_clk {
	28	#clock-cells = <0>;
	29	compatible = "fixed-clock";
	30	clock-frequency = <50000000>;
	31	};
d243c186	32
d243c186 MY	33	iobus_clk: iobus_clk {
	34	#clock-cells = <0>;
	35	compatible = "fixed-clock";
	36	clock-frequency = <100000000>;
	37	};
edcfaeb8	38	};
8f06243a	39	};
edcfaeb8	40
8f06243a	41	&soc {
4e1f81d4 MY	42	l2: l2-cache@500c0000 {
	43	compatible = "socionext,uniphier-system-cache";
	44	reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
	45	interrupts = <0 174 4>, <0 175 4>;
	46	cache-unified;
	47	cache-size = <(512 * 1024)>;
	48	cache-sets = <256>;
	49	cache-line-size = <128>;
	50	cache-level = <2>;
	51	};
	52
595dc1e1 MY	53	port0x: gpio@55000008 {
	54	compatible = "socionext,uniphier-gpio";
	55	reg = <0x55000008 0x8>;
	56	gpio-controller;
	57	#gpio-cells = <2>;
	58	};
	59
	60	port1x: gpio@55000010 {
	61	compatible = "socionext,uniphier-gpio";
	62	reg = <0x55000010 0x8>;
	63	gpio-controller;
	64	#gpio-cells = <2>;
	65	};
	66
	67	port2x: gpio@55000018 {
	68	compatible = "socionext,uniphier-gpio";
	69	reg = <0x55000018 0x8>;
	70	gpio-controller;
	71	#gpio-cells = <2>;
	72	};
	73
	74	port3x: gpio@55000020 {
	75	compatible = "socionext,uniphier-gpio";
	76	reg = <0x55000020 0x8>;
	77	gpio-controller;
	78	#gpio-cells = <2>;
	79	};
	80
	81	port4: gpio@55000028 {
	82	compatible = "socionext,uniphier-gpio";
	83	reg = <0x55000028 0x8>;
	84	gpio-controller;
	85	#gpio-cells = <2>;
	86	};
	87
	88	port5x: gpio@55000030 {
	89	compatible = "socionext,uniphier-gpio";
	90	reg = <0x55000030 0x8>;
	91	gpio-controller;
	92	#gpio-cells = <2>;
	93	};
	94
	95	port6x: gpio@55000038 {
	96	compatible = "socionext,uniphier-gpio";
	97	reg = <0x55000038 0x8>;
	98	gpio-controller;
	99	#gpio-cells = <2>;
	100	};
	101
	102	port7x: gpio@55000040 {
	103	compatible = "socionext,uniphier-gpio";
	104	reg = <0x55000040 0x8>;
	105	gpio-controller;
	106	#gpio-cells = <2>;
	107	};
	108
	109	port8x: gpio@55000048 {
	110	compatible = "socionext,uniphier-gpio";
	111	reg = <0x55000048 0x8>;
	112	gpio-controller;
	113	#gpio-cells = <2>;
	114	};
	115
	116	port9x: gpio@55000050 {
117	compatible = "socionext,uniphier-gpio";
118	reg = <0x55000050 0x8>;
119	gpio-controller;
120	#gpio-cells = <2>;
121	};
122
123	port10x: gpio@55000058 {
124	compatible = "socionext,uniphier-gpio";
125	reg = <0x55000058 0x8>;
126	gpio-controller;
127	#gpio-cells = <2>;
128	};
129
130	port11x: gpio@55000060 {
131	compatible = "socionext,uniphier-gpio";
132	reg = <0x55000060 0x8>;
133	gpio-controller;
134	#gpio-cells = <2>;
135	};
136
137	port12x: gpio@55000068 {
138	compatible = "socionext,uniphier-gpio";
139	reg = <0x55000068 0x8>;
140	gpio-controller;
141	#gpio-cells = <2>;
142	};
143
144	port13x: gpio@55000070 {
145	compatible = "socionext,uniphier-gpio";
146	reg = <0x55000070 0x8>;
147	gpio-controller;
148	#gpio-cells = <2>;
149	};
150
151	port14x: gpio@55000078 {
152	compatible = "socionext,uniphier-gpio";
153	reg = <0x55000078 0x8>;
154	gpio-controller;
155	#gpio-cells = <2>;
156	};
157
158	port16x: gpio@55000088 {
159	compatible = "socionext,uniphier-gpio";
160	reg = <0x55000088 0x8>;
161	gpio-controller;
162	#gpio-cells = <2>;
163	};
164
8f06243a MY	165	i2c0: i2c@58400000 {
	166	compatible = "socionext,uniphier-i2c";
	167	status = "disabled";
	168	reg = <0x58400000 0x40>;
509eb678	169	#address-cells = <1>;
8f06243a MY	170	#size-cells = <0>;
	171	interrupts = <0 41 1>;
	172	pinctrl-names = "default";
	173	pinctrl-0 = <&pinctrl_i2c0>;
	174	clocks = <&iobus_clk>;
	175	clock-frequency = <100000>;
	176	};
f5fd7afc	177
8f06243a MY	178	i2c1: i2c@58480000 {
	179	compatible = "socionext,uniphier-i2c";
	180	status = "disabled";
	181	reg = <0x58480000 0x40>;
	182	#address-cells = <1>;
	183	#size-cells = <0>;
	184	interrupts = <0 42 1>;
	185	pinctrl-names = "default";
	186	pinctrl-0 = <&pinctrl_i2c1>;
	187	clocks = <&iobus_clk>;
	188	clock-frequency = <100000>;
	189	};
f5fd7afc	190
8f06243a MY	191	/* chip-internal connection for DMD */
	192	i2c2: i2c@58500000 {
	193	compatible = "socionext,uniphier-i2c";
	194	reg = <0x58500000 0x40>;
	195	#address-cells = <1>;
	196	#size-cells = <0>;
	197	interrupts = <0 43 1>;
	198	pinctrl-names = "default";
	199	pinctrl-0 = <&pinctrl_i2c2>;
	200	clocks = <&iobus_clk>;
	201	clock-frequency = <400000>;
	202	};
edcfaeb8	203
8f06243a MY	204	i2c3: i2c@58580000 {
	205	compatible = "socionext,uniphier-i2c";
	206	status = "disabled";
	207	reg = <0x58580000 0x40>;
	208	#address-cells = <1>;
	209	#size-cells = <0>;
	210	interrupts = <0 44 1>;
	211	pinctrl-names = "default";
	212	pinctrl-0 = <&pinctrl_i2c3>;
	213	clocks = <&iobus_clk>;
	214	clock-frequency = <100000>;
	215	};
149c751d	216
c7f94eec MY	217	sd: sdhc@5a400000 {
	218	compatible = "socionext,uniphier-sdhc";
	219	status = "disabled";
	220	reg = <0x5a400000 0x200>;
	221	interrupts = <0 76 4>;
	222	pinctrl-names = "default", "1.8v";
	223	pinctrl-0 = <&pinctrl_sd>;
	224	pinctrl-1 = <&pinctrl_sd_1v8>;
35343a26	225	clocks = <&mio_clk 0>;
c7f94eec MY	226	bus-width = <4>;
	227	};
	228
	229	emmc: sdhc@5a500000 {
	230	compatible = "socionext,uniphier-sdhc";
	231	status = "disabled";
	232	reg = <0x5a500000 0x200>;
	233	interrupts = <0 78 4>;
	234	pinctrl-names = "default", "1.8v";
	235	pinctrl-0 = <&pinctrl_emmc>;
	236	pinctrl-1 = <&pinctrl_emmc_1v8>;
35343a26	237	clocks = <&mio_clk 1>;
c7f94eec MY	238	bus-width = <8>;
	239	non-removable;
	240	};
	241
8f06243a MY	242	usb0: usb@5a800100 {
	243	compatible = "socionext,uniphier-ehci", "generic-ehci";
	244	status = "disabled";
	245	reg = <0x5a800100 0x100>;
	246	interrupts = <0 80 4>;
	247	pinctrl-names = "default";
	248	pinctrl-0 = <&pinctrl_usb0>;
35343a26	249	clocks = <&mio_clk 3>, <&mio_clk 6>;
8f06243a	250	};
149c751d	251
8f06243a MY	252	usb1: usb@5a810100 {
	253	compatible = "socionext,uniphier-ehci", "generic-ehci";
	254	status = "disabled";
	255	reg = <0x5a810100 0x100>;
	256	interrupts = <0 81 4>;
	257	pinctrl-names = "default";
	258	pinctrl-0 = <&pinctrl_usb1>;
35343a26	259	clocks = <&mio_clk 4>, <&mio_clk 6>;
8f06243a	260	};
d243c186	261
8f06243a MY	262	usb2: usb@5a820100 {
	263	compatible = "socionext,uniphier-ehci", "generic-ehci";
	264	status = "disabled";
	265	reg = <0x5a820100 0x100>;
	266	interrupts = <0 82 4>;
	267	pinctrl-names = "default";
	268	pinctrl-0 = <&pinctrl_usb2>;
35343a26	269	clocks = <&mio_clk 5>, <&mio_clk 6>;
8f06243a	270	};
1013aef3 MY	271
	272	aidet@61830000 {
	273	compatible = "simple-mfd", "syscon";
	274	reg = <0x61830000 0x200>;
	275	};
8f06243a	276	};
f5fd7afc	277
cc336095 MY	278	&refclk {
	279	clock-frequency = <24576000>;
	280	};
	281
8f06243a MY	282	&serial0 {
	283	clock-frequency = <36864000>;
	284	};
edcfaeb8	285
8f06243a MY	286	&serial1 {
	287	clock-frequency = <36864000>;
	288	};
edcfaeb8	289
8f06243a MY	290	&serial2 {
	291	clock-frequency = <36864000>;
	292	};
edcfaeb8	293
8f06243a MY	294	&serial3 {
	295	interrupts = <0 29 4>;
	296	clock-frequency = <36864000>;
509eb678	297	};
d243c186	298
35343a26 MY	299	&mio_clk {
	300	compatible = "socionext,uniphier-ld4-mio-clock";
	301	};
	302
	303	&mio_rst {
	304	compatible = "socionext,uniphier-ld4-mio-reset";
	305	};
	306
	307	&peri_clk {
	308	compatible = "socionext,uniphier-ld4-peri-clock";
aa37aba1 MY	309	};
aa37aba1 MY	310
35343a26 MY	311	&peri_rst {
35343a26 MY	312	compatible = "socionext,uniphier-ld4-peri-reset";
9fbb2f7e MY	313	};
9fbb2f7e MY	314
8f06243a	315	&pinctrl {
c4adc50e	316	compatible = "socionext,uniphier-ld4-pinctrl";
8f06243a	317	};
233812a6	318
35343a26 MY	319	&sys_clk {
	320	compatible = "socionext,uniphier-ld4-clock";
	321	};
	322
	323	&sys_rst {
	324	compatible = "socionext,uniphier-ld4-reset";
233812a6	325	};