[people/ms/u-boot.git] / arch / arm / dts / uniphier-ph1-sld3.dtsi

/*
 * Device Tree Source for UniPhier PH1-sLD3 SoC
 *
 * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+	X11
 */

/include/ "skeleton.dtsi"

/ {
	compatible = "socionext,ph1-sld3";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "socionext,uniphier-smp";

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
		};
	};

	clocks {
		refclk: ref {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <24576000>;
		};

		arm_timer_clk: arm_timer_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <50000000>;
		};

		uart_clk: uart_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <36864000>;
		};

		iobus_clk: iobus_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <100000000>;
		};
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		interrupt-parent = <&intc>;
		u-boot,dm-pre-reloc;

		timer@20000200 {
			compatible = "arm,cortex-a9-global-timer";
			reg = <0x20000200 0x20>;
			interrupts = <1 11 0x304>;
			clocks = <&arm_timer_clk>;
		};

		timer@20000600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0x20000600 0x20>;
			interrupts = <1 13 0x304>;
			clocks = <&arm_timer_clk>;
		};

		intc: interrupt-controller@20001000 {
			compatible = "arm,cortex-a9-gic";
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0x20001000 0x1000>,
			      <0x20000100 0x100>;
		};

		serial0: serial@54006800 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006800 0x40>;
			interrupts = <0 33 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart0>;
			clocks = <&uart_clk>;
			clock-frequency = <36864000>;
		};

		serial1: serial@54006900 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006900 0x40>;
			interrupts = <0 35 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart1>;
			clocks = <&uart_clk>;
			clock-frequency = <36864000>;
		};

		serial2: serial@54006a00 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006a00 0x40>;
			interrupts = <0 37 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart2>;
			clocks = <&uart_clk>;
			clock-frequency = <36864000>;
		};

		port0x: gpio@55000008 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000008 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port1x: gpio@55000010 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000010 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port2x: gpio@55000018 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000018 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port3x: gpio@55000020 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000020 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port4: gpio@55000028 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000028 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port5x: gpio@55000030 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000030 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port6x: gpio@55000038 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000038 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port7x: gpio@55000040 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000040 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port8x: gpio@55000048 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000048 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port9x: gpio@55000050 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000050 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port10x: gpio@55000058 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000058 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port11x: gpio@55000060 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000060 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port12x: gpio@55000068 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000068 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port13x: gpio@55000070 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000070 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port14x: gpio@55000078 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000078 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port16x: gpio@55000088 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000088 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		i2c0: i2c@58400000 {
			compatible = "socionext,uniphier-i2c";
			status = "disabled";
			reg = <0x58400000 0x40>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 41 1>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c0>;
			clocks = <&iobus_clk>;
			clock-frequency = <100000>;
		};

		i2c1: i2c@58480000 {
			compatible = "socionext,uniphier-i2c";
			status = "disabled";
			reg = <0x58480000 0x40>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 42 1>;
			clocks = <&iobus_clk>;
			clock-frequency = <100000>;
		};

		i2c2: i2c@58500000 {
			compatible = "socionext,uniphier-i2c";
			status = "disabled";
			reg = <0x58500000 0x40>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 43 1>;
			clocks = <&iobus_clk>;
			clock-frequency = <100000>;
		};

		i2c3: i2c@58580000 {
			compatible = "socionext,uniphier-i2c";
			status = "disabled";
			reg = <0x58580000 0x40>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 44 1>;
			clocks = <&iobus_clk>;
			clock-frequency = <100000>;
		};

		/* chip-internal connection for DMD */
		i2c4: i2c@58600000 {
			compatible = "socionext,uniphier-i2c";
			reg = <0x58600000 0x40>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 45 1>;
			clocks = <&iobus_clk>;
			clock-frequency = <400000>;
		};

		system_bus: system-bus@58c00000 {
			compatible = "socionext,uniphier-system-bus";
			reg = <0x58c00000 0x400>;
			#address-cells = <2>;
			#size-cells = <1>;
		};

		smpctrl@59800000 {
			compatible = "socionext,uniphier-smpctrl";
			reg = <0x59801000 0x400>;
		};

		mio: mioctrl@59810000 {
			compatible = "socionext,ph1-sld3-mioctrl";
			reg = <0x59810000 0x800>;
			#clock-cells = <1>;
			clock-names = "stdmac", "ehci";
			clocks = <&sysctrl 10>, <&sysctrl 18>;
		};

		emmc: sdhc@5a400000 {
			compatible = "socionext,uniphier-sdhc";
			status = "disabled";
			reg = <0x5a400000 0x200>;
			interrupts = <0 78 4>;
			pinctrl-names = "default", "1.8v";
			pinctrl-0 = <&pinctrl_emmc>;
			pinctrl-1 = <&pinctrl_emmc_1v8>;
			clocks = <&mio 1>;
			bus-width = <8>;
			non-removable;
		};

		sd: sdhc@5a500000 {
			compatible = "socionext,uniphier-sdhc";
			status = "disabled";
			reg = <0x5a500000 0x200>;
			interrupts = <0 76 4>;
			pinctrl-names = "default", "1.8v";
			pinctrl-0 = <&pinctrl_sd>;
			pinctrl-1 = <&pinctrl_sd_1v8>;
			clocks = <&mio 0>;
			bus-width = <4>;
		};

		usb0: usb@5a800100 {
			compatible = "socionext,uniphier-ehci", "generic-ehci";
			status = "disabled";
			reg = <0x5a800100 0x100>;
			interrupts = <0 80 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb0>;
			clocks = <&mio 3>, <&mio 6>;
		};

		usb1: usb@5a810100 {
			compatible = "socionext,uniphier-ehci", "generic-ehci";
			status = "disabled";
			reg = <0x5a810100 0x100>;
			interrupts = <0 81 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb1>;
			clocks = <&mio 4>, <&mio 6>;
		};

		usb2: usb@5a820100 {
			compatible = "socionext,uniphier-ehci", "generic-ehci";
			status = "disabled";
			reg = <0x5a820100 0x100>;
			interrupts = <0 82 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb2>;
			clocks = <&mio 5>, <&mio 6>;
		};

		usb3: usb@5a830100 {
			compatible = "socionext,uniphier-ehci", "generic-ehci";
			status = "disabled";
			reg = <0x5a830100 0x100>;
			interrupts = <0 83 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb3>;
			clocks = <&mio 7>, <&mio 6>;
		};

		soc-glue@5f800000 {
			compatible = "simple-mfd", "syscon";
			reg = <0x5f800000 0x2000>;
			u-boot,dm-pre-reloc;

			pinctrl: pinctrl {
				compatible = "socionext,uniphier-sld3-pinctrl";
				u-boot,dm-pre-reloc;
			};
		};

		aidet@f1830000 {
			compatible = "simple-mfd", "syscon";
			reg = <0xf1830000 0x200>;
		};

		sysctrl: sysctrl@f1840000 {
			compatible = "socionext,ph1-sld3-sysctrl";
			reg = <0xf1840000 0x4000>;
			#clock-cells = <1>;
			clock-names = "ref";
			clocks = <&refclk>;
		};

		nand: nand@f8000000 {
			compatible = "denali,denali-nand-dt";
			reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
			reg-names = "nand_data", "denali_reg";
		};
	};
};

/include/ "uniphier-pinctrl.dtsi"
Commit	Line	Data
230ce30a MY	1	/*
	2	* Device Tree Source for UniPhier PH1-sLD3 SoC
	3	*
edcfaeb8	4	* Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
230ce30a	5	*
13b2ba1a	6	* SPDX-License-Identifier: GPL-2.0+ X11
230ce30a MY	7	*/
	8
	9	/include/ "skeleton.dtsi"
	10
	11	/ {
6462cded	12	compatible = "socionext,ph1-sld3";
230ce30a MY	13
	14	cpus {
	15	#address-cells = <1>;
	16	#size-cells = <0>;
edcfaeb8	17	enable-method = "socionext,uniphier-smp";
230ce30a MY	18
	19	cpu@0 {
	20	device_type = "cpu";
	21	compatible = "arm,cortex-a9";
	22	reg = <0>;
	23	};
	24
	25	cpu@1 {
	26	device_type = "cpu";
	27	compatible = "arm,cortex-a9";
	28	reg = <1>;
	29	};
	30	};
	31
edcfaeb8	32	clocks {
cc336095 MY	33	refclk: ref {
	34	#clock-cells = <0>;
	35	compatible = "fixed-clock";
	36	clock-frequency = <24576000>;
	37	};
	38
edcfaeb8 MY	39	arm_timer_clk: arm_timer_clk {
	40	#clock-cells = <0>;
	41	compatible = "fixed-clock";
	42	clock-frequency = <50000000>;
	43	};
d243c186 MY	44
	45	uart_clk: uart_clk {
	46	#clock-cells = <0>;
	47	compatible = "fixed-clock";
	48	clock-frequency = <36864000>;
	49	};
	50
	51	iobus_clk: iobus_clk {
	52	#clock-cells = <0>;
	53	compatible = "fixed-clock";
	54	clock-frequency = <100000000>;
	55	};
edcfaeb8 MY	56	};
edcfaeb8 MY	57
230ce30a MY	58	soc {
	59	compatible = "simple-bus";
	60	#address-cells = <1>;
	61	#size-cells = <1>;
	62	ranges;
edcfaeb8	63	interrupt-parent = <&intc>;
f0633533	64	u-boot,dm-pre-reloc;
edcfaeb8	65
edcfaeb8 MY	66	timer@20000200 {
	67	compatible = "arm,cortex-a9-global-timer";
	68	reg = <0x20000200 0x20>;
	69	interrupts = <1 11 0x304>;
	70	clocks = <&arm_timer_clk>;
	71	};
	72
	73	timer@20000600 {
	74	compatible = "arm,cortex-a9-twd-timer";
	75	reg = <0x20000600 0x20>;
	76	interrupts = <1 13 0x304>;
	77	clocks = <&arm_timer_clk>;
	78	};
	79
	80	intc: interrupt-controller@20001000 {
	81	compatible = "arm,cortex-a9-gic";
	82	#interrupt-cells = <3>;
	83	interrupt-controller;
	84	reg = <0x20001000 0x1000>,
	85	<0x20000100 0x100>;
	86	};
230ce30a	87
d243c186	88	serial0: serial@54006800 {
6462cded	89	compatible = "socionext,uniphier-uart";
230ce30a	90	status = "disabled";
d243c186 MY	91	reg = <0x54006800 0x40>;
d243c186 MY	92	interrupts = <0 33 4>;
4475c0ca MY	93	pinctrl-names = "default";
4475c0ca MY	94	pinctrl-0 = <&pinctrl_uart0>;
d243c186	95	clocks = <&uart_clk>;
230ce30a MY	96	clock-frequency = <36864000>;
	97	};
	98
d243c186	99	serial1: serial@54006900 {
6462cded	100	compatible = "socionext,uniphier-uart";
230ce30a	101	status = "disabled";
d243c186 MY	102	reg = <0x54006900 0x40>;
d243c186 MY	103	interrupts = <0 35 4>;
4475c0ca MY	104	pinctrl-names = "default";
4475c0ca MY	105	pinctrl-0 = <&pinctrl_uart1>;
d243c186	106	clocks = <&uart_clk>;
230ce30a MY	107	clock-frequency = <36864000>;
	108	};
	109
d243c186	110	serial2: serial@54006a00 {
6462cded	111	compatible = "socionext,uniphier-uart";
230ce30a	112	status = "disabled";
d243c186 MY	113	reg = <0x54006a00 0x40>;
d243c186 MY	114	interrupts = <0 37 4>;
4475c0ca MY	115	pinctrl-names = "default";
4475c0ca MY	116	pinctrl-0 = <&pinctrl_uart2>;
d243c186	117	clocks = <&uart_clk>;
230ce30a MY	118	clock-frequency = <36864000>;
	119	};
	120
595dc1e1 MY	121	port0x: gpio@55000008 {
	122	compatible = "socionext,uniphier-gpio";
	123	reg = <0x55000008 0x8>;
	124	gpio-controller;
	125	#gpio-cells = <2>;
	126	};
	127
	128	port1x: gpio@55000010 {
	129	compatible = "socionext,uniphier-gpio";
	130	reg = <0x55000010 0x8>;
	131	gpio-controller;
	132	#gpio-cells = <2>;
	133	};
	134
	135	port2x: gpio@55000018 {
	136	compatible = "socionext,uniphier-gpio";
	137	reg = <0x55000018 0x8>;
	138	gpio-controller;
	139	#gpio-cells = <2>;
	140	};
	141
	142	port3x: gpio@55000020 {
	143	compatible = "socionext,uniphier-gpio";
	144	reg = <0x55000020 0x8>;
	145	gpio-controller;
	146	#gpio-cells = <2>;
	147	};
	148
	149	port4: gpio@55000028 {
	150	compatible = "socionext,uniphier-gpio";
	151	reg = <0x55000028 0x8>;
	152	gpio-controller;
	153	#gpio-cells = <2>;
	154	};
	155
	156	port5x: gpio@55000030 {
	157	compatible = "socionext,uniphier-gpio";
	158	reg = <0x55000030 0x8>;
	159	gpio-controller;
	160	#gpio-cells = <2>;
	161	};
	162
	163	port6x: gpio@55000038 {
	164	compatible = "socionext,uniphier-gpio";
	165	reg = <0x55000038 0x8>;
	166	gpio-controller;
	167	#gpio-cells = <2>;
	168	};
	169
	170	port7x: gpio@55000040 {
	171	compatible = "socionext,uniphier-gpio";
	172	reg = <0x55000040 0x8>;
	173	gpio-controller;
	174	#gpio-cells = <2>;
	175	};
	176
	177	port8x: gpio@55000048 {
	178	compatible = "socionext,uniphier-gpio";
	179	reg = <0x55000048 0x8>;
	180	gpio-controller;
	181	#gpio-cells = <2>;
	182	};
	183
	184	port9x: gpio@55000050 {
185	compatible = "socionext,uniphier-gpio";
186	reg = <0x55000050 0x8>;
187	gpio-controller;
188	#gpio-cells = <2>;
189	};
190
191	port10x: gpio@55000058 {
192	compatible = "socionext,uniphier-gpio";
193	reg = <0x55000058 0x8>;
194	gpio-controller;
195	#gpio-cells = <2>;
196	};
197
198	port11x: gpio@55000060 {
199	compatible = "socionext,uniphier-gpio";
200	reg = <0x55000060 0x8>;
201	gpio-controller;
202	#gpio-cells = <2>;
203	};
204
205	port12x: gpio@55000068 {
206	compatible = "socionext,uniphier-gpio";
207	reg = <0x55000068 0x8>;
208	gpio-controller;
209	#gpio-cells = <2>;
210	};
211
212	port13x: gpio@55000070 {
213	compatible = "socionext,uniphier-gpio";
214	reg = <0x55000070 0x8>;
215	gpio-controller;
216	#gpio-cells = <2>;
217	};
218
219	port14x: gpio@55000078 {
220	compatible = "socionext,uniphier-gpio";
221	reg = <0x55000078 0x8>;
222	gpio-controller;
223	#gpio-cells = <2>;
224	};
225
226	port16x: gpio@55000088 {
227	compatible = "socionext,uniphier-gpio";
228	reg = <0x55000088 0x8>;
229	gpio-controller;
230	#gpio-cells = <2>;
231	};
232
230ce30a	233	i2c0: i2c@58400000 {
6462cded	234	compatible = "socionext,uniphier-i2c";
d243c186 MY	235	status = "disabled";
d243c186 MY	236	reg = <0x58400000 0x40>;
230ce30a MY	237	#address-cells = <1>;
230ce30a MY	238	#size-cells = <0>;
d243c186	239	interrupts = <0 41 1>;
4475c0ca MY	240	pinctrl-names = "default";
4475c0ca MY	241	pinctrl-0 = <&pinctrl_i2c0>;
d243c186	242	clocks = <&iobus_clk>;
230ce30a	243	clock-frequency = <100000>;
230ce30a MY	244	};
	245
	246	i2c1: i2c@58480000 {
6462cded	247	compatible = "socionext,uniphier-i2c";
d243c186 MY	248	status = "disabled";
d243c186 MY	249	reg = <0x58480000 0x40>;
230ce30a MY	250	#address-cells = <1>;
230ce30a MY	251	#size-cells = <0>;
d243c186 MY	252	interrupts = <0 42 1>;
d243c186 MY	253	clocks = <&iobus_clk>;
230ce30a	254	clock-frequency = <100000>;
230ce30a MY	255	};
	256
	257	i2c2: i2c@58500000 {
6462cded	258	compatible = "socionext,uniphier-i2c";
d243c186 MY	259	status = "disabled";
d243c186 MY	260	reg = <0x58500000 0x40>;
230ce30a MY	261	#address-cells = <1>;
230ce30a MY	262	#size-cells = <0>;
d243c186 MY	263	interrupts = <0 43 1>;
d243c186 MY	264	clocks = <&iobus_clk>;
230ce30a	265	clock-frequency = <100000>;
230ce30a MY	266	};
	267
	268	i2c3: i2c@58580000 {
6462cded	269	compatible = "socionext,uniphier-i2c";
d243c186 MY	270	status = "disabled";
d243c186 MY	271	reg = <0x58580000 0x40>;
230ce30a MY	272	#address-cells = <1>;
230ce30a MY	273	#size-cells = <0>;
d243c186 MY	274	interrupts = <0 44 1>;
d243c186 MY	275	clocks = <&iobus_clk>;
230ce30a	276	clock-frequency = <100000>;
230ce30a MY	277	};
230ce30a MY	278
d243c186	279	/* chip-internal connection for DMD */
f1d79453	280	i2c4: i2c@58600000 {
d243c186 MY	281	compatible = "socionext,uniphier-i2c";
d243c186 MY	282	reg = <0x58600000 0x40>;
f1d79453 MY	283	#address-cells = <1>;
f1d79453 MY	284	#size-cells = <0>;
d243c186 MY	285	interrupts = <0 45 1>;
d243c186 MY	286	clocks = <&iobus_clk>;
f1d79453	287	clock-frequency = <400000>;
f1d79453 MY	288	};
f1d79453 MY	289
0f5fb8ce MY	290	system_bus: system-bus@58c00000 {
	291	compatible = "socionext,uniphier-system-bus";
	292	reg = <0x58c00000 0x400>;
	293	#address-cells = <2>;
	294	#size-cells = <1>;
	295	};
	296
	297	smpctrl@59800000 {
	298	compatible = "socionext,uniphier-smpctrl";
	299	reg = <0x59801000 0x400>;
edcfaeb8	300	};
aa37aba1 MY	301
	302	mio: mioctrl@59810000 {
	303	compatible = "socionext,ph1-sld3-mioctrl";
	304	reg = <0x59810000 0x800>;
	305	#clock-cells = <1>;
	306	clock-names = "stdmac", "ehci";
	307	clocks = <&sysctrl 10>, <&sysctrl 18>;
	308	};
edcfaeb8	309
c7f94eec MY	310	emmc: sdhc@5a400000 {
	311	compatible = "socionext,uniphier-sdhc";
	312	status = "disabled";
	313	reg = <0x5a400000 0x200>;
	314	interrupts = <0 78 4>;
4475c0ca MY	315	pinctrl-names = "default", "1.8v";
	316	pinctrl-0 = <&pinctrl_emmc>;
	317	pinctrl-1 = <&pinctrl_emmc_1v8>;
c7f94eec MY	318	clocks = <&mio 1>;
	319	bus-width = <8>;
	320	non-removable;
	321	};
	322
	323	sd: sdhc@5a500000 {
	324	compatible = "socionext,uniphier-sdhc";
	325	status = "disabled";
	326	reg = <0x5a500000 0x200>;
	327	interrupts = <0 76 4>;
4475c0ca MY	328	pinctrl-names = "default", "1.8v";
	329	pinctrl-0 = <&pinctrl_sd>;
	330	pinctrl-1 = <&pinctrl_sd_1v8>;
c7f94eec MY	331	clocks = <&mio 0>;
	332	bus-width = <4>;
	333	};
	334
230ce30a	335	usb0: usb@5a800100 {
6462cded	336	compatible = "socionext,uniphier-ehci", "generic-ehci";
230ce30a MY	337	status = "disabled";
230ce30a MY	338	reg = <0x5a800100 0x100>;
d243c186	339	interrupts = <0 80 4>;
4475c0ca MY	340	pinctrl-names = "default";
4475c0ca MY	341	pinctrl-0 = <&pinctrl_usb0>;
49dde45b	342	clocks = <&mio 3>, <&mio 6>;
230ce30a MY	343	};
	344
	345	usb1: usb@5a810100 {
6462cded	346	compatible = "socionext,uniphier-ehci", "generic-ehci";
230ce30a MY	347	status = "disabled";
230ce30a MY	348	reg = <0x5a810100 0x100>;
d243c186	349	interrupts = <0 81 4>;
4475c0ca MY	350	pinctrl-names = "default";
4475c0ca MY	351	pinctrl-0 = <&pinctrl_usb1>;
49dde45b	352	clocks = <&mio 4>, <&mio 6>;
230ce30a MY	353	};
	354
	355	usb2: usb@5a820100 {
6462cded	356	compatible = "socionext,uniphier-ehci", "generic-ehci";
230ce30a MY	357	status = "disabled";
230ce30a MY	358	reg = <0x5a820100 0x100>;
d243c186	359	interrupts = <0 82 4>;
4475c0ca MY	360	pinctrl-names = "default";
4475c0ca MY	361	pinctrl-0 = <&pinctrl_usb2>;
49dde45b	362	clocks = <&mio 5>, <&mio 6>;
230ce30a MY	363	};
	364
	365	usb3: usb@5a830100 {
6462cded	366	compatible = "socionext,uniphier-ehci", "generic-ehci";
230ce30a MY	367	status = "disabled";
230ce30a MY	368	reg = <0x5a830100 0x100>;
d243c186	369	interrupts = <0 83 4>;
4475c0ca MY	370	pinctrl-names = "default";
4475c0ca MY	371	pinctrl-0 = <&pinctrl_usb3>;
49dde45b	372	clocks = <&mio 7>, <&mio 6>;
230ce30a MY	373	};
230ce30a MY	374
4475c0ca MY	375	soc-glue@5f800000 {
	376	compatible = "simple-mfd", "syscon";
	377	reg = <0x5f800000 0x2000>;
	378	u-boot,dm-pre-reloc;
	379
	380	pinctrl: pinctrl {
	381	compatible = "socionext,uniphier-sld3-pinctrl";
	382	u-boot,dm-pre-reloc;
	383	};
	384	};
	385
1013aef3 MY	386	aidet@f1830000 {
	387	compatible = "simple-mfd", "syscon";
	388	reg = <0xf1830000 0x200>;
	389	};
	390
233812a6 MY	391	sysctrl: sysctrl@f1840000 {
	392	compatible = "socionext,ph1-sld3-sysctrl";
	393	reg = <0xf1840000 0x4000>;
	394	#clock-cells = <1>;
	395	clock-names = "ref";
	396	clocks = <&refclk>;
	397	};
	398
230ce30a MY	399	nand: nand@f8000000 {
	400	compatible = "denali,denali-nand-dt";
	401	reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
	402	reg-names = "nand_data", "denali_reg";
	403	};
	404	};
	405	};
4475c0ca MY	406
4475c0ca MY	407	/include/ "uniphier-pinctrl.dtsi"