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Commit | Line | Data |
---|---|---|
f875bbb4 | 1 | /* |
52159d27 | 2 | * Device Tree Source for UniPhier PXs2 SoC |
f875bbb4 | 3 | * |
52159d27 MY |
4 | * Copyright (C) 2015-2016 Socionext Inc. |
5 | * Author: Masahiro Yamada <yamada.masahiro@socionext.com> | |
f875bbb4 | 6 | * |
d9403001 | 7 | * SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
f875bbb4 MY |
8 | */ |
9 | ||
f875bbb4 | 10 | / { |
52159d27 | 11 | compatible = "socionext,uniphier-pxs2"; |
f16eda96 MY |
12 | #address-cells = <1>; |
13 | #size-cells = <1>; | |
f875bbb4 MY |
14 | |
15 | cpus { | |
16 | #address-cells = <1>; | |
17 | #size-cells = <0>; | |
f875bbb4 MY |
18 | |
19 | cpu@0 { | |
20 | device_type = "cpu"; | |
21 | compatible = "arm,cortex-a9"; | |
22 | reg = <0>; | |
cd62214d | 23 | clocks = <&sys_clk 32>; |
52159d27 | 24 | enable-method = "psci"; |
4e1f81d4 | 25 | next-level-cache = <&l2>; |
cd62214d | 26 | operating-points-v2 = <&cpu_opp>; |
f875bbb4 MY |
27 | }; |
28 | ||
29 | cpu@1 { | |
30 | device_type = "cpu"; | |
31 | compatible = "arm,cortex-a9"; | |
32 | reg = <1>; | |
cd62214d | 33 | clocks = <&sys_clk 32>; |
52159d27 | 34 | enable-method = "psci"; |
4e1f81d4 | 35 | next-level-cache = <&l2>; |
cd62214d | 36 | operating-points-v2 = <&cpu_opp>; |
f875bbb4 MY |
37 | }; |
38 | ||
39 | cpu@2 { | |
40 | device_type = "cpu"; | |
41 | compatible = "arm,cortex-a9"; | |
42 | reg = <2>; | |
cd62214d | 43 | clocks = <&sys_clk 32>; |
52159d27 | 44 | enable-method = "psci"; |
4e1f81d4 | 45 | next-level-cache = <&l2>; |
cd62214d | 46 | operating-points-v2 = <&cpu_opp>; |
f875bbb4 MY |
47 | }; |
48 | ||
49 | cpu@3 { | |
50 | device_type = "cpu"; | |
51 | compatible = "arm,cortex-a9"; | |
52 | reg = <3>; | |
cd62214d | 53 | clocks = <&sys_clk 32>; |
52159d27 | 54 | enable-method = "psci"; |
4e1f81d4 | 55 | next-level-cache = <&l2>; |
cd62214d | 56 | operating-points-v2 = <&cpu_opp>; |
f875bbb4 MY |
57 | }; |
58 | }; | |
59 | ||
cd62214d MY |
60 | cpu_opp: opp_table { |
61 | compatible = "operating-points-v2"; | |
62 | opp-shared; | |
63 | ||
4e7f8de4 | 64 | opp-100000000 { |
cd62214d MY |
65 | opp-hz = /bits/ 64 <100000000>; |
66 | clock-latency-ns = <300>; | |
67 | }; | |
4e7f8de4 | 68 | opp-150000000 { |
cd62214d MY |
69 | opp-hz = /bits/ 64 <150000000>; |
70 | clock-latency-ns = <300>; | |
71 | }; | |
4e7f8de4 | 72 | opp-200000000 { |
cd62214d MY |
73 | opp-hz = /bits/ 64 <200000000>; |
74 | clock-latency-ns = <300>; | |
75 | }; | |
4e7f8de4 | 76 | opp-300000000 { |
cd62214d MY |
77 | opp-hz = /bits/ 64 <300000000>; |
78 | clock-latency-ns = <300>; | |
79 | }; | |
4e7f8de4 | 80 | opp-400000000 { |
cd62214d MY |
81 | opp-hz = /bits/ 64 <400000000>; |
82 | clock-latency-ns = <300>; | |
83 | }; | |
4e7f8de4 | 84 | opp-600000000 { |
cd62214d MY |
85 | opp-hz = /bits/ 64 <600000000>; |
86 | clock-latency-ns = <300>; | |
87 | }; | |
4e7f8de4 | 88 | opp-800000000 { |
cd62214d MY |
89 | opp-hz = /bits/ 64 <800000000>; |
90 | clock-latency-ns = <300>; | |
91 | }; | |
4e7f8de4 | 92 | opp-1200000000 { |
cd62214d MY |
93 | opp-hz = /bits/ 64 <1200000000>; |
94 | clock-latency-ns = <300>; | |
95 | }; | |
96 | }; | |
97 | ||
98 | psci { | |
99 | compatible = "arm,psci-0.2"; | |
100 | method = "smc"; | |
101 | }; | |
102 | ||
f875bbb4 | 103 | clocks { |
cd62214d MY |
104 | refclk: ref { |
105 | compatible = "fixed-clock"; | |
106 | #clock-cells = <0>; | |
107 | clock-frequency = <25000000>; | |
108 | }; | |
109 | ||
f875bbb4 MY |
110 | arm_timer_clk: arm_timer_clk { |
111 | #clock-cells = <0>; | |
112 | compatible = "fixed-clock"; | |
113 | clock-frequency = <50000000>; | |
114 | }; | |
f875bbb4 MY |
115 | }; |
116 | ||
cd62214d MY |
117 | soc { |
118 | compatible = "simple-bus"; | |
119 | #address-cells = <1>; | |
120 | #size-cells = <1>; | |
121 | ranges; | |
122 | interrupt-parent = <&intc>; | |
cd62214d MY |
123 | |
124 | l2: l2-cache@500c0000 { | |
125 | compatible = "socionext,uniphier-system-cache"; | |
126 | reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, | |
127 | <0x506c0000 0x400>; | |
128 | interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>; | |
129 | cache-unified; | |
130 | cache-size = <(1280 * 1024)>; | |
131 | cache-sets = <512>; | |
132 | cache-line-size = <128>; | |
133 | cache-level = <2>; | |
134 | }; | |
595dc1e1 | 135 | |
cd62214d MY |
136 | serial0: serial@54006800 { |
137 | compatible = "socionext,uniphier-uart"; | |
138 | status = "disabled"; | |
139 | reg = <0x54006800 0x40>; | |
140 | interrupts = <0 33 4>; | |
141 | pinctrl-names = "default"; | |
142 | pinctrl-0 = <&pinctrl_uart0>; | |
143 | clocks = <&peri_clk 0>; | |
144 | clock-frequency = <88900000>; | |
145 | }; | |
595dc1e1 | 146 | |
cd62214d MY |
147 | serial1: serial@54006900 { |
148 | compatible = "socionext,uniphier-uart"; | |
149 | status = "disabled"; | |
150 | reg = <0x54006900 0x40>; | |
151 | interrupts = <0 35 4>; | |
152 | pinctrl-names = "default"; | |
153 | pinctrl-0 = <&pinctrl_uart1>; | |
154 | clocks = <&peri_clk 1>; | |
155 | clock-frequency = <88900000>; | |
156 | }; | |
595dc1e1 | 157 | |
cd62214d MY |
158 | serial2: serial@54006a00 { |
159 | compatible = "socionext,uniphier-uart"; | |
160 | status = "disabled"; | |
161 | reg = <0x54006a00 0x40>; | |
162 | interrupts = <0 37 4>; | |
163 | pinctrl-names = "default"; | |
164 | pinctrl-0 = <&pinctrl_uart2>; | |
165 | clocks = <&peri_clk 2>; | |
166 | clock-frequency = <88900000>; | |
167 | }; | |
595dc1e1 | 168 | |
cd62214d MY |
169 | serial3: serial@54006b00 { |
170 | compatible = "socionext,uniphier-uart"; | |
171 | status = "disabled"; | |
172 | reg = <0x54006b00 0x40>; | |
173 | interrupts = <0 177 4>; | |
174 | pinctrl-names = "default"; | |
175 | pinctrl-0 = <&pinctrl_uart3>; | |
176 | clocks = <&peri_clk 3>; | |
177 | clock-frequency = <88900000>; | |
178 | }; | |
595dc1e1 | 179 | |
0f72b74b | 180 | gpio: gpio@55000000 { |
cd62214d | 181 | compatible = "socionext,uniphier-gpio"; |
0f72b74b MY |
182 | reg = <0x55000000 0x200>; |
183 | interrupt-parent = <&aidet>; | |
184 | interrupt-controller; | |
185 | #interrupt-cells = <2>; | |
cd62214d MY |
186 | gpio-controller; |
187 | #gpio-cells = <2>; | |
0f72b74b MY |
188 | gpio-ranges = <&pinctrl 0 0 0>, |
189 | <&pinctrl 96 0 0>; | |
190 | gpio-ranges-group-names = "gpio_range0", | |
191 | "gpio_range1"; | |
192 | ngpios = <232>; | |
cd62214d | 193 | }; |
f875bbb4 | 194 | |
cd62214d MY |
195 | i2c0: i2c@58780000 { |
196 | compatible = "socionext,uniphier-fi2c"; | |
197 | status = "disabled"; | |
198 | reg = <0x58780000 0x80>; | |
199 | #address-cells = <1>; | |
200 | #size-cells = <0>; | |
201 | interrupts = <0 41 4>; | |
202 | pinctrl-names = "default"; | |
203 | pinctrl-0 = <&pinctrl_i2c0>; | |
7317a940 | 204 | clocks = <&peri_clk 4>; |
cd62214d MY |
205 | clock-frequency = <100000>; |
206 | }; | |
f875bbb4 | 207 | |
cd62214d MY |
208 | i2c1: i2c@58781000 { |
209 | compatible = "socionext,uniphier-fi2c"; | |
210 | status = "disabled"; | |
211 | reg = <0x58781000 0x80>; | |
212 | #address-cells = <1>; | |
213 | #size-cells = <0>; | |
214 | interrupts = <0 42 4>; | |
215 | pinctrl-names = "default"; | |
216 | pinctrl-0 = <&pinctrl_i2c1>; | |
7317a940 | 217 | clocks = <&peri_clk 5>; |
cd62214d MY |
218 | clock-frequency = <100000>; |
219 | }; | |
f875bbb4 | 220 | |
cd62214d MY |
221 | i2c2: i2c@58782000 { |
222 | compatible = "socionext,uniphier-fi2c"; | |
223 | status = "disabled"; | |
224 | reg = <0x58782000 0x80>; | |
225 | #address-cells = <1>; | |
226 | #size-cells = <0>; | |
227 | interrupts = <0 43 4>; | |
228 | pinctrl-names = "default"; | |
229 | pinctrl-0 = <&pinctrl_i2c2>; | |
7317a940 | 230 | clocks = <&peri_clk 6>; |
cd62214d MY |
231 | clock-frequency = <100000>; |
232 | }; | |
f875bbb4 | 233 | |
cd62214d MY |
234 | i2c3: i2c@58783000 { |
235 | compatible = "socionext,uniphier-fi2c"; | |
236 | status = "disabled"; | |
237 | reg = <0x58783000 0x80>; | |
238 | #address-cells = <1>; | |
239 | #size-cells = <0>; | |
240 | interrupts = <0 44 4>; | |
241 | pinctrl-names = "default"; | |
242 | pinctrl-0 = <&pinctrl_i2c3>; | |
7317a940 | 243 | clocks = <&peri_clk 7>; |
cd62214d MY |
244 | clock-frequency = <100000>; |
245 | }; | |
c7f94eec | 246 | |
cd62214d MY |
247 | /* chip-internal connection for DMD */ |
248 | i2c4: i2c@58784000 { | |
249 | compatible = "socionext,uniphier-fi2c"; | |
250 | reg = <0x58784000 0x80>; | |
251 | #address-cells = <1>; | |
252 | #size-cells = <0>; | |
253 | interrupts = <0 45 4>; | |
7317a940 | 254 | clocks = <&peri_clk 8>; |
cd62214d MY |
255 | clock-frequency = <400000>; |
256 | }; | |
c7f94eec | 257 | |
cd62214d MY |
258 | /* chip-internal connection for STM */ |
259 | i2c5: i2c@58785000 { | |
260 | compatible = "socionext,uniphier-fi2c"; | |
261 | reg = <0x58785000 0x80>; | |
262 | #address-cells = <1>; | |
263 | #size-cells = <0>; | |
264 | interrupts = <0 25 4>; | |
7317a940 | 265 | clocks = <&peri_clk 9>; |
cd62214d MY |
266 | clock-frequency = <400000>; |
267 | }; | |
1013aef3 | 268 | |
cd62214d MY |
269 | /* chip-internal connection for HDMI */ |
270 | i2c6: i2c@58786000 { | |
271 | compatible = "socionext,uniphier-fi2c"; | |
272 | reg = <0x58786000 0x80>; | |
273 | #address-cells = <1>; | |
274 | #size-cells = <0>; | |
275 | interrupts = <0 26 4>; | |
7317a940 | 276 | clocks = <&peri_clk 10>; |
cd62214d MY |
277 | clock-frequency = <400000>; |
278 | }; | |
f875bbb4 | 279 | |
cd62214d MY |
280 | system_bus: system-bus@58c00000 { |
281 | compatible = "socionext,uniphier-system-bus"; | |
282 | status = "disabled"; | |
283 | reg = <0x58c00000 0x400>; | |
284 | #address-cells = <2>; | |
285 | #size-cells = <1>; | |
286 | pinctrl-names = "default"; | |
287 | pinctrl-0 = <&pinctrl_system_bus>; | |
288 | }; | |
f875bbb4 | 289 | |
abb6ac25 | 290 | smpctrl@59801000 { |
cd62214d MY |
291 | compatible = "socionext,uniphier-smpctrl"; |
292 | reg = <0x59801000 0x400>; | |
293 | }; | |
cc336095 | 294 | |
cd62214d MY |
295 | sdctrl@59810000 { |
296 | compatible = "socionext,uniphier-pxs2-sdctrl", | |
297 | "simple-mfd", "syscon"; | |
6c9e46ef | 298 | reg = <0x59810000 0x400>; |
cd62214d MY |
299 | |
300 | sd_clk: clock { | |
301 | compatible = "socionext,uniphier-pxs2-sd-clock"; | |
302 | #clock-cells = <1>; | |
303 | }; | |
304 | ||
305 | sd_rst: reset { | |
306 | compatible = "socionext,uniphier-pxs2-sd-reset"; | |
307 | #reset-cells = <1>; | |
308 | }; | |
309 | }; | |
f875bbb4 | 310 | |
cd62214d MY |
311 | perictrl@59820000 { |
312 | compatible = "socionext,uniphier-pxs2-perictrl", | |
313 | "simple-mfd", "syscon"; | |
314 | reg = <0x59820000 0x200>; | |
2610b136 | 315 | |
cd62214d MY |
316 | peri_clk: clock { |
317 | compatible = "socionext,uniphier-pxs2-peri-clock"; | |
318 | #clock-cells = <1>; | |
319 | }; | |
2610b136 | 320 | |
cd62214d MY |
321 | peri_rst: reset { |
322 | compatible = "socionext,uniphier-pxs2-peri-reset"; | |
323 | #reset-cells = <1>; | |
324 | }; | |
325 | }; | |
f875bbb4 | 326 | |
cd62214d MY |
327 | emmc: sdhc@5a000000 { |
328 | compatible = "socionext,uniphier-sdhc"; | |
329 | status = "disabled"; | |
330 | reg = <0x5a000000 0x800>; | |
331 | interrupts = <0 78 4>; | |
332 | pinctrl-names = "default"; | |
333 | pinctrl-0 = <&pinctrl_emmc>; | |
334 | clocks = <&sd_clk 1>; | |
335 | reset-names = "host"; | |
336 | resets = <&sd_rst 1>; | |
337 | bus-width = <8>; | |
338 | non-removable; | |
339 | cap-mmc-highspeed; | |
340 | cap-mmc-hw-reset; | |
341 | no-3-3-v; | |
342 | }; | |
35343a26 | 343 | |
cd62214d MY |
344 | sd: sdhc@5a400000 { |
345 | compatible = "socionext,uniphier-sdhc"; | |
346 | status = "disabled"; | |
347 | reg = <0x5a400000 0x800>; | |
348 | interrupts = <0 76 4>; | |
349 | pinctrl-names = "default", "1.8v"; | |
350 | pinctrl-0 = <&pinctrl_sd>; | |
351 | pinctrl-1 = <&pinctrl_sd_1v8>; | |
352 | clocks = <&sd_clk 0>; | |
353 | reset-names = "host"; | |
354 | resets = <&sd_rst 0>; | |
355 | bus-width = <4>; | |
356 | cap-sd-highspeed; | |
357 | sd-uhs-sdr12; | |
358 | sd-uhs-sdr25; | |
359 | sd-uhs-sdr50; | |
360 | }; | |
35343a26 | 361 | |
cd62214d MY |
362 | soc-glue@5f800000 { |
363 | compatible = "socionext,uniphier-pxs2-soc-glue", | |
364 | "simple-mfd", "syscon"; | |
365 | reg = <0x5f800000 0x2000>; | |
aa37aba1 | 366 | |
cd62214d MY |
367 | pinctrl: pinctrl { |
368 | compatible = "socionext,uniphier-pxs2-pinctrl"; | |
cd62214d MY |
369 | }; |
370 | }; | |
9fbb2f7e | 371 | |
6c9e46ef MY |
372 | aidet: aidet@5fc20000 { |
373 | compatible = "socionext,uniphier-pxs2-aidet"; | |
cd62214d | 374 | reg = <0x5fc20000 0x200>; |
6c9e46ef MY |
375 | interrupt-controller; |
376 | #interrupt-cells = <2>; | |
cd62214d | 377 | }; |
233812a6 | 378 | |
cd62214d MY |
379 | timer@60000200 { |
380 | compatible = "arm,cortex-a9-global-timer"; | |
381 | reg = <0x60000200 0x20>; | |
382 | interrupts = <1 11 0xf04>; | |
383 | clocks = <&arm_timer_clk>; | |
384 | }; | |
385 | ||
386 | timer@60000600 { | |
387 | compatible = "arm,cortex-a9-twd-timer"; | |
388 | reg = <0x60000600 0x20>; | |
389 | interrupts = <1 13 0xf04>; | |
390 | clocks = <&arm_timer_clk>; | |
391 | }; | |
392 | ||
393 | intc: interrupt-controller@60001000 { | |
394 | compatible = "arm,cortex-a9-gic"; | |
395 | reg = <0x60001000 0x1000>, | |
396 | <0x60000100 0x100>; | |
397 | #interrupt-cells = <3>; | |
398 | interrupt-controller; | |
399 | }; | |
400 | ||
401 | sysctrl@61840000 { | |
402 | compatible = "socionext,uniphier-pxs2-sysctrl", | |
403 | "simple-mfd", "syscon"; | |
7317a940 | 404 | reg = <0x61840000 0x10000>; |
cd62214d MY |
405 | |
406 | sys_clk: clock { | |
407 | compatible = "socionext,uniphier-pxs2-clock"; | |
408 | #clock-cells = <1>; | |
409 | }; | |
35343a26 | 410 | |
cd62214d MY |
411 | sys_rst: reset { |
412 | compatible = "socionext,uniphier-pxs2-reset"; | |
413 | #reset-cells = <1>; | |
414 | }; | |
415 | }; | |
416 | ||
417 | usb0: usb@65b00000 { | |
418 | compatible = "socionext,uniphier-pxs2-dwc3"; | |
419 | status = "disabled"; | |
420 | reg = <0x65b00000 0x1000>; | |
421 | #address-cells = <1>; | |
422 | #size-cells = <1>; | |
423 | ranges; | |
424 | pinctrl-names = "default"; | |
425 | pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>; | |
426 | dwc3@65a00000 { | |
427 | compatible = "snps,dwc3"; | |
428 | reg = <0x65a00000 0x10000>; | |
429 | interrupts = <0 134 4>; | |
3444d1d4 | 430 | dr_mode = "host"; |
cd62214d MY |
431 | tx-fifo-resize; |
432 | }; | |
433 | }; | |
434 | ||
435 | usb1: usb@65d00000 { | |
436 | compatible = "socionext,uniphier-pxs2-dwc3"; | |
437 | status = "disabled"; | |
438 | reg = <0x65d00000 0x1000>; | |
439 | #address-cells = <1>; | |
440 | #size-cells = <1>; | |
441 | ranges; | |
442 | pinctrl-names = "default"; | |
443 | pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>; | |
444 | dwc3@65c00000 { | |
445 | compatible = "snps,dwc3"; | |
446 | reg = <0x65c00000 0x10000>; | |
447 | interrupts = <0 137 4>; | |
3444d1d4 | 448 | dr_mode = "host"; |
cd62214d MY |
449 | tx-fifo-resize; |
450 | }; | |
451 | }; | |
452 | ||
453 | nand: nand@68000000 { | |
4e7f8de4 | 454 | compatible = "socionext,uniphier-denali-nand-v5b"; |
cd62214d MY |
455 | status = "disabled"; |
456 | reg-names = "nand_data", "denali_reg"; | |
457 | reg = <0x68000000 0x20>, <0x68100000 0x1000>; | |
458 | interrupts = <0 65 4>; | |
459 | pinctrl-names = "default"; | |
6c9e46ef | 460 | pinctrl-0 = <&pinctrl_nand2cs>; |
cd62214d | 461 | clocks = <&sys_clk 2>; |
cd62214d MY |
462 | }; |
463 | }; | |
233812a6 | 464 | }; |
cd62214d | 465 | |
6c9e46ef | 466 | #include "uniphier-pinctrl.dtsi" |