[people/ms/u-boot.git] / arch / arm / dts / uniphier-sld3.dtsi

/*
 * Device Tree Source for UniPhier sLD3 SoC
 *
 * Copyright (C) 2015-2016 Socionext Inc.
 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 *
 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 */

/ {
	compatible = "socionext,uniphier-sld3";
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
			enable-method = "psci";
			next-level-cache = <&l2>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
			enable-method = "psci";
			next-level-cache = <&l2>;
		};
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	clocks {
		refclk: ref {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <24576000>;
		};

		arm_timer_clk: arm_timer_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <50000000>;
		};
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		interrupt-parent = <&intc>;
		u-boot,dm-pre-reloc;

		timer@20000200 {
			compatible = "arm,cortex-a9-global-timer";
			reg = <0x20000200 0x20>;
			interrupts = <1 11 0x304>;
			clocks = <&arm_timer_clk>;
		};

		timer@20000600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0x20000600 0x20>;
			interrupts = <1 13 0x304>;
			clocks = <&arm_timer_clk>;
		};

		intc: interrupt-controller@20001000 {
			compatible = "arm,cortex-a9-gic";
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0x20001000 0x1000>,
			      <0x20000100 0x100>;
		};

		l2: l2-cache@500c0000 {
			compatible = "socionext,uniphier-system-cache";
			reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
			      <0x506c0000 0x400>;
			interrupts = <0 174 4>, <0 175 4>;
			cache-unified;
			cache-size = <(512 * 1024)>;
			cache-sets = <256>;
			cache-line-size = <128>;
			cache-level = <2>;
		};

		serial0: serial@54006800 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006800 0x40>;
			interrupts = <0 33 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart0>;
			clocks = <&sys_clk 0>;
			clock-frequency = <36864000>;
		};

		serial1: serial@54006900 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006900 0x40>;
			interrupts = <0 35 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart1>;
			clocks = <&sys_clk 0>;
			clock-frequency = <36864000>;
		};

		serial2: serial@54006a00 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006a00 0x40>;
			interrupts = <0 37 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart2>;
			clocks = <&sys_clk 0>;
			clock-frequency = <36864000>;
		};

		port0x: gpio@55000008 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000008 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port1x: gpio@55000010 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000010 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port2x: gpio@55000018 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000018 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port3x: gpio@55000020 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000020 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port4: gpio@55000028 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000028 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port5x: gpio@55000030 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000030 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port6x: gpio@55000038 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000038 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port7x: gpio@55000040 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000040 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port8x: gpio@55000048 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000048 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port9x: gpio@55000050 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000050 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port10x: gpio@55000058 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000058 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port11x: gpio@55000060 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000060 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port12x: gpio@55000068 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000068 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port13x: gpio@55000070 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000070 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port14x: gpio@55000078 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000078 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port16x: gpio@55000088 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000088 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		i2c0: i2c@58400000 {
			compatible = "socionext,uniphier-i2c";
			status = "disabled";
			reg = <0x58400000 0x40>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 41 1>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c0>;
			clocks = <&sys_clk 1>;
			clock-frequency = <100000>;
		};

		i2c1: i2c@58480000 {
			compatible = "socionext,uniphier-i2c";
			status = "disabled";
			reg = <0x58480000 0x40>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 42 1>;
			clocks = <&sys_clk 1>;
			clock-frequency = <100000>;
		};

		i2c2: i2c@58500000 {
			compatible = "socionext,uniphier-i2c";
			status = "disabled";
			reg = <0x58500000 0x40>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 43 1>;
			clocks = <&sys_clk 1>;
			clock-frequency = <100000>;
		};

		i2c3: i2c@58580000 {
			compatible = "socionext,uniphier-i2c";
			status = "disabled";
			reg = <0x58580000 0x40>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 44 1>;
			clocks = <&sys_clk 1>;
			clock-frequency = <100000>;
		};

		/* chip-internal connection for DMD */
		i2c4: i2c@58600000 {
			compatible = "socionext,uniphier-i2c";
			reg = <0x58600000 0x40>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 45 1>;
			clocks = <&sys_clk 1>;
			clock-frequency = <400000>;
		};

		system_bus: system-bus@58c00000 {
			compatible = "socionext,uniphier-system-bus";
			status = "disabled";
			reg = <0x58c00000 0x400>;
			#address-cells = <2>;
			#size-cells = <1>;
		};

		smpctrl@59801000 {
			compatible = "socionext,uniphier-smpctrl";
			reg = <0x59801000 0x400>;
		};

		mioctrl@59810000 {
			compatible = "socionext,uniphier-sld3-mioctrl",
				     "simple-mfd", "syscon";
			reg = <0x59810000 0x800>;
			u-boot,dm-pre-reloc;

			mio_clk: clock {
				compatible = "socionext,uniphier-sld3-mio-clock";
				#clock-cells = <1>;
				u-boot,dm-pre-reloc;
			};

			mio_rst: reset {
				compatible = "socionext,uniphier-sld3-mio-reset";
				#reset-cells = <1>;
			};
		};

		emmc: sdhc@5a400000 {
			compatible = "socionext,uniphier-sdhc";
			status = "disabled";
			reg = <0x5a400000 0x200>;
			interrupts = <0 78 4>;
			pinctrl-names = "default", "1.8v";
			pinctrl-0 = <&pinctrl_emmc>;
			pinctrl-1 = <&pinctrl_emmc_1v8>;
			clocks = <&mio_clk 1>;
			reset-names = "host", "bridge";
			resets = <&mio_rst 1>, <&mio_rst 4>;
			bus-width = <8>;
			non-removable;
			cap-mmc-highspeed;
			cap-mmc-hw-reset;
		};

		sd: sdhc@5a500000 {
			compatible = "socionext,uniphier-sdhc";
			status = "disabled";
			reg = <0x5a500000 0x200>;
			interrupts = <0 76 4>;
			pinctrl-names = "default", "1.8v";
			pinctrl-0 = <&pinctrl_sd>;
			pinctrl-1 = <&pinctrl_sd_1v8>;
			clocks = <&mio_clk 0>;
			reset-names = "host", "bridge";
			resets = <&mio_rst 0>, <&mio_rst 3>;
			bus-width = <4>;
			cap-sd-highspeed;
			sd-uhs-sdr12;
			sd-uhs-sdr25;
			sd-uhs-sdr50;
		};

		usb0: usb@5a800100 {
			compatible = "socionext,uniphier-ehci", "generic-ehci";
			status = "disabled";
			reg = <0x5a800100 0x100>;
			interrupts = <0 80 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb0>;
			clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
				 <&mio_rst 12>;
		};

		usb1: usb@5a810100 {
			compatible = "socionext,uniphier-ehci", "generic-ehci";
			status = "disabled";
			reg = <0x5a810100 0x100>;
			interrupts = <0 81 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb1>;
			clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
				 <&mio_rst 13>;
		};

		usb2: usb@5a820100 {
			compatible = "socionext,uniphier-ehci", "generic-ehci";
			status = "disabled";
			reg = <0x5a820100 0x100>;
			interrupts = <0 82 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb2>;
			clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
				 <&mio_rst 14>;
		};

		usb3: usb@5a830100 {
			compatible = "socionext,uniphier-ehci", "generic-ehci";
			status = "disabled";
			reg = <0x5a830100 0x100>;
			interrupts = <0 83 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb3>;
			clocks = <&mio_clk 7>, <&mio_clk 11>, <&mio_clk 15>;
			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 11>,
				 <&mio_rst 15>;
		};

		soc-glue@5f800000 {
			compatible = "socionext,uniphier-sld3-soc-glue",
				     "simple-mfd", "syscon";
			reg = <0x5f800000 0x2000>;
			u-boot,dm-pre-reloc;

			pinctrl: pinctrl {
				compatible = "socionext,uniphier-sld3-pinctrl";
				u-boot,dm-pre-reloc;
			};
		};

		aidet@f1830000 {
			compatible = "simple-mfd", "syscon";
			reg = <0xf1830000 0x200>;
		};

		sysctrl@f1840000 {
			compatible = "socionext,uniphier-sld3-sysctrl",
				     "simple-mfd", "syscon";
			reg = <0xf1840000 0x10000>;

			sys_clk: clock {
				compatible = "socionext,uniphier-sld3-clock";
				#clock-cells = <1>;
			};

			sys_rst: reset {
				compatible = "socionext,uniphier-sld3-reset";
				#reset-cells = <1>;
			};
		};

		nand: nand@f8000000 {
			compatible = "socionext,uniphier-denali-nand-v5a";
			status = "disabled";
			reg-names = "nand_data", "denali_reg";
			reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
			interrupts = <0 65 4>;
			clocks = <&sys_clk 2>;
			nand-ecc-strength = <8>;
		};
	};
};

/include/ "uniphier-pinctrl.dtsi"
Commit	Line	Data
230ce30a	1	/*
52159d27	2	* Device Tree Source for UniPhier sLD3 SoC
230ce30a	3	*
52159d27 MY	4	* Copyright (C) 2015-2016 Socionext Inc.
52159d27 MY	5	* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
230ce30a	6	*
d9403001	7	* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
230ce30a MY	8	*/
230ce30a MY	9
230ce30a	10	/ {
52159d27	11	compatible = "socionext,uniphier-sld3";
f16eda96 MY	12	#address-cells = <1>;
f16eda96 MY	13	#size-cells = <1>;
230ce30a MY	14
	15	cpus {
	16	#address-cells = <1>;
	17	#size-cells = <0>;
	18
	19	cpu@0 {
	20	device_type = "cpu";
	21	compatible = "arm,cortex-a9";
	22	reg = <0>;
52159d27 MY	23	enable-method = "psci";
52159d27 MY	24	next-level-cache = <&l2>;
230ce30a MY	25	};
	26
	27	cpu@1 {
	28	device_type = "cpu";
	29	compatible = "arm,cortex-a9";
	30	reg = <1>;
52159d27 MY	31	enable-method = "psci";
52159d27 MY	32	next-level-cache = <&l2>;
230ce30a MY	33	};
	34	};
	35
52159d27 MY	36	psci {
	37	compatible = "arm,psci-0.2";
	38	method = "smc";
	39	};
	40
edcfaeb8	41	clocks {
cc336095 MY	42	refclk: ref {
	43	#clock-cells = <0>;
	44	compatible = "fixed-clock";
	45	clock-frequency = <24576000>;
	46	};
	47
edcfaeb8 MY	48	arm_timer_clk: arm_timer_clk {
	49	#clock-cells = <0>;
	50	compatible = "fixed-clock";
	51	clock-frequency = <50000000>;
	52	};
	53	};
	54
230ce30a MY	55	soc {
	56	compatible = "simple-bus";
	57	#address-cells = <1>;
	58	#size-cells = <1>;
	59	ranges;
edcfaeb8	60	interrupt-parent = <&intc>;
f0633533	61	u-boot,dm-pre-reloc;
edcfaeb8	62
edcfaeb8 MY	63	timer@20000200 {
	64	compatible = "arm,cortex-a9-global-timer";
	65	reg = <0x20000200 0x20>;
	66	interrupts = <1 11 0x304>;
	67	clocks = <&arm_timer_clk>;
	68	};
	69
	70	timer@20000600 {
	71	compatible = "arm,cortex-a9-twd-timer";
	72	reg = <0x20000600 0x20>;
	73	interrupts = <1 13 0x304>;
	74	clocks = <&arm_timer_clk>;
	75	};
	76
	77	intc: interrupt-controller@20001000 {
	78	compatible = "arm,cortex-a9-gic";
	79	#interrupt-cells = <3>;
	80	interrupt-controller;
	81	reg = <0x20001000 0x1000>,
	82	<0x20000100 0x100>;
	83	};
230ce30a	84
52159d27 MY	85	l2: l2-cache@500c0000 {
	86	compatible = "socionext,uniphier-system-cache";
	87	reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
	88	<0x506c0000 0x400>;
	89	interrupts = <0 174 4>, <0 175 4>;
	90	cache-unified;
	91	cache-size = <(512 * 1024)>;
	92	cache-sets = <256>;
	93	cache-line-size = <128>;
	94	cache-level = <2>;
	95	};
	96
d243c186	97	serial0: serial@54006800 {
6462cded	98	compatible = "socionext,uniphier-uart";
230ce30a	99	status = "disabled";
d243c186 MY	100	reg = <0x54006800 0x40>;
d243c186 MY	101	interrupts = <0 33 4>;
4475c0ca MY	102	pinctrl-names = "default";
4475c0ca MY	103	pinctrl-0 = <&pinctrl_uart0>;
7317a940	104	clocks = <&sys_clk 0>;
230ce30a MY	105	clock-frequency = <36864000>;
	106	};
	107
d243c186	108	serial1: serial@54006900 {
6462cded	109	compatible = "socionext,uniphier-uart";
230ce30a	110	status = "disabled";
d243c186 MY	111	reg = <0x54006900 0x40>;
d243c186 MY	112	interrupts = <0 35 4>;
4475c0ca MY	113	pinctrl-names = "default";
4475c0ca MY	114	pinctrl-0 = <&pinctrl_uart1>;
7317a940	115	clocks = <&sys_clk 0>;
230ce30a MY	116	clock-frequency = <36864000>;
	117	};
	118
d243c186	119	serial2: serial@54006a00 {
6462cded	120	compatible = "socionext,uniphier-uart";
230ce30a	121	status = "disabled";
d243c186 MY	122	reg = <0x54006a00 0x40>;
d243c186 MY	123	interrupts = <0 37 4>;
4475c0ca MY	124	pinctrl-names = "default";
4475c0ca MY	125	pinctrl-0 = <&pinctrl_uart2>;
7317a940	126	clocks = <&sys_clk 0>;
230ce30a MY	127	clock-frequency = <36864000>;
	128	};
	129
595dc1e1 MY	130	port0x: gpio@55000008 {
	131	compatible = "socionext,uniphier-gpio";
	132	reg = <0x55000008 0x8>;
	133	gpio-controller;
	134	#gpio-cells = <2>;
	135	};
	136
	137	port1x: gpio@55000010 {
	138	compatible = "socionext,uniphier-gpio";
	139	reg = <0x55000010 0x8>;
	140	gpio-controller;
	141	#gpio-cells = <2>;
	142	};
	143
	144	port2x: gpio@55000018 {
	145	compatible = "socionext,uniphier-gpio";
	146	reg = <0x55000018 0x8>;
	147	gpio-controller;
	148	#gpio-cells = <2>;
	149	};
	150
	151	port3x: gpio@55000020 {
	152	compatible = "socionext,uniphier-gpio";
	153	reg = <0x55000020 0x8>;
	154	gpio-controller;
	155	#gpio-cells = <2>;
	156	};
	157
	158	port4: gpio@55000028 {
	159	compatible = "socionext,uniphier-gpio";
	160	reg = <0x55000028 0x8>;
	161	gpio-controller;
	162	#gpio-cells = <2>;
	163	};
	164
	165	port5x: gpio@55000030 {
	166	compatible = "socionext,uniphier-gpio";
	167	reg = <0x55000030 0x8>;
	168	gpio-controller;
	169	#gpio-cells = <2>;
	170	};
	171
	172	port6x: gpio@55000038 {
	173	compatible = "socionext,uniphier-gpio";
	174	reg = <0x55000038 0x8>;
	175	gpio-controller;
	176	#gpio-cells = <2>;
	177	};
	178
	179	port7x: gpio@55000040 {
	180	compatible = "socionext,uniphier-gpio";
	181	reg = <0x55000040 0x8>;
	182	gpio-controller;
	183	#gpio-cells = <2>;
	184	};
	185
	186	port8x: gpio@55000048 {
	187	compatible = "socionext,uniphier-gpio";
	188	reg = <0x55000048 0x8>;
	189	gpio-controller;
	190	#gpio-cells = <2>;
	191	};
	192
	193	port9x: gpio@55000050 {
194	compatible = "socionext,uniphier-gpio";
195	reg = <0x55000050 0x8>;
196	gpio-controller;
197	#gpio-cells = <2>;
198	};
199
200	port10x: gpio@55000058 {
201	compatible = "socionext,uniphier-gpio";
202	reg = <0x55000058 0x8>;
203	gpio-controller;
204	#gpio-cells = <2>;
205	};
206
207	port11x: gpio@55000060 {
208	compatible = "socionext,uniphier-gpio";
209	reg = <0x55000060 0x8>;
210	gpio-controller;
211	#gpio-cells = <2>;
212	};
213
214	port12x: gpio@55000068 {
215	compatible = "socionext,uniphier-gpio";
216	reg = <0x55000068 0x8>;
217	gpio-controller;
218	#gpio-cells = <2>;
219	};
220
221	port13x: gpio@55000070 {
222	compatible = "socionext,uniphier-gpio";
223	reg = <0x55000070 0x8>;
224	gpio-controller;
225	#gpio-cells = <2>;
226	};
227
228	port14x: gpio@55000078 {
229	compatible = "socionext,uniphier-gpio";
230	reg = <0x55000078 0x8>;
231	gpio-controller;
232	#gpio-cells = <2>;
233	};
234
235	port16x: gpio@55000088 {
236	compatible = "socionext,uniphier-gpio";
237	reg = <0x55000088 0x8>;
238	gpio-controller;
239	#gpio-cells = <2>;
240	};
241
230ce30a	242	i2c0: i2c@58400000 {
6462cded	243	compatible = "socionext,uniphier-i2c";
d243c186 MY	244	status = "disabled";
d243c186 MY	245	reg = <0x58400000 0x40>;
230ce30a MY	246	#address-cells = <1>;
230ce30a MY	247	#size-cells = <0>;
d243c186	248	interrupts = <0 41 1>;
4475c0ca MY	249	pinctrl-names = "default";
4475c0ca MY	250	pinctrl-0 = <&pinctrl_i2c0>;
cd62214d	251	clocks = <&sys_clk 1>;
230ce30a	252	clock-frequency = <100000>;
230ce30a MY	253	};
	254
	255	i2c1: i2c@58480000 {
6462cded	256	compatible = "socionext,uniphier-i2c";
d243c186 MY	257	status = "disabled";
d243c186 MY	258	reg = <0x58480000 0x40>;
230ce30a MY	259	#address-cells = <1>;
230ce30a MY	260	#size-cells = <0>;
d243c186	261	interrupts = <0 42 1>;
cd62214d	262	clocks = <&sys_clk 1>;
230ce30a	263	clock-frequency = <100000>;
230ce30a MY	264	};
	265
	266	i2c2: i2c@58500000 {
6462cded	267	compatible = "socionext,uniphier-i2c";
d243c186 MY	268	status = "disabled";
d243c186 MY	269	reg = <0x58500000 0x40>;
230ce30a MY	270	#address-cells = <1>;
230ce30a MY	271	#size-cells = <0>;
d243c186	272	interrupts = <0 43 1>;
cd62214d	273	clocks = <&sys_clk 1>;
230ce30a	274	clock-frequency = <100000>;
230ce30a MY	275	};
	276
	277	i2c3: i2c@58580000 {
6462cded	278	compatible = "socionext,uniphier-i2c";
d243c186 MY	279	status = "disabled";
d243c186 MY	280	reg = <0x58580000 0x40>;
230ce30a MY	281	#address-cells = <1>;
230ce30a MY	282	#size-cells = <0>;
d243c186	283	interrupts = <0 44 1>;
cd62214d	284	clocks = <&sys_clk 1>;
230ce30a	285	clock-frequency = <100000>;
230ce30a MY	286	};
230ce30a MY	287
d243c186	288	/* chip-internal connection for DMD */
f1d79453	289	i2c4: i2c@58600000 {
d243c186 MY	290	compatible = "socionext,uniphier-i2c";
d243c186 MY	291	reg = <0x58600000 0x40>;
f1d79453 MY	292	#address-cells = <1>;
f1d79453 MY	293	#size-cells = <0>;
d243c186	294	interrupts = <0 45 1>;
cd62214d	295	clocks = <&sys_clk 1>;
f1d79453	296	clock-frequency = <400000>;
f1d79453 MY	297	};
f1d79453 MY	298
0f5fb8ce MY	299	system_bus: system-bus@58c00000 {
0f5fb8ce MY	300	compatible = "socionext,uniphier-system-bus";
52159d27	301	status = "disabled";
0f5fb8ce MY	302	reg = <0x58c00000 0x400>;
	303	#address-cells = <2>;
	304	#size-cells = <1>;
	305	};
	306
abb6ac25	307	smpctrl@59801000 {
0f5fb8ce MY	308	compatible = "socionext,uniphier-smpctrl";
0f5fb8ce MY	309	reg = <0x59801000 0x400>;
edcfaeb8	310	};
aa37aba1	311
35343a26	312	mioctrl@59810000 {
7317a940	313	compatible = "socionext,uniphier-sld3-mioctrl",
35343a26	314	"simple-mfd", "syscon";
aa37aba1	315	reg = <0x59810000 0x800>;
35343a26 MY	316	u-boot,dm-pre-reloc;
	317
	318	mio_clk: clock {
	319	compatible = "socionext,uniphier-sld3-mio-clock";
	320	#clock-cells = <1>;
	321	u-boot,dm-pre-reloc;
	322	};
	323
	324	mio_rst: reset {
	325	compatible = "socionext,uniphier-sld3-mio-reset";
	326	#reset-cells = <1>;
	327	};
aa37aba1	328	};
edcfaeb8	329
c7f94eec MY	330	emmc: sdhc@5a400000 {
	331	compatible = "socionext,uniphier-sdhc";
	332	status = "disabled";
	333	reg = <0x5a400000 0x200>;
	334	interrupts = <0 78 4>;
4475c0ca MY	335	pinctrl-names = "default", "1.8v";
	336	pinctrl-0 = <&pinctrl_emmc>;
	337	pinctrl-1 = <&pinctrl_emmc_1v8>;
35343a26	338	clocks = <&mio_clk 1>;
cd62214d	339	reset-names = "host", "bridge";
52159d27	340	resets = <&mio_rst 1>, <&mio_rst 4>;
c7f94eec MY	341	bus-width = <8>;
c7f94eec MY	342	non-removable;
cd62214d MY	343	cap-mmc-highspeed;
cd62214d MY	344	cap-mmc-hw-reset;
c7f94eec MY	345	};
	346
	347	sd: sdhc@5a500000 {
	348	compatible = "socionext,uniphier-sdhc";
	349	status = "disabled";
	350	reg = <0x5a500000 0x200>;
	351	interrupts = <0 76 4>;
4475c0ca MY	352	pinctrl-names = "default", "1.8v";
	353	pinctrl-0 = <&pinctrl_sd>;
	354	pinctrl-1 = <&pinctrl_sd_1v8>;
35343a26	355	clocks = <&mio_clk 0>;
cd62214d	356	reset-names = "host", "bridge";
52159d27	357	resets = <&mio_rst 0>, <&mio_rst 3>;
c7f94eec	358	bus-width = <4>;
cd62214d MY	359	cap-sd-highspeed;
	360	sd-uhs-sdr12;
	361	sd-uhs-sdr25;
	362	sd-uhs-sdr50;
c7f94eec MY	363	};
c7f94eec MY	364
230ce30a	365	usb0: usb@5a800100 {
6462cded	366	compatible = "socionext,uniphier-ehci", "generic-ehci";
230ce30a MY	367	status = "disabled";
230ce30a MY	368	reg = <0x5a800100 0x100>;
d243c186	369	interrupts = <0 80 4>;
4475c0ca MY	370	pinctrl-names = "default";
4475c0ca MY	371	pinctrl-0 = <&pinctrl_usb0>;
52159d27 MY	372	clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
	373	resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
	374	<&mio_rst 12>;
230ce30a MY	375	};
	376
	377	usb1: usb@5a810100 {
6462cded	378	compatible = "socionext,uniphier-ehci", "generic-ehci";
230ce30a MY	379	status = "disabled";
230ce30a MY	380	reg = <0x5a810100 0x100>;
d243c186	381	interrupts = <0 81 4>;
4475c0ca MY	382	pinctrl-names = "default";
4475c0ca MY	383	pinctrl-0 = <&pinctrl_usb1>;
52159d27 MY	384	clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
	385	resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
	386	<&mio_rst 13>;
230ce30a MY	387	};
	388
	389	usb2: usb@5a820100 {
6462cded	390	compatible = "socionext,uniphier-ehci", "generic-ehci";
230ce30a MY	391	status = "disabled";
230ce30a MY	392	reg = <0x5a820100 0x100>;
d243c186	393	interrupts = <0 82 4>;
4475c0ca MY	394	pinctrl-names = "default";
4475c0ca MY	395	pinctrl-0 = <&pinctrl_usb2>;
52159d27 MY	396	clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
	397	resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
	398	<&mio_rst 14>;
230ce30a MY	399	};
	400
	401	usb3: usb@5a830100 {
6462cded	402	compatible = "socionext,uniphier-ehci", "generic-ehci";
230ce30a MY	403	status = "disabled";
230ce30a MY	404	reg = <0x5a830100 0x100>;
d243c186	405	interrupts = <0 83 4>;
4475c0ca MY	406	pinctrl-names = "default";
4475c0ca MY	407	pinctrl-0 = <&pinctrl_usb3>;
52159d27 MY	408	clocks = <&mio_clk 7>, <&mio_clk 11>, <&mio_clk 15>;
	409	resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 11>,
	410	<&mio_rst 15>;
230ce30a MY	411	};
230ce30a MY	412
4475c0ca	413	soc-glue@5f800000 {
cd62214d MY	414	compatible = "socionext,uniphier-sld3-soc-glue",
cd62214d MY	415	"simple-mfd", "syscon";
4475c0ca MY	416	reg = <0x5f800000 0x2000>;
	417	u-boot,dm-pre-reloc;
	418
	419	pinctrl: pinctrl {
	420	compatible = "socionext,uniphier-sld3-pinctrl";
	421	u-boot,dm-pre-reloc;
	422	};
	423	};
	424
1013aef3 MY	425	aidet@f1830000 {
	426	compatible = "simple-mfd", "syscon";
	427	reg = <0xf1830000 0x200>;
	428	};
	429
35343a26	430	sysctrl@f1840000 {
cd62214d	431	compatible = "socionext,uniphier-sld3-sysctrl",
35343a26	432	"simple-mfd", "syscon";
7317a940	433	reg = <0xf1840000 0x10000>;
35343a26 MY	434
	435	sys_clk: clock {
	436	compatible = "socionext,uniphier-sld3-clock";
	437	#clock-cells = <1>;
	438	};
	439
	440	sys_rst: reset {
	441	compatible = "socionext,uniphier-sld3-reset";
	442	#reset-cells = <1>;
	443	};
233812a6 MY	444	};
233812a6 MY	445
230ce30a	446	nand: nand@f8000000 {
abb6ac25	447	compatible = "socionext,uniphier-denali-nand-v5a";
cd62214d	448	status = "disabled";
230ce30a	449	reg-names = "nand_data", "denali_reg";
cd62214d MY	450	reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
	451	interrupts = <0 65 4>;
	452	clocks = <&sys_clk 2>;
	453	nand-ecc-strength = <8>;
230ce30a MY	454	};
	455	};
	456	};
4475c0ca MY	457
4475c0ca MY	458	/include/ "uniphier-pinctrl.dtsi"