[thirdparty/u-boot.git] / arch / arm / dts / uniphier-sld8.dtsi

// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier sLD8 SoC
//
// Copyright (C) 2015-2016 Socionext Inc.
//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>

#include <dt-bindings/gpio/uniphier-gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "socionext,uniphier-sld8";
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
			enable-method = "psci";
			next-level-cache = <&l2>;
		};
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	clocks {
		refclk: ref {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <25000000>;
		};

		arm_timer_clk: arm-timer {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <50000000>;
		};
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		interrupt-parent = <&intc>;

		l2: cache-controller@500c0000 {
			compatible = "socionext,uniphier-system-cache";
			reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
			      <0x506c0000 0x400>;
			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
			cache-unified;
			cache-size = <(256 * 1024)>;
			cache-sets = <256>;
			cache-line-size = <128>;
			cache-level = <2>;
		};

		spi: spi@54006000 {
			compatible = "socionext,uniphier-scssi";
			status = "disabled";
			reg = <0x54006000 0x100>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_spi0>;
			clocks = <&peri_clk 11>;
			resets = <&peri_rst 11>;
		};

		serial0: serial@54006800 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006800 0x40>;
			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart0>;
			clocks = <&peri_clk 0>;
			resets = <&peri_rst 0>;
		};

		serial1: serial@54006900 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006900 0x40>;
			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart1>;
			clocks = <&peri_clk 1>;
			resets = <&peri_rst 1>;
		};

		serial2: serial@54006a00 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006a00 0x40>;
			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart2>;
			clocks = <&peri_clk 2>;
			resets = <&peri_rst 2>;
		};

		serial3: serial@54006b00 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006b00 0x40>;
			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart3>;
			clocks = <&peri_clk 3>;
			resets = <&peri_rst 3>;
		};

		gpio: gpio@55000000 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000000 0x200>;
			interrupt-parent = <&aidet>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl 0 0 0>,
				      <&pinctrl 104 0 0>,
				      <&pinctrl 112 0 0>;
			gpio-ranges-group-names = "gpio_range0",
						  "gpio_range1",
						  "gpio_range2";
			ngpios = <136>;
			socionext,interrupt-ranges = <0 48 13>, <14 62 2>;
		};

		i2c0: i2c@58400000 {
			compatible = "socionext,uniphier-i2c";
			status = "disabled";
			reg = <0x58400000 0x40>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c0>;
			clocks = <&peri_clk 4>;
			resets = <&peri_rst 4>;
			clock-frequency = <100000>;
		};

		i2c1: i2c@58480000 {
			compatible = "socionext,uniphier-i2c";
			status = "disabled";
			reg = <0x58480000 0x40>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c1>;
			clocks = <&peri_clk 5>;
			resets = <&peri_rst 5>;
			clock-frequency = <100000>;
		};

		/* chip-internal connection for DMD */
		i2c2: i2c@58500000 {
			compatible = "socionext,uniphier-i2c";
			reg = <0x58500000 0x40>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c2>;
			clocks = <&peri_clk 6>;
			resets = <&peri_rst 6>;
			clock-frequency = <400000>;
		};

		i2c3: i2c@58580000 {
			compatible = "socionext,uniphier-i2c";
			status = "disabled";
			reg = <0x58580000 0x40>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c3>;
			clocks = <&peri_clk 7>;
			resets = <&peri_rst 7>;
			clock-frequency = <100000>;
		};

		system_bus: system-bus@58c00000 {
			compatible = "socionext,uniphier-system-bus";
			status = "disabled";
			reg = <0x58c00000 0x400>;
			#address-cells = <2>;
			#size-cells = <1>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_system_bus>;
		};

		smpctrl@59801000 {
			compatible = "socionext,uniphier-smpctrl";
			reg = <0x59801000 0x400>;
		};

		mioctrl: syscon@59810000 {
			compatible = "socionext,uniphier-sld8-mioctrl",
				     "simple-mfd", "syscon";
			reg = <0x59810000 0x800>;

			mio_clk: clock-controller {
				compatible = "socionext,uniphier-sld8-mio-clock";
				#clock-cells = <1>;
			};

			mio_rst: reset-controller {
				compatible = "socionext,uniphier-sld8-mio-reset";
				#reset-cells = <1>;
			};
		};

		syscon@59820000 {
			compatible = "socionext,uniphier-sld8-perictrl",
				     "simple-mfd", "syscon";
			reg = <0x59820000 0x200>;

			peri_clk: clock-controller {
				compatible = "socionext,uniphier-sld8-peri-clock";
				#clock-cells = <1>;
			};

			peri_rst: reset-controller {
				compatible = "socionext,uniphier-sld8-peri-reset";
				#reset-cells = <1>;
			};
		};

		dmac: dma-controller@5a000000 {
			compatible = "socionext,uniphier-mio-dmac";
			reg = <0x5a000000 0x1000>;
			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&mio_clk 7>;
			resets = <&mio_rst 7>;
			#dma-cells = <1>;
		};

		sd: mmc@5a400000 {
			compatible = "socionext,uniphier-sd-v2.91";
			status = "disabled";
			reg = <0x5a400000 0x200>;
			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default", "uhs";
			pinctrl-0 = <&pinctrl_sd>;
			pinctrl-1 = <&pinctrl_sd_uhs>;
			clocks = <&mio_clk 0>;
			reset-names = "host", "bridge";
			resets = <&mio_rst 0>, <&mio_rst 3>;
			dma-names = "rx-tx";
			dmas = <&dmac 4>;
			bus-width = <4>;
			cap-sd-highspeed;
			sd-uhs-sdr12;
			sd-uhs-sdr25;
			sd-uhs-sdr50;
			socionext,syscon-uhs-mode = <&mioctrl 0>;
		};

		emmc: mmc@5a500000 {
			compatible = "socionext,uniphier-sd-v2.91";
			status = "disabled";
			reg = <0x5a500000 0x200>;
			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_emmc>;
			clocks = <&mio_clk 1>;
			reset-names = "host", "bridge", "hw";
			resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
			dma-names = "rx-tx";
			dmas = <&dmac 6>;
			bus-width = <8>;
			cap-mmc-highspeed;
			cap-mmc-hw-reset;
			non-removable;
		};

		usb0: usb@5a800100 {
			compatible = "socionext,uniphier-ehci", "generic-ehci";
			status = "disabled";
			reg = <0x5a800100 0x100>;
			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb0>;
			clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
				 <&mio_clk 12>;
			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
				 <&mio_rst 12>;
			has-transaction-translator;
		};

		usb1: usb@5a810100 {
			compatible = "socionext,uniphier-ehci", "generic-ehci";
			status = "disabled";
			reg = <0x5a810100 0x100>;
			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb1>;
			clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
				 <&mio_clk 13>;
			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
				 <&mio_rst 13>;
			has-transaction-translator;
		};

		usb2: usb@5a820100 {
			compatible = "socionext,uniphier-ehci", "generic-ehci";
			status = "disabled";
			reg = <0x5a820100 0x100>;
			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb2>;
			clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
				 <&mio_clk 14>;
			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
				 <&mio_rst 14>;
			has-transaction-translator;
		};

		syscon@5f800000 {
			compatible = "socionext,uniphier-sld8-soc-glue",
				     "simple-mfd", "syscon";
			reg = <0x5f800000 0x2000>;

			pinctrl: pinctrl {
				compatible = "socionext,uniphier-sld8-pinctrl";
			};
		};

		syscon@5f900000 {
			compatible = "socionext,uniphier-sld8-soc-glue-debug",
				     "simple-mfd", "syscon";
			reg = <0x5f900000 0x2000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x5f900000 0x2000>;

			efuse@100 {
				compatible = "socionext,uniphier-efuse";
				reg = <0x100 0x28>;
			};

			efuse@200 {
				compatible = "socionext,uniphier-efuse";
				reg = <0x200 0x14>;
			};
		};

		timer@60000200 {
			compatible = "arm,cortex-a9-global-timer";
			reg = <0x60000200 0x20>;
			interrupts = <GIC_PPI 11
				(GIC_CPU_MASK_RAW(1) | IRQ_TYPE_LEVEL_HIGH)>;
			clocks = <&arm_timer_clk>;
		};

		timer@60000600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0x60000600 0x20>;
			interrupts = <GIC_PPI 13
				(GIC_CPU_MASK_RAW(1) | IRQ_TYPE_LEVEL_HIGH)>;
			clocks = <&arm_timer_clk>;
		};

		intc: interrupt-controller@60001000 {
			compatible = "arm,cortex-a9-gic";
			reg = <0x60001000 0x1000>,
			      <0x60000100 0x100>;
			#interrupt-cells = <3>;
			interrupt-controller;
		};

		aidet: interrupt-controller@61830000 {
			compatible = "socionext,uniphier-sld8-aidet";
			reg = <0x61830000 0x200>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		syscon@61840000 {
			compatible = "socionext,uniphier-sld8-sysctrl",
				     "simple-mfd", "syscon";
			reg = <0x61840000 0x10000>;

			sys_clk: clock-controller {
				compatible = "socionext,uniphier-sld8-clock";
				#clock-cells = <1>;
			};

			sys_rst: reset-controller {
				compatible = "socionext,uniphier-sld8-reset";
				#reset-cells = <1>;
			};
		};

		nand: nand-controller@68000000 {
			compatible = "socionext,uniphier-denali-nand-v5a";
			status = "disabled";
			reg-names = "nand_data", "denali_reg";
			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_nand2cs>;
			clock-names = "nand", "nand_x", "ecc";
			clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
			reset-names = "nand", "reg";
			resets = <&sys_rst 2>, <&sys_rst 2>;
		};
	};
};

#include "uniphier-pinctrl.dtsi"
Commit	Line	Data
3e98fc12 MY	1	// SPDX-License-Identifier: GPL-2.0+ OR MIT
	2	//
	3	// Device Tree Source for UniPhier sLD8 SoC
	4	//
	5	// Copyright (C) 2015-2016 Socionext Inc.
	6	// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
509eb678	7
b443fb42	8	#include <dt-bindings/gpio/uniphier-gpio.h>
051451ad	9	#include <dt-bindings/interrupt-controller/arm-gic.h>
b443fb42	10
509eb678	11	/ {
52159d27	12	compatible = "socionext,uniphier-sld8";
f16eda96 MY	13	#address-cells = <1>;
f16eda96 MY	14	#size-cells = <1>;
509eb678 MY	15
509eb678 MY	16	cpus {
509eb678	17	#address-cells = <1>;
f5fd7afc	18	#size-cells = <0>;
509eb678 MY	19
	20	cpu@0 {
	21	device_type = "cpu";
	22	compatible = "arm,cortex-a9";
	23	reg = <0>;
52159d27	24	enable-method = "psci";
4e1f81d4	25	next-level-cache = <&l2>;
509eb678 MY	26	};
	27	};
	28
cd62214d MY	29	psci {
	30	compatible = "arm,psci-0.2";
	31	method = "smc";
	32	};
	33
edcfaeb8	34	clocks {
cd62214d	35	refclk: ref {
edcfaeb8	36	compatible = "fixed-clock";
cd62214d MY	37	#clock-cells = <0>;
cd62214d MY	38	clock-frequency = <25000000>;
edcfaeb8	39	};
d243c186	40
b443fb42	41	arm_timer_clk: arm-timer {
d243c186 MY	42	#clock-cells = <0>;
d243c186 MY	43	compatible = "fixed-clock";
cd62214d	44	clock-frequency = <50000000>;
d243c186	45	};
edcfaeb8 MY	46	};
edcfaeb8 MY	47
cd62214d MY	48	soc {
	49	compatible = "simple-bus";
	50	#address-cells = <1>;
	51	#size-cells = <1>;
	52	ranges;
	53	interrupt-parent = <&intc>;
cd62214d	54
44ebaa8e	55	l2: cache-controller@500c0000 {
cd62214d MY	56	compatible = "socionext,uniphier-system-cache";
	57	reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
	58	<0x506c0000 0x400>;
051451ad KH	59	interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
051451ad KH	60	<GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
cd62214d MY	61	cache-unified;
	62	cache-size = <(256 * 1024)>;
	63	cache-sets = <256>;
	64	cache-line-size = <128>;
	65	cache-level = <2>;
	66	};
4e1f81d4	67
2001a81c MY	68	spi: spi@54006000 {
	69	compatible = "socionext,uniphier-scssi";
	70	status = "disabled";
	71	reg = <0x54006000 0x100>;
08520333 MY	72	#address-cells = <1>;
08520333 MY	73	#size-cells = <0>;
051451ad	74	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
2001a81c MY	75	pinctrl-names = "default";
	76	pinctrl-0 = <&pinctrl_spi0>;
	77	clocks = <&peri_clk 11>;
	78	resets = <&peri_rst 11>;
	79	};
	80
cd62214d MY	81	serial0: serial@54006800 {
	82	compatible = "socionext,uniphier-uart";
	83	status = "disabled";
	84	reg = <0x54006800 0x40>;
051451ad	85	interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
cd62214d MY	86	pinctrl-names = "default";
	87	pinctrl-0 = <&pinctrl_uart0>;
	88	clocks = <&peri_clk 0>;
b443fb42	89	resets = <&peri_rst 0>;
cd62214d	90	};
595dc1e1	91
cd62214d MY	92	serial1: serial@54006900 {
	93	compatible = "socionext,uniphier-uart";
	94	status = "disabled";
	95	reg = <0x54006900 0x40>;
051451ad	96	interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
cd62214d MY	97	pinctrl-names = "default";
	98	pinctrl-0 = <&pinctrl_uart1>;
	99	clocks = <&peri_clk 1>;
b443fb42	100	resets = <&peri_rst 1>;
cd62214d	101	};
595dc1e1	102
cd62214d MY	103	serial2: serial@54006a00 {
	104	compatible = "socionext,uniphier-uart";
	105	status = "disabled";
	106	reg = <0x54006a00 0x40>;
051451ad	107	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
cd62214d MY	108	pinctrl-names = "default";
	109	pinctrl-0 = <&pinctrl_uart2>;
	110	clocks = <&peri_clk 2>;
b443fb42	111	resets = <&peri_rst 2>;
cd62214d	112	};
595dc1e1	113
cd62214d MY	114	serial3: serial@54006b00 {
	115	compatible = "socionext,uniphier-uart";
	116	status = "disabled";
	117	reg = <0x54006b00 0x40>;
051451ad	118	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
cd62214d MY	119	pinctrl-names = "default";
	120	pinctrl-0 = <&pinctrl_uart3>;
	121	clocks = <&peri_clk 3>;
b443fb42	122	resets = <&peri_rst 3>;
cd62214d	123	};
595dc1e1	124
0f72b74b	125	gpio: gpio@55000000 {
cd62214d	126	compatible = "socionext,uniphier-gpio";
0f72b74b MY	127	reg = <0x55000000 0x200>;
	128	interrupt-parent = <&aidet>;
	129	interrupt-controller;
	130	#interrupt-cells = <2>;
cd62214d MY	131	gpio-controller;
cd62214d MY	132	#gpio-cells = <2>;
0f72b74b MY	133	gpio-ranges = <&pinctrl 0 0 0>,
	134	<&pinctrl 104 0 0>,
	135	<&pinctrl 112 0 0>;
	136	gpio-ranges-group-names = "gpio_range0",
	137	"gpio_range1",
	138	"gpio_range2";
	139	ngpios = <136>;
b443fb42	140	socionext,interrupt-ranges = <0 48 13>, <14 62 2>;
cd62214d	141	};
149c751d	142
cd62214d MY	143	i2c0: i2c@58400000 {
	144	compatible = "socionext,uniphier-i2c";
	145	status = "disabled";
	146	reg = <0x58400000 0x40>;
	147	#address-cells = <1>;
	148	#size-cells = <0>;
051451ad	149	interrupts = <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>;
cd62214d MY	150	pinctrl-names = "default";
	151	pinctrl-0 = <&pinctrl_i2c0>;
	152	clocks = <&peri_clk 4>;
b443fb42	153	resets = <&peri_rst 4>;
cd62214d MY	154	clock-frequency = <100000>;
cd62214d MY	155	};
c7f94eec	156
cd62214d MY	157	i2c1: i2c@58480000 {
	158	compatible = "socionext,uniphier-i2c";
	159	status = "disabled";
	160	reg = <0x58480000 0x40>;
	161	#address-cells = <1>;
	162	#size-cells = <0>;
051451ad	163	interrupts = <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>;
cd62214d MY	164	pinctrl-names = "default";
	165	pinctrl-0 = <&pinctrl_i2c1>;
	166	clocks = <&peri_clk 5>;
b443fb42	167	resets = <&peri_rst 5>;
cd62214d MY	168	clock-frequency = <100000>;
cd62214d MY	169	};
c7f94eec	170
cd62214d MY	171	/* chip-internal connection for DMD */
	172	i2c2: i2c@58500000 {
	173	compatible = "socionext,uniphier-i2c";
	174	reg = <0x58500000 0x40>;
	175	#address-cells = <1>;
	176	#size-cells = <0>;
051451ad	177	interrupts = <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>;
cd62214d MY	178	pinctrl-names = "default";
	179	pinctrl-0 = <&pinctrl_i2c2>;
	180	clocks = <&peri_clk 6>;
b443fb42	181	resets = <&peri_rst 6>;
cd62214d MY	182	clock-frequency = <400000>;
cd62214d MY	183	};
149c751d	184
cd62214d MY	185	i2c3: i2c@58580000 {
	186	compatible = "socionext,uniphier-i2c";
	187	status = "disabled";
	188	reg = <0x58580000 0x40>;
	189	#address-cells = <1>;
	190	#size-cells = <0>;
051451ad	191	interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>;
cd62214d MY	192	pinctrl-names = "default";
	193	pinctrl-0 = <&pinctrl_i2c3>;
	194	clocks = <&peri_clk 7>;
b443fb42	195	resets = <&peri_rst 7>;
cd62214d MY	196	clock-frequency = <100000>;
cd62214d MY	197	};
d243c186	198
cd62214d MY	199	system_bus: system-bus@58c00000 {
	200	compatible = "socionext,uniphier-system-bus";
	201	status = "disabled";
	202	reg = <0x58c00000 0x400>;
	203	#address-cells = <2>;
	204	#size-cells = <1>;
	205	pinctrl-names = "default";
	206	pinctrl-0 = <&pinctrl_system_bus>;
	207	};
1013aef3	208
abb6ac25	209	smpctrl@59801000 {
cd62214d MY	210	compatible = "socionext,uniphier-smpctrl";
	211	reg = <0x59801000 0x400>;
	212	};
f5fd7afc	213
051451ad	214	mioctrl: syscon@59810000 {
cd62214d MY	215	compatible = "socionext,uniphier-sld8-mioctrl",
	216	"simple-mfd", "syscon";
	217	reg = <0x59810000 0x800>;
cc336095	218
051451ad	219	mio_clk: clock-controller {
cd62214d MY	220	compatible = "socionext,uniphier-sld8-mio-clock";
	221	#clock-cells = <1>;
	222	};
edcfaeb8	223
051451ad	224	mio_rst: reset-controller {
cd62214d MY	225	compatible = "socionext,uniphier-sld8-mio-reset";
	226	#reset-cells = <1>;
	227	};
	228	};
edcfaeb8	229
051451ad	230	syscon@59820000 {
cd62214d MY	231	compatible = "socionext,uniphier-sld8-perictrl",
	232	"simple-mfd", "syscon";
	233	reg = <0x59820000 0x200>;
edcfaeb8	234
051451ad	235	peri_clk: clock-controller {
cd62214d MY	236	compatible = "socionext,uniphier-sld8-peri-clock";
	237	#clock-cells = <1>;
	238	};
d243c186	239
051451ad	240	peri_rst: reset-controller {
cd62214d MY	241	compatible = "socionext,uniphier-sld8-peri-reset";
	242	#reset-cells = <1>;
	243	};
	244	};
35343a26	245
cd33feda MY	246	dmac: dma-controller@5a000000 {
	247	compatible = "socionext,uniphier-mio-dmac";
	248	reg = <0x5a000000 0x1000>;
051451ad KH	249	interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
	250	<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
	251	<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
	252	<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
	253	<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
	254	<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
	255	<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
cd33feda MY	256	clocks = <&mio_clk 7>;
	257	resets = <&mio_rst 7>;
	258	#dma-cells = <1>;
	259	};
	260
44ebaa8e	261	sd: mmc@5a400000 {
c3ab1e11	262	compatible = "socionext,uniphier-sd-v2.91";
cd62214d MY	263	status = "disabled";
cd62214d MY	264	reg = <0x5a400000 0x200>;
051451ad	265	interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
c3ab1e11	266	pinctrl-names = "default", "uhs";
cd62214d	267	pinctrl-0 = <&pinctrl_sd>;
c3ab1e11	268	pinctrl-1 = <&pinctrl_sd_uhs>;
cd62214d MY	269	clocks = <&mio_clk 0>;
	270	reset-names = "host", "bridge";
	271	resets = <&mio_rst 0>, <&mio_rst 3>;
cd33feda MY	272	dma-names = "rx-tx";
cd33feda MY	273	dmas = <&dmac 4>;
cd62214d MY	274	bus-width = <4>;
	275	cap-sd-highspeed;
	276	sd-uhs-sdr12;
	277	sd-uhs-sdr25;
	278	sd-uhs-sdr50;
051451ad	279	socionext,syscon-uhs-mode = <&mioctrl 0>;
cd62214d	280	};
35343a26	281
44ebaa8e	282	emmc: mmc@5a500000 {
c3ab1e11	283	compatible = "socionext,uniphier-sd-v2.91";
cd62214d MY	284	status = "disabled";
cd62214d MY	285	reg = <0x5a500000 0x200>;
051451ad	286	interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
33aae6b5	287	pinctrl-names = "default";
cd62214d	288	pinctrl-0 = <&pinctrl_emmc>;
cd62214d	289	clocks = <&mio_clk 1>;
c3ab1e11 MY	290	reset-names = "host", "bridge", "hw";
c3ab1e11 MY	291	resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
cd33feda MY	292	dma-names = "rx-tx";
cd33feda MY	293	dmas = <&dmac 6>;
cd62214d	294	bus-width = <8>;
cd62214d MY	295	cap-mmc-highspeed;
cd62214d MY	296	cap-mmc-hw-reset;
c3ab1e11	297	non-removable;
cd62214d	298	};
aa37aba1	299
cd62214d MY	300	usb0: usb@5a800100 {
	301	compatible = "socionext,uniphier-ehci", "generic-ehci";
	302	status = "disabled";
	303	reg = <0x5a800100 0x100>;
051451ad	304	interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
cd62214d MY	305	pinctrl-names = "default";
cd62214d MY	306	pinctrl-0 = <&pinctrl_usb0>;
b443fb42 MY	307	clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
b443fb42 MY	308	<&mio_clk 12>;
cd62214d MY	309	resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
cd62214d MY	310	<&mio_rst 12>;
46820e3f	311	has-transaction-translator;
cd62214d	312	};
9fbb2f7e	313
cd62214d MY	314	usb1: usb@5a810100 {
	315	compatible = "socionext,uniphier-ehci", "generic-ehci";
	316	status = "disabled";
	317	reg = <0x5a810100 0x100>;
051451ad	318	interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
cd62214d MY	319	pinctrl-names = "default";
cd62214d MY	320	pinctrl-0 = <&pinctrl_usb1>;
b443fb42 MY	321	clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
b443fb42 MY	322	<&mio_clk 13>;
cd62214d MY	323	resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
cd62214d MY	324	<&mio_rst 13>;
46820e3f	325	has-transaction-translator;
cd62214d	326	};
233812a6	327
cd62214d MY	328	usb2: usb@5a820100 {
	329	compatible = "socionext,uniphier-ehci", "generic-ehci";
	330	status = "disabled";
	331	reg = <0x5a820100 0x100>;
051451ad	332	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
cd62214d MY	333	pinctrl-names = "default";
cd62214d MY	334	pinctrl-0 = <&pinctrl_usb2>;
b443fb42 MY	335	clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
b443fb42 MY	336	<&mio_clk 14>;
cd62214d MY	337	resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
cd62214d MY	338	<&mio_rst 14>;
46820e3f	339	has-transaction-translator;
cd62214d MY	340	};
cd62214d MY	341
051451ad	342	syscon@5f800000 {
cd62214d MY	343	compatible = "socionext,uniphier-sld8-soc-glue",
	344	"simple-mfd", "syscon";
	345	reg = <0x5f800000 0x2000>;
cd62214d MY	346
	347	pinctrl: pinctrl {
	348	compatible = "socionext,uniphier-sld8-pinctrl";
cd62214d MY	349	};
	350	};
	351
051451ad	352	syscon@5f900000 {
46820e3f	353	compatible = "socionext,uniphier-sld8-soc-glue-debug",
051451ad KH	354	"simple-mfd", "syscon";
051451ad KH	355	reg = <0x5f900000 0x2000>;
46820e3f MY	356	#address-cells = <1>;
	357	#size-cells = <1>;
	358	ranges = <0 0x5f900000 0x2000>;
	359
	360	efuse@100 {
	361	compatible = "socionext,uniphier-efuse";
	362	reg = <0x100 0x28>;
	363	};
	364
	365	efuse@200 {
	366	compatible = "socionext,uniphier-efuse";
	367	reg = <0x200 0x14>;
	368	};
	369	};
	370
cd62214d MY	371	timer@60000200 {
	372	compatible = "arm,cortex-a9-global-timer";
	373	reg = <0x60000200 0x20>;
051451ad KH	374	interrupts = <GIC_PPI 11
051451ad KH	375	(GIC_CPU_MASK_RAW(1) \| IRQ_TYPE_LEVEL_HIGH)>;
cd62214d MY	376	clocks = <&arm_timer_clk>;
cd62214d MY	377	};
35343a26	378
cd62214d MY	379	timer@60000600 {
	380	compatible = "arm,cortex-a9-twd-timer";
	381	reg = <0x60000600 0x20>;
051451ad KH	382	interrupts = <GIC_PPI 13
051451ad KH	383	(GIC_CPU_MASK_RAW(1) \| IRQ_TYPE_LEVEL_HIGH)>;
cd62214d MY	384	clocks = <&arm_timer_clk>;
	385	};
	386
	387	intc: interrupt-controller@60001000 {
	388	compatible = "arm,cortex-a9-gic";
	389	reg = <0x60001000 0x1000>,
	390	<0x60000100 0x100>;
	391	#interrupt-cells = <3>;
	392	interrupt-controller;
	393	};
	394
44ebaa8e	395	aidet: interrupt-controller@61830000 {
6c9e46ef	396	compatible = "socionext,uniphier-sld8-aidet";
cd62214d	397	reg = <0x61830000 0x200>;
6c9e46ef MY	398	interrupt-controller;
6c9e46ef MY	399	#interrupt-cells = <2>;
cd62214d MY	400	};
cd62214d MY	401
051451ad	402	syscon@61840000 {
cd62214d MY	403	compatible = "socionext,uniphier-sld8-sysctrl",
	404	"simple-mfd", "syscon";
	405	reg = <0x61840000 0x10000>;
	406
051451ad	407	sys_clk: clock-controller {
cd62214d MY	408	compatible = "socionext,uniphier-sld8-clock";
	409	#clock-cells = <1>;
	410	};
	411
051451ad	412	sys_rst: reset-controller {
cd62214d MY	413	compatible = "socionext,uniphier-sld8-reset";
	414	#reset-cells = <1>;
	415	};
	416	};
	417
44ebaa8e	418	nand: nand-controller@68000000 {
abb6ac25	419	compatible = "socionext,uniphier-denali-nand-v5a";
cd62214d MY	420	status = "disabled";
	421	reg-names = "nand_data", "denali_reg";
	422	reg = <0x68000000 0x20>, <0x68100000 0x1000>;
051451ad KH	423	#address-cells = <1>;
	424	#size-cells = <0>;
	425	interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
cd62214d	426	pinctrl-names = "default";
6c9e46ef	427	pinctrl-0 = <&pinctrl_nand2cs>;
2001a81c MY	428	clock-names = "nand", "nand_x", "ecc";
2001a81c MY	429	clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
5ad15962 MY	430	reset-names = "nand", "reg";
5ad15962 MY	431	resets = <&sys_rst 2>, <&sys_rst 2>;
cd62214d MY	432	};
cd62214d MY	433	};
233812a6	434	};
cd62214d	435
6c9e46ef	436	#include "uniphier-pinctrl.dtsi"