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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Xilinx Versal NET
4 *
5 * Copyright (C) 2021 - 2022, Xilinx, Inc.
6 * Copyright (C) 2022, Advanced Micro Devices, Inc.
7 *
8 * Michal Simek <michal.simek@amd.com>
9 */
10
11/dts-v1/;
12
13#include <dt-bindings/gpio/gpio.h>
14
15/ {
16 compatible = "xlnx,versal-net-mini";
17 model = "Xilinx Versal NET MINI";
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 memory: memory@0 {
22 reg = <0 0xBBF00000 0 0x100000>, <0 0 0 0x80000000>;
23 device_type = "memory";
24 };
25
26 aliases {
27 /* serial0 = &serial0; */
28 serial0 = &dcc;
29 };
30
31 chosen {
32 stdout-path = "serial0:115200";
33 };
34
35 clk1: clk1 {
8c103c33 36 bootph-all;
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37 compatible = "fixed-clock";
38 #clock-cells = <0>;
39 clock-frequency = <1000000>;
40 };
41
42 dcc: dcc {
43 compatible = "arm,dcc";
44 status = "okay";
8c103c33 45 bootph-all;
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46 };
47
48 amba: axi {
49 compatible = "simple-bus";
8c103c33 50 bootph-all;
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51 #address-cells = <2>;
52 #size-cells = <2>;
53 ranges;
54
55 serial0: serial@f1920000 {
8c103c33 56 bootph-all;
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57 compatible = "arm,pl011", "arm,primecell";
58 reg = <0 0xf1920000 0 0x1000>;
59 reg-io-width = <4>;
60 clock-names = "uartclk", "apb_pclk";
61 clocks = <&clk1>, <&clk1>;
62 clock = <1000000>;
63 current-speed = <115200>;
64 skip-init;
65 };
66 };
67};