projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| f8f36c5d JT |
2 | /* |
| 3 | * Xilinx Zynq 7000 DTSI | |
| 4 | * Describes the hardware common to all Zynq 7000-based boards. | |
| 5 | * | |
| 05e7ca63 | 6 | * Copyright (C) 2011 - 2015 Xilinx |
| f8f36c5d | 7 | */ |
| f8f36c5d JT |
8 | |
| 9 | / { | |
| cc7978be MS |
10 | #address-cells = <1>; |
| 11 | #size-cells = <1>; | |
| f8f36c5d | 12 | compatible = "xlnx,zynq-7000"; |
| 580a54c5 MY |
13 | |
| 14 | cpus { | |
| 15 | #address-cells = <1>; | |
| 16 | #size-cells = <0>; | |
| 17 | ||
| 720ba46e | 18 | cpu0: cpu@0 { |
| 580a54c5 MY |
19 | compatible = "arm,cortex-a9"; |
| 20 | device_type = "cpu"; | |
| 21 | reg = <0>; | |
| 22 | clocks = <&clkc 3>; | |
| 23 | clock-latency = <1000>; | |
| bece06ce | 24 | cpu0-supply = <®ulator_vccpint>; |
| 580a54c5 MY |
25 | operating-points = < |
| 26 | /* kHz uV */ | |
| 27 | 666667 1000000 | |
| 28 | 333334 1000000 | |
| 580a54c5 MY |
29 | >; |
| 30 | }; | |
| 31 | ||
| 720ba46e | 32 | cpu1: cpu@1 { |
| 580a54c5 MY |
33 | compatible = "arm,cortex-a9"; |
| 34 | device_type = "cpu"; | |
| 35 | reg = <1>; | |
| 36 | clocks = <&clkc 3>; | |
| 37 | }; | |
| 38 | }; | |
| 39 | ||
| 0b180d02 MS |
40 | fpga_full: fpga-full { |
| 41 | compatible = "fpga-region"; | |
| 42 | fpga-mgr = <&devcfg>; | |
| 43 | #address-cells = <1>; | |
| 44 | #size-cells = <1>; | |
| 45 | ranges; | |
| 46 | }; | |
| 47 | ||
| cc7978be | 48 | pmu@f8891000 { |
| 580a54c5 MY |
49 | compatible = "arm,cortex-a9-pmu"; |
| 50 | interrupts = <0 5 4>, <0 6 4>; | |
| 51 | interrupt-parent = <&intc>; | |
| 427d568c MS |
52 | reg = <0xf8891000 0x1000>, |
| 53 | <0xf8893000 0x1000>; | |
| 580a54c5 MY |
54 | }; |
| 55 | ||
| cc7978be | 56 | regulator_vccpint: fixedregulator { |
| bece06ce MS |
57 | compatible = "regulator-fixed"; |
| 58 | regulator-name = "VCCPINT"; | |
| 59 | regulator-min-microvolt = <1000000>; | |
| 60 | regulator-max-microvolt = <1000000>; | |
| 61 | regulator-boot-on; | |
| 62 | regulator-always-on; | |
| 63 | }; | |
| 64 | ||
| d12c8ccd ZC |
65 | replicator { |
| 66 | compatible = "arm,coresight-static-replicator"; | |
| 67 | clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; | |
| 68 | clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; | |
| 69 | ||
| 70 | out-ports { | |
| 71 | #address-cells = <1>; | |
| 72 | #size-cells = <0>; | |
| 73 | ||
| 74 | /* replicator output ports */ | |
| 75 | port@0 { | |
| 76 | reg = <0>; | |
| 77 | replicator_out_port0: endpoint { | |
| 78 | remote-endpoint = <&tpiu_in_port>; | |
| 79 | }; | |
| 80 | }; | |
| 81 | port@1 { | |
| 82 | reg = <1>; | |
| 83 | replicator_out_port1: endpoint { | |
| 84 | remote-endpoint = <&etb_in_port>; | |
| 85 | }; | |
| 86 | }; | |
| 87 | }; | |
| 88 | in-ports { | |
| 89 | /* replicator input port */ | |
| 90 | port { | |
| 91 | replicator_in_port0: endpoint { | |
| 92 | remote-endpoint = <&funnel_out_port>; | |
| 93 | }; | |
| 94 | }; | |
| 95 | }; | |
| 96 | }; | |
| 97 | ||
| 767aa16d | 98 | amba: axi { |
| 8c103c33 | 99 | bootph-all; |
| 580a54c5 MY |
100 | compatible = "simple-bus"; |
| 101 | #address-cells = <1>; | |
| 102 | #size-cells = <1>; | |
| 103 | interrupt-parent = <&intc>; | |
| 104 | ranges; | |
| 105 | ||
| fb1a5061 MS |
106 | adc: adc@f8007100 { |
| 107 | compatible = "xlnx,zynq-xadc-1.00.a"; | |
| 108 | reg = <0xf8007100 0x20>; | |
| 109 | interrupts = <0 7 4>; | |
| 110 | interrupt-parent = <&intc>; | |
| 111 | clocks = <&clkc 12>; | |
| 112 | }; | |
| 113 | ||
| 114 | can0: can@e0008000 { | |
| 115 | compatible = "xlnx,zynq-can-1.0"; | |
| 116 | status = "disabled"; | |
| 117 | clocks = <&clkc 19>, <&clkc 36>; | |
| 118 | clock-names = "can_clk", "pclk"; | |
| 119 | reg = <0xe0008000 0x1000>; | |
| 120 | interrupts = <0 28 4>; | |
| 121 | interrupt-parent = <&intc>; | |
| 122 | tx-fifo-depth = <0x40>; | |
| 123 | rx-fifo-depth = <0x40>; | |
| 124 | }; | |
| 125 | ||
| 126 | can1: can@e0009000 { | |
| 127 | compatible = "xlnx,zynq-can-1.0"; | |
| 128 | status = "disabled"; | |
| 129 | clocks = <&clkc 20>, <&clkc 37>; | |
| 130 | clock-names = "can_clk", "pclk"; | |
| 131 | reg = <0xe0009000 0x1000>; | |
| 132 | interrupts = <0 51 4>; | |
| 133 | interrupt-parent = <&intc>; | |
| 134 | tx-fifo-depth = <0x40>; | |
| 135 | rx-fifo-depth = <0x40>; | |
| 136 | }; | |
| 137 | ||
| 138 | gpio0: gpio@e000a000 { | |
| 139 | compatible = "xlnx,zynq-gpio-1.0"; | |
| 140 | #gpio-cells = <2>; | |
| 141 | clocks = <&clkc 42>; | |
| 142 | gpio-controller; | |
| 58fab4cd | 143 | interrupt-controller; |
| 534f7e02 | 144 | #interrupt-cells = <2>; |
| fb1a5061 MS |
145 | interrupt-parent = <&intc>; |
| 146 | interrupts = <0 20 4>; | |
| 147 | reg = <0xe000a000 0x1000>; | |
| 148 | }; | |
| 149 | ||
| a0cb47f1 | 150 | i2c0: i2c@e0004000 { |
| 580a54c5 MY |
151 | compatible = "cdns,i2c-r1p10"; |
| 152 | status = "disabled"; | |
| 153 | clocks = <&clkc 38>; | |
| 154 | interrupt-parent = <&intc>; | |
| 155 | interrupts = <0 25 4>; | |
| 156 | reg = <0xe0004000 0x1000>; | |
| 157 | #address-cells = <1>; | |
| 158 | #size-cells = <0>; | |
| 159 | }; | |
| 160 | ||
| a0cb47f1 | 161 | i2c1: i2c@e0005000 { |
| 580a54c5 MY |
162 | compatible = "cdns,i2c-r1p10"; |
| 163 | status = "disabled"; | |
| 164 | clocks = <&clkc 39>; | |
| 165 | interrupt-parent = <&intc>; | |
| 166 | interrupts = <0 48 4>; | |
| 167 | reg = <0xe0005000 0x1000>; | |
| 168 | #address-cells = <1>; | |
| 169 | #size-cells = <0>; | |
| 170 | }; | |
| 171 | ||
| 172 | intc: interrupt-controller@f8f01000 { | |
| 173 | compatible = "arm,cortex-a9-gic"; | |
| 174 | #interrupt-cells = <3>; | |
| 580a54c5 MY |
175 | interrupt-controller; |
| 176 | reg = <0xF8F01000 0x1000>, | |
| 177 | <0xF8F00100 0x100>; | |
| 178 | }; | |
| 179 | ||
| a0cb47f1 | 180 | L2: cache-controller@f8f02000 { |
| 580a54c5 MY |
181 | compatible = "arm,pl310-cache"; |
| 182 | reg = <0xF8F02000 0x1000>; | |
| d50cb3d6 | 183 | interrupts = <0 2 4>; |
| 580a54c5 MY |
184 | arm,data-latency = <3 2 2>; |
| 185 | arm,tag-latency = <2 2 2>; | |
| 186 | cache-unified; | |
| 187 | cache-level = <2>; | |
| 188 | }; | |
| 189 | ||
| fb1a5061 MS |
190 | mc: memory-controller@f8006000 { |
| 191 | compatible = "xlnx,zynq-ddrc-a05"; | |
| 192 | reg = <0xf8006000 0x1000>; | |
| 5c341965 MS |
193 | }; |
| 194 | ||
| 195 | ocm: sram@fffc0000 { | |
| 196 | compatible = "mmio-sram"; | |
| 197 | reg = <0xfffc0000 0x10000>; | |
| 198 | #address-cells = <1>; | |
| 199 | #size-cells = <1>; | |
| 200 | ranges = <0 0xfffc0000 0x10000>; | |
| 201 | ocm-sram@0 { | |
| 202 | reg = <0x0 0x10000>; | |
| 203 | }; | |
| fb1a5061 MS |
204 | }; |
| 205 | ||
| a0cb47f1 | 206 | uart0: serial@e0000000 { |
| 8a8c46a6 | 207 | compatible = "xlnx,xuartps", "cdns,uart-r1p8"; |
| 580a54c5 MY |
208 | status = "disabled"; |
| 209 | clocks = <&clkc 23>, <&clkc 40>; | |
| 8a8c46a6 | 210 | clock-names = "uart_clk", "pclk"; |
| 580a54c5 MY |
211 | reg = <0xE0000000 0x1000>; |
| 212 | interrupts = <0 27 4>; | |
| 213 | }; | |
| 214 | ||
| a0cb47f1 | 215 | uart1: serial@e0001000 { |
| 8a8c46a6 | 216 | compatible = "xlnx,xuartps", "cdns,uart-r1p8"; |
| 580a54c5 MY |
217 | status = "disabled"; |
| 218 | clocks = <&clkc 24>, <&clkc 41>; | |
| 8a8c46a6 | 219 | clock-names = "uart_clk", "pclk"; |
| 580a54c5 MY |
220 | reg = <0xE0001000 0x1000>; |
| 221 | interrupts = <0 50 4>; | |
| 222 | }; | |
| 223 | ||
| a8a8fc9c | 224 | spi0: spi@e0006000 { |
| 40b383fa | 225 | compatible = "xlnx,zynq-spi-r1p6"; |
| a8a8fc9c JT |
226 | reg = <0xe0006000 0x1000>; |
| 227 | status = "disabled"; | |
| 228 | interrupt-parent = <&intc>; | |
| 229 | interrupts = <0 26 4>; | |
| 230 | clocks = <&clkc 25>, <&clkc 34>; | |
| 231 | clock-names = "ref_clk", "pclk"; | |
| 232 | #address-cells = <1>; | |
| 233 | #size-cells = <0>; | |
| 234 | }; | |
| 235 | ||
| 236 | spi1: spi@e0007000 { | |
| 40b383fa | 237 | compatible = "xlnx,zynq-spi-r1p6"; |
| a8a8fc9c JT |
238 | reg = <0xe0007000 0x1000>; |
| 239 | status = "disabled"; | |
| 240 | interrupt-parent = <&intc>; | |
| 241 | interrupts = <0 49 4>; | |
| 242 | clocks = <&clkc 26>, <&clkc 35>; | |
| 243 | clock-names = "ref_clk", "pclk"; | |
| 244 | #address-cells = <1>; | |
| 245 | #size-cells = <0>; | |
| 246 | }; | |
| 247 | ||
| 70676cb3 | 248 | qspi: spi@e000d000 { |
| 70676cb3 | 249 | compatible = "xlnx,zynq-qspi-1.0"; |
| 41634fd2 | 250 | reg = <0xe000d000 0x1000>; |
| 70676cb3 JT |
251 | interrupt-parent = <&intc>; |
| 252 | interrupts = <0 19 4>; | |
| 41634fd2 MS |
253 | clocks = <&clkc 10>, <&clkc 43>; |
| 254 | clock-names = "ref_clk", "pclk"; | |
| 255 | status = "disabled"; | |
| 70676cb3 JT |
256 | #address-cells = <1>; |
| 257 | #size-cells = <0>; | |
| 258 | }; | |
| 259 | ||
| 580a54c5 | 260 | gem0: ethernet@e000b000 { |
| a09d9278 | 261 | compatible = "xlnx,zynq-gem", "cdns,gem"; |
| 08305feb | 262 | reg = <0xe000b000 0x1000>; |
| 580a54c5 MY |
263 | status = "disabled"; |
| 264 | interrupts = <0 22 4>; | |
| 265 | clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; | |
| 266 | clock-names = "pclk", "hclk", "tx_clk"; | |
| 5ee236a3 MS |
267 | #address-cells = <1>; |
| 268 | #size-cells = <0>; | |
| 580a54c5 MY |
269 | }; |
| 270 | ||
| 271 | gem1: ethernet@e000c000 { | |
| a09d9278 | 272 | compatible = "xlnx,zynq-gem", "cdns,gem"; |
| 08305feb | 273 | reg = <0xe000c000 0x1000>; |
| 580a54c5 MY |
274 | status = "disabled"; |
| 275 | interrupts = <0 45 4>; | |
| 276 | clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; | |
| 277 | clock-names = "pclk", "hclk", "tx_clk"; | |
| 5ee236a3 MS |
278 | #address-cells = <1>; |
| 279 | #size-cells = <0>; | |
| 580a54c5 MY |
280 | }; |
| 281 | ||
| 03a8e826 MW |
282 | smcc: memory-controller@e000e000 { |
| 283 | compatible = "arm,pl353-smc-r2p1", "arm,primecell"; | |
| 284 | reg = <0xe000e000 0x0001000>; | |
| 285 | status = "disabled"; | |
| 286 | clock-names = "memclk", "apb_pclk"; | |
| 287 | clocks = <&clkc 11>, <&clkc 44>; | |
| 288 | ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */ | |
| 289 | 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */ | |
| 290 | 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */ | |
| 291 | #address-cells = <2>; | |
| 292 | #size-cells = <1>; | |
| 293 | interrupt-parent = <&intc>; | |
| 294 | interrupts = <0 18 4>; | |
| 295 | ||
| 296 | nfc0: nand-controller@0,0 { | |
| 297 | compatible = "arm,pl353-nand-r2p1"; | |
| 298 | reg = <0 0 0x1000000>; | |
| 299 | status = "disabled"; | |
| 300 | #address-cells = <1>; | |
| a13e0821 | 301 | #size-cells = <0>; |
| 03a8e826 MW |
302 | }; |
| 303 | nor0: flash@1,0 { | |
| 304 | status = "disabled"; | |
| 305 | compatible = "cfi-flash"; | |
| 306 | reg = <1 0 0x2000000>; | |
| 307 | #address-cells = <1>; | |
| 308 | #size-cells = <1>; | |
| 309 | }; | |
| 310 | }; | |
| 311 | ||
| 7b85f790 | 312 | sdhci0: mmc@e0100000 { |
| 580a54c5 MY |
313 | compatible = "arasan,sdhci-8.9a"; |
| 314 | status = "disabled"; | |
| 315 | clock-names = "clk_xin", "clk_ahb"; | |
| 316 | clocks = <&clkc 21>, <&clkc 32>; | |
| 317 | interrupt-parent = <&intc>; | |
| 318 | interrupts = <0 24 4>; | |
| 319 | reg = <0xe0100000 0x1000>; | |
| e5c343dd | 320 | }; |
| 580a54c5 | 321 | |
| 7b85f790 | 322 | sdhci1: mmc@e0101000 { |
| 580a54c5 MY |
323 | compatible = "arasan,sdhci-8.9a"; |
| 324 | status = "disabled"; | |
| 325 | clock-names = "clk_xin", "clk_ahb"; | |
| 326 | clocks = <&clkc 22>, <&clkc 33>; | |
| 327 | interrupt-parent = <&intc>; | |
| 328 | interrupts = <0 47 4>; | |
| 329 | reg = <0xe0101000 0x1000>; | |
| e5c343dd | 330 | }; |
| 580a54c5 MY |
331 | |
| 332 | slcr: slcr@f8000000 { | |
| 8c103c33 | 333 | bootph-all; |
| 580a54c5 MY |
334 | #address-cells = <1>; |
| 335 | #size-cells = <1>; | |
| 621a93e1 | 336 | compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; |
| 580a54c5 MY |
337 | reg = <0xF8000000 0x1000>; |
| 338 | ranges; | |
| 339 | clkc: clkc@100 { | |
| 8c103c33 | 340 | bootph-all; |
| 580a54c5 MY |
341 | #clock-cells = <1>; |
| 342 | compatible = "xlnx,ps7-clkc"; | |
| 96dcde48 | 343 | fclk-enable = <0xf>; |
| 580a54c5 MY |
344 | clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", |
| 345 | "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", | |
| 346 | "dci", "lqspi", "smc", "pcap", "gem0", "gem1", | |
| 347 | "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", | |
| 348 | "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", | |
| 349 | "dma", "usb0_aper", "usb1_aper", "gem0_aper", | |
| 350 | "gem1_aper", "sdio0_aper", "sdio1_aper", | |
| 351 | "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", | |
| 352 | "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", | |
| 353 | "gpio_aper", "lqspi_aper", "smc_aper", "swdt", | |
| 354 | "dbg_trc", "dbg_apb"; | |
| 355 | reg = <0x100 0x100>; | |
| 356 | }; | |
| e913ce2a | 357 | |
| 4c987271 MF |
358 | rstc: rstc@200 { |
| 359 | compatible = "xlnx,zynq-reset"; | |
| 360 | reg = <0x200 0x48>; | |
| 361 | #reset-cells = <1>; | |
| 362 | syscon = <&slcr>; | |
| 363 | }; | |
| 364 | ||
| e913ce2a MS |
365 | pinctrl0: pinctrl@700 { |
| 366 | compatible = "xlnx,pinctrl-zynq"; | |
| 367 | reg = <0x700 0x200>; | |
| 368 | syscon = <&slcr>; | |
| 369 | }; | |
| 580a54c5 MY |
370 | }; |
| 371 | ||
| 5331845d | 372 | dmac_s: dma-controller@f8003000 { |
| fb1a5061 MS |
373 | compatible = "arm,pl330", "arm,primecell"; |
| 374 | reg = <0xf8003000 0x1000>; | |
| 375 | interrupt-parent = <&intc>; | |
| cfa39857 MS |
376 | /* |
| 377 | * interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", | |
| 378 | * "dma4", "dma5", "dma6", "dma7"; | |
| 379 | */ | |
| fb1a5061 MS |
380 | interrupts = <0 13 4>, |
| 381 | <0 14 4>, <0 15 4>, | |
| 382 | <0 16 4>, <0 17 4>, | |
| 383 | <0 40 4>, <0 41 4>, | |
| 384 | <0 42 4>, <0 43 4>; | |
| 385 | #dma-cells = <1>; | |
| fb1a5061 MS |
386 | clocks = <&clkc 27>; |
| 387 | clock-names = "apb_pclk"; | |
| 388 | }; | |
| 389 | ||
| 390 | devcfg: devcfg@f8007000 { | |
| 391 | compatible = "xlnx,zynq-devcfg-1.0"; | |
| 41634fd2 | 392 | reg = <0xf8007000 0x100>; |
| 77bb73de MS |
393 | interrupt-parent = <&intc>; |
| 394 | interrupts = <0 8 4>; | |
| 77bb73de MS |
395 | clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; |
| 396 | clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; | |
| 20fe3f17 | 397 | syscon = <&slcr>; |
| fb1a5061 MS |
398 | }; |
| 399 | ||
| e7f327fe MS |
400 | efuse: efuse@f800d000 { |
| 401 | compatible = "xlnx,zynq-efuse"; | |
| 402 | reg = <0xf800d000 0x20>; | |
| 403 | }; | |
| 404 | ||
| 580a54c5 MY |
405 | global_timer: timer@f8f00200 { |
| 406 | compatible = "arm,cortex-a9-global-timer"; | |
| 407 | reg = <0xf8f00200 0x20>; | |
| 408 | interrupts = <1 11 0x301>; | |
| 409 | interrupt-parent = <&intc>; | |
| 410 | clocks = <&clkc 4>; | |
| 411 | }; | |
| 412 | ||
| a0cb47f1 | 413 | ttc0: timer@f8001000 { |
| 580a54c5 | 414 | interrupt-parent = <&intc>; |
| b346bd1d | 415 | interrupts = <0 10 4>, <0 11 4>, <0 12 4>; |
| 580a54c5 MY |
416 | compatible = "cdns,ttc"; |
| 417 | clocks = <&clkc 6>; | |
| 418 | reg = <0xF8001000 0x1000>; | |
| 419 | }; | |
| 420 | ||
| a0cb47f1 | 421 | ttc1: timer@f8002000 { |
| 580a54c5 | 422 | interrupt-parent = <&intc>; |
| b346bd1d | 423 | interrupts = <0 37 4>, <0 38 4>, <0 39 4>; |
| 580a54c5 MY |
424 | compatible = "cdns,ttc"; |
| 425 | clocks = <&clkc 6>; | |
| 426 | reg = <0xF8002000 0x1000>; | |
| 427 | }; | |
| fb1a5061 | 428 | |
| a0cb47f1 | 429 | scutimer: timer@f8f00600 { |
| 8c103c33 | 430 | bootph-all; |
| 580a54c5 | 431 | interrupt-parent = <&intc>; |
| e5c343dd | 432 | interrupts = <1 13 0x301>; |
| 580a54c5 | 433 | compatible = "arm,cortex-a9-twd-timer"; |
| e5c343dd | 434 | reg = <0xf8f00600 0x20>; |
| 580a54c5 | 435 | clocks = <&clkc 4>; |
| e5c343dd | 436 | }; |
| fb1a5061 MS |
437 | |
| 438 | usb0: usb@e0002000 { | |
| 439 | compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; | |
| 440 | status = "disabled"; | |
| 441 | clocks = <&clkc 28>; | |
| 442 | interrupt-parent = <&intc>; | |
| 443 | interrupts = <0 21 4>; | |
| 444 | reg = <0xe0002000 0x1000>; | |
| 445 | phy_type = "ulpi"; | |
| 446 | }; | |
| 447 | ||
| 448 | usb1: usb@e0003000 { | |
| 449 | compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; | |
| 450 | status = "disabled"; | |
| 451 | clocks = <&clkc 29>; | |
| 452 | interrupt-parent = <&intc>; | |
| 453 | interrupts = <0 44 4>; | |
| 454 | reg = <0xe0003000 0x1000>; | |
| 455 | phy_type = "ulpi"; | |
| 456 | }; | |
| 457 | ||
| 458 | watchdog0: watchdog@f8005000 { | |
| 459 | clocks = <&clkc 45>; | |
| 460 | compatible = "cdns,wdt-r1p2"; | |
| 461 | interrupt-parent = <&intc>; | |
| 462 | interrupts = <0 9 1>; | |
| 463 | reg = <0xf8005000 0x1000>; | |
| 464 | timeout-sec = <10>; | |
| 465 | }; | |
| d12c8ccd ZC |
466 | |
| 467 | etb@f8801000 { | |
| 468 | compatible = "arm,coresight-etb10", "arm,primecell"; | |
| 469 | reg = <0xf8801000 0x1000>; | |
| 470 | clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; | |
| 471 | clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; | |
| 472 | in-ports { | |
| 473 | port { | |
| 474 | etb_in_port: endpoint { | |
| 475 | remote-endpoint = <&replicator_out_port1>; | |
| 476 | }; | |
| 477 | }; | |
| 478 | }; | |
| 479 | }; | |
| 480 | ||
| 481 | tpiu@f8803000 { | |
| 482 | compatible = "arm,coresight-tpiu", "arm,primecell"; | |
| 483 | reg = <0xf8803000 0x1000>; | |
| 484 | clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; | |
| 485 | clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; | |
| 486 | in-ports { | |
| 487 | port { | |
| 488 | tpiu_in_port: endpoint { | |
| 489 | remote-endpoint = <&replicator_out_port0>; | |
| 490 | }; | |
| 491 | }; | |
| 492 | }; | |
| 493 | }; | |
| 494 | ||
| 495 | funnel@f8804000 { | |
| 496 | compatible = "arm,coresight-static-funnel", "arm,primecell"; | |
| 497 | reg = <0xf8804000 0x1000>; | |
| 498 | clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; | |
| 499 | clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; | |
| 500 | ||
| 501 | /* funnel output ports */ | |
| 502 | out-ports { | |
| 503 | port { | |
| 504 | funnel_out_port: endpoint { | |
| 505 | remote-endpoint = | |
| 506 | <&replicator_in_port0>; | |
| 507 | }; | |
| 508 | }; | |
| 509 | }; | |
| 510 | ||
| 511 | in-ports { | |
| 512 | #address-cells = <1>; | |
| 513 | #size-cells = <0>; | |
| 514 | ||
| 515 | /* funnel input ports */ | |
| 516 | port@0 { | |
| 517 | reg = <0>; | |
| 518 | funnel0_in_port0: endpoint { | |
| 519 | remote-endpoint = <&ptm0_out_port>; | |
| 520 | }; | |
| 521 | }; | |
| 522 | ||
| 523 | port@1 { | |
| 524 | reg = <1>; | |
| 525 | funnel0_in_port1: endpoint { | |
| 526 | remote-endpoint = <&ptm1_out_port>; | |
| 527 | }; | |
| 528 | }; | |
| 529 | ||
| 530 | port@2 { | |
| 531 | reg = <2>; | |
| 532 | funnel0_in_port2: endpoint { | |
| 533 | }; | |
| 534 | }; | |
| 535 | /* The other input ports are not connect to anything */ | |
| 536 | }; | |
| 537 | }; | |
| 538 | ||
| 539 | ptm@f889c000 { | |
| 540 | compatible = "arm,coresight-etm3x", "arm,primecell"; | |
| 541 | reg = <0xf889c000 0x1000>; | |
| 542 | clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; | |
| 543 | clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; | |
| 544 | cpu = <&cpu0>; | |
| 545 | out-ports { | |
| 546 | port { | |
| 547 | ptm0_out_port: endpoint { | |
| 548 | remote-endpoint = <&funnel0_in_port0>; | |
| 549 | }; | |
| 550 | }; | |
| 551 | }; | |
| 552 | }; | |
| 553 | ||
| 554 | ptm@f889d000 { | |
| 555 | compatible = "arm,coresight-etm3x", "arm,primecell"; | |
| 556 | reg = <0xf889d000 0x1000>; | |
| 557 | clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; | |
| 558 | clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; | |
| 559 | cpu = <&cpu1>; | |
| 560 | out-ports { | |
| 561 | port { | |
| 562 | ptm1_out_port: endpoint { | |
| 563 | remote-endpoint = <&funnel0_in_port1>; | |
| 564 | }; | |
| 565 | }; | |
| 566 | }; | |
| 567 | }; | |
| 580a54c5 | 568 | }; |
| f8f36c5d | 569 | }; |