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Commit | Line | Data |
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f8f36c5d JT |
1 | /* |
2 | * Xilinx Zynq 7000 DTSI | |
3 | * Describes the hardware common to all Zynq 7000-based boards. | |
4 | * | |
05e7ca63 | 5 | * Copyright (C) 2011 - 2015 Xilinx |
f8f36c5d JT |
6 | * |
7 | * SPDX-License-Identifier: GPL-2.0+ | |
8 | */ | |
9 | /include/ "skeleton.dtsi" | |
10 | ||
11 | / { | |
12 | compatible = "xlnx,zynq-7000"; | |
580a54c5 MY |
13 | |
14 | cpus { | |
15 | #address-cells = <1>; | |
16 | #size-cells = <0>; | |
17 | ||
18 | cpu@0 { | |
19 | compatible = "arm,cortex-a9"; | |
20 | device_type = "cpu"; | |
21 | reg = <0>; | |
22 | clocks = <&clkc 3>; | |
23 | clock-latency = <1000>; | |
bece06ce | 24 | cpu0-supply = <®ulator_vccpint>; |
580a54c5 MY |
25 | operating-points = < |
26 | /* kHz uV */ | |
27 | 666667 1000000 | |
28 | 333334 1000000 | |
580a54c5 MY |
29 | >; |
30 | }; | |
31 | ||
32 | cpu@1 { | |
33 | compatible = "arm,cortex-a9"; | |
34 | device_type = "cpu"; | |
35 | reg = <1>; | |
36 | clocks = <&clkc 3>; | |
37 | }; | |
38 | }; | |
39 | ||
40 | pmu { | |
41 | compatible = "arm,cortex-a9-pmu"; | |
42 | interrupts = <0 5 4>, <0 6 4>; | |
43 | interrupt-parent = <&intc>; | |
44 | reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; | |
45 | }; | |
46 | ||
bece06ce MS |
47 | regulator_vccpint: fixedregulator@0 { |
48 | compatible = "regulator-fixed"; | |
49 | regulator-name = "VCCPINT"; | |
50 | regulator-min-microvolt = <1000000>; | |
51 | regulator-max-microvolt = <1000000>; | |
52 | regulator-boot-on; | |
53 | regulator-always-on; | |
54 | }; | |
55 | ||
461c3888 | 56 | amba: amba { |
580a54c5 MY |
57 | compatible = "simple-bus"; |
58 | #address-cells = <1>; | |
59 | #size-cells = <1>; | |
60 | interrupt-parent = <&intc>; | |
61 | ranges; | |
62 | ||
fb1a5061 MS |
63 | adc: adc@f8007100 { |
64 | compatible = "xlnx,zynq-xadc-1.00.a"; | |
65 | reg = <0xf8007100 0x20>; | |
66 | interrupts = <0 7 4>; | |
67 | interrupt-parent = <&intc>; | |
68 | clocks = <&clkc 12>; | |
69 | }; | |
70 | ||
71 | can0: can@e0008000 { | |
72 | compatible = "xlnx,zynq-can-1.0"; | |
73 | status = "disabled"; | |
74 | clocks = <&clkc 19>, <&clkc 36>; | |
75 | clock-names = "can_clk", "pclk"; | |
76 | reg = <0xe0008000 0x1000>; | |
77 | interrupts = <0 28 4>; | |
78 | interrupt-parent = <&intc>; | |
79 | tx-fifo-depth = <0x40>; | |
80 | rx-fifo-depth = <0x40>; | |
81 | }; | |
82 | ||
83 | can1: can@e0009000 { | |
84 | compatible = "xlnx,zynq-can-1.0"; | |
85 | status = "disabled"; | |
86 | clocks = <&clkc 20>, <&clkc 37>; | |
87 | clock-names = "can_clk", "pclk"; | |
88 | reg = <0xe0009000 0x1000>; | |
89 | interrupts = <0 51 4>; | |
90 | interrupt-parent = <&intc>; | |
91 | tx-fifo-depth = <0x40>; | |
92 | rx-fifo-depth = <0x40>; | |
93 | }; | |
94 | ||
95 | gpio0: gpio@e000a000 { | |
96 | compatible = "xlnx,zynq-gpio-1.0"; | |
97 | #gpio-cells = <2>; | |
98 | clocks = <&clkc 42>; | |
99 | gpio-controller; | |
100 | interrupt-parent = <&intc>; | |
101 | interrupts = <0 20 4>; | |
102 | reg = <0xe000a000 0x1000>; | |
103 | }; | |
104 | ||
a0cb47f1 | 105 | i2c0: i2c@e0004000 { |
580a54c5 MY |
106 | compatible = "cdns,i2c-r1p10"; |
107 | status = "disabled"; | |
108 | clocks = <&clkc 38>; | |
109 | interrupt-parent = <&intc>; | |
110 | interrupts = <0 25 4>; | |
111 | reg = <0xe0004000 0x1000>; | |
112 | #address-cells = <1>; | |
113 | #size-cells = <0>; | |
114 | }; | |
115 | ||
a0cb47f1 | 116 | i2c1: i2c@e0005000 { |
580a54c5 MY |
117 | compatible = "cdns,i2c-r1p10"; |
118 | status = "disabled"; | |
119 | clocks = <&clkc 39>; | |
120 | interrupt-parent = <&intc>; | |
121 | interrupts = <0 48 4>; | |
122 | reg = <0xe0005000 0x1000>; | |
123 | #address-cells = <1>; | |
124 | #size-cells = <0>; | |
125 | }; | |
126 | ||
127 | intc: interrupt-controller@f8f01000 { | |
128 | compatible = "arm,cortex-a9-gic"; | |
129 | #interrupt-cells = <3>; | |
580a54c5 MY |
130 | interrupt-controller; |
131 | reg = <0xF8F01000 0x1000>, | |
132 | <0xF8F00100 0x100>; | |
133 | }; | |
134 | ||
a0cb47f1 | 135 | L2: cache-controller@f8f02000 { |
580a54c5 MY |
136 | compatible = "arm,pl310-cache"; |
137 | reg = <0xF8F02000 0x1000>; | |
d50cb3d6 | 138 | interrupts = <0 2 4>; |
580a54c5 MY |
139 | arm,data-latency = <3 2 2>; |
140 | arm,tag-latency = <2 2 2>; | |
141 | cache-unified; | |
142 | cache-level = <2>; | |
143 | }; | |
144 | ||
fb1a5061 MS |
145 | mc: memory-controller@f8006000 { |
146 | compatible = "xlnx,zynq-ddrc-a05"; | |
147 | reg = <0xf8006000 0x1000>; | |
148 | }; | |
149 | ||
a0cb47f1 | 150 | uart0: serial@e0000000 { |
8a8c46a6 | 151 | compatible = "xlnx,xuartps", "cdns,uart-r1p8"; |
580a54c5 MY |
152 | status = "disabled"; |
153 | clocks = <&clkc 23>, <&clkc 40>; | |
8a8c46a6 | 154 | clock-names = "uart_clk", "pclk"; |
580a54c5 MY |
155 | reg = <0xE0000000 0x1000>; |
156 | interrupts = <0 27 4>; | |
157 | }; | |
158 | ||
a0cb47f1 | 159 | uart1: serial@e0001000 { |
8a8c46a6 | 160 | compatible = "xlnx,xuartps", "cdns,uart-r1p8"; |
580a54c5 MY |
161 | status = "disabled"; |
162 | clocks = <&clkc 24>, <&clkc 41>; | |
8a8c46a6 | 163 | clock-names = "uart_clk", "pclk"; |
580a54c5 MY |
164 | reg = <0xE0001000 0x1000>; |
165 | interrupts = <0 50 4>; | |
166 | }; | |
167 | ||
a8a8fc9c | 168 | spi0: spi@e0006000 { |
40b383fa | 169 | compatible = "xlnx,zynq-spi-r1p6"; |
a8a8fc9c JT |
170 | reg = <0xe0006000 0x1000>; |
171 | status = "disabled"; | |
172 | interrupt-parent = <&intc>; | |
173 | interrupts = <0 26 4>; | |
174 | clocks = <&clkc 25>, <&clkc 34>; | |
175 | clock-names = "ref_clk", "pclk"; | |
cdc9dd07 | 176 | spi-max-frequency = <166666700>; |
a8a8fc9c JT |
177 | #address-cells = <1>; |
178 | #size-cells = <0>; | |
179 | }; | |
180 | ||
181 | spi1: spi@e0007000 { | |
40b383fa | 182 | compatible = "xlnx,zynq-spi-r1p6"; |
a8a8fc9c JT |
183 | reg = <0xe0007000 0x1000>; |
184 | status = "disabled"; | |
185 | interrupt-parent = <&intc>; | |
186 | interrupts = <0 49 4>; | |
187 | clocks = <&clkc 26>, <&clkc 35>; | |
188 | clock-names = "ref_clk", "pclk"; | |
cdc9dd07 | 189 | spi-max-frequency = <166666700>; |
a8a8fc9c JT |
190 | #address-cells = <1>; |
191 | #size-cells = <0>; | |
192 | }; | |
193 | ||
580a54c5 | 194 | gem0: ethernet@e000b000 { |
7e163363 | 195 | compatible = "cdns,zynq-gem", "cdns,gem"; |
08305feb | 196 | reg = <0xe000b000 0x1000>; |
580a54c5 MY |
197 | status = "disabled"; |
198 | interrupts = <0 22 4>; | |
199 | clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; | |
200 | clock-names = "pclk", "hclk", "tx_clk"; | |
5ee236a3 MS |
201 | #address-cells = <1>; |
202 | #size-cells = <0>; | |
580a54c5 MY |
203 | }; |
204 | ||
205 | gem1: ethernet@e000c000 { | |
7e163363 | 206 | compatible = "cdns,zynq-gem", "cdns,gem"; |
08305feb | 207 | reg = <0xe000c000 0x1000>; |
580a54c5 MY |
208 | status = "disabled"; |
209 | interrupts = <0 45 4>; | |
210 | clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; | |
211 | clock-names = "pclk", "hclk", "tx_clk"; | |
5ee236a3 MS |
212 | #address-cells = <1>; |
213 | #size-cells = <0>; | |
580a54c5 MY |
214 | }; |
215 | ||
a0cb47f1 | 216 | sdhci0: sdhci@e0100000 { |
580a54c5 MY |
217 | compatible = "arasan,sdhci-8.9a"; |
218 | status = "disabled"; | |
219 | clock-names = "clk_xin", "clk_ahb"; | |
220 | clocks = <&clkc 21>, <&clkc 32>; | |
221 | interrupt-parent = <&intc>; | |
222 | interrupts = <0 24 4>; | |
223 | reg = <0xe0100000 0x1000>; | |
224 | } ; | |
225 | ||
a0cb47f1 | 226 | sdhci1: sdhci@e0101000 { |
580a54c5 MY |
227 | compatible = "arasan,sdhci-8.9a"; |
228 | status = "disabled"; | |
229 | clock-names = "clk_xin", "clk_ahb"; | |
230 | clocks = <&clkc 22>, <&clkc 33>; | |
231 | interrupt-parent = <&intc>; | |
232 | interrupts = <0 47 4>; | |
233 | reg = <0xe0101000 0x1000>; | |
234 | } ; | |
235 | ||
236 | slcr: slcr@f8000000 { | |
237 | #address-cells = <1>; | |
238 | #size-cells = <1>; | |
e913ce2a | 239 | compatible = "xlnx,zynq-slcr", "syscon", "simple-bus"; |
580a54c5 MY |
240 | reg = <0xF8000000 0x1000>; |
241 | ranges; | |
242 | clkc: clkc@100 { | |
243 | #clock-cells = <1>; | |
244 | compatible = "xlnx,ps7-clkc"; | |
580a54c5 MY |
245 | fclk-enable = <0>; |
246 | clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", | |
247 | "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", | |
248 | "dci", "lqspi", "smc", "pcap", "gem0", "gem1", | |
249 | "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", | |
250 | "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", | |
251 | "dma", "usb0_aper", "usb1_aper", "gem0_aper", | |
252 | "gem1_aper", "sdio0_aper", "sdio1_aper", | |
253 | "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", | |
254 | "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", | |
255 | "gpio_aper", "lqspi_aper", "smc_aper", "swdt", | |
256 | "dbg_trc", "dbg_apb"; | |
257 | reg = <0x100 0x100>; | |
258 | }; | |
e913ce2a MS |
259 | |
260 | pinctrl0: pinctrl@700 { | |
261 | compatible = "xlnx,pinctrl-zynq"; | |
262 | reg = <0x700 0x200>; | |
263 | syscon = <&slcr>; | |
264 | }; | |
580a54c5 MY |
265 | }; |
266 | ||
fb1a5061 MS |
267 | dmac_s: dmac@f8003000 { |
268 | compatible = "arm,pl330", "arm,primecell"; | |
269 | reg = <0xf8003000 0x1000>; | |
270 | interrupt-parent = <&intc>; | |
271 | interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", | |
272 | "dma4", "dma5", "dma6", "dma7"; | |
273 | interrupts = <0 13 4>, | |
274 | <0 14 4>, <0 15 4>, | |
275 | <0 16 4>, <0 17 4>, | |
276 | <0 40 4>, <0 41 4>, | |
277 | <0 42 4>, <0 43 4>; | |
278 | #dma-cells = <1>; | |
279 | #dma-channels = <8>; | |
280 | #dma-requests = <4>; | |
281 | clocks = <&clkc 27>; | |
282 | clock-names = "apb_pclk"; | |
283 | }; | |
284 | ||
285 | devcfg: devcfg@f8007000 { | |
286 | compatible = "xlnx,zynq-devcfg-1.0"; | |
287 | reg = <0xf8007000 0x100>; | |
288 | }; | |
289 | ||
580a54c5 MY |
290 | global_timer: timer@f8f00200 { |
291 | compatible = "arm,cortex-a9-global-timer"; | |
292 | reg = <0xf8f00200 0x20>; | |
293 | interrupts = <1 11 0x301>; | |
294 | interrupt-parent = <&intc>; | |
295 | clocks = <&clkc 4>; | |
296 | }; | |
297 | ||
a0cb47f1 | 298 | ttc0: timer@f8001000 { |
580a54c5 | 299 | interrupt-parent = <&intc>; |
b346bd1d | 300 | interrupts = <0 10 4>, <0 11 4>, <0 12 4>; |
580a54c5 MY |
301 | compatible = "cdns,ttc"; |
302 | clocks = <&clkc 6>; | |
303 | reg = <0xF8001000 0x1000>; | |
304 | }; | |
305 | ||
a0cb47f1 | 306 | ttc1: timer@f8002000 { |
580a54c5 | 307 | interrupt-parent = <&intc>; |
b346bd1d | 308 | interrupts = <0 37 4>, <0 38 4>, <0 39 4>; |
580a54c5 MY |
309 | compatible = "cdns,ttc"; |
310 | clocks = <&clkc 6>; | |
311 | reg = <0xF8002000 0x1000>; | |
312 | }; | |
fb1a5061 | 313 | |
a0cb47f1 | 314 | scutimer: timer@f8f00600 { |
580a54c5 MY |
315 | interrupt-parent = <&intc>; |
316 | interrupts = < 1 13 0x301 >; | |
317 | compatible = "arm,cortex-a9-twd-timer"; | |
318 | reg = < 0xf8f00600 0x20 >; | |
319 | clocks = <&clkc 4>; | |
320 | } ; | |
fb1a5061 MS |
321 | |
322 | usb0: usb@e0002000 { | |
323 | compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; | |
324 | status = "disabled"; | |
325 | clocks = <&clkc 28>; | |
326 | interrupt-parent = <&intc>; | |
327 | interrupts = <0 21 4>; | |
328 | reg = <0xe0002000 0x1000>; | |
329 | phy_type = "ulpi"; | |
330 | }; | |
331 | ||
332 | usb1: usb@e0003000 { | |
333 | compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; | |
334 | status = "disabled"; | |
335 | clocks = <&clkc 29>; | |
336 | interrupt-parent = <&intc>; | |
337 | interrupts = <0 44 4>; | |
338 | reg = <0xe0003000 0x1000>; | |
339 | phy_type = "ulpi"; | |
340 | }; | |
341 | ||
342 | watchdog0: watchdog@f8005000 { | |
343 | clocks = <&clkc 45>; | |
344 | compatible = "cdns,wdt-r1p2"; | |
345 | interrupt-parent = <&intc>; | |
346 | interrupts = <0 9 1>; | |
347 | reg = <0xf8005000 0x1000>; | |
348 | timeout-sec = <10>; | |
349 | }; | |
580a54c5 | 350 | }; |
f8f36c5d | 351 | }; |