[people/ms/u-boot.git] / arch / arm / dts / zynq-zed.dts

/*
 * Xilinx ZED board DTS
 *
 *  Copyright (C) 2011 - 2015 Xilinx
 *  Copyright (C) 2012 National Instruments Corp.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
/dts-v1/;
#include "zynq-7000.dtsi"

/ {
	model = "Zynq Zed Development Board";
	compatible = "xlnx,zynq-zed", "xlnx,zynq-7000";

	aliases {
		ethernet0 = &gem0;
		serial0 = &uart1;
		spi0 = &qspi;
	};

	memory {
		device_type = "memory";
		reg = <0x0 0x20000000>;
	};

	chosen {
		bootargs = "earlyprintk";
		stdout-path = "serial0:115200n8";
	};

	usb_phy0: phy0 {
		compatible = "usb-nop-xceiv";
		#phy-cells = <0>;
	};
};

&clkc {
	ps-clk-frequency = <33333333>;
};

&gem0 {
	status = "okay";
	phy-mode = "rgmii-id";
	phy-handle = <&ethernet_phy>;

	ethernet_phy: ethernet-phy@0 {
		reg = <0>;
	};
};

&sdhci0 {
	status = "okay";
};

&uart1 {
	status = "okay";
};

&qspi {
	status = "okay";
};

&usb0 {
	status = "okay";
	dr_mode = "host";
	usb-phy = <&usb_phy0>;
};
Commit	Line	Data
f8f36c5d JT	1	/*
	2	* Xilinx ZED board DTS
	3	*
999667ca MS	4	* Copyright (C) 2011 - 2015 Xilinx
999667ca MS	5	* Copyright (C) 2012 National Instruments Corp.
f8f36c5d JT	6	*
	7	* SPDX-License-Identifier: GPL-2.0+
	8	*/
	9	/dts-v1/;
	10	#include "zynq-7000.dtsi"
	11
	12	/ {
999667ca	13	model = "Zynq Zed Development Board";
f8f36c5d	14	compatible = "xlnx,zynq-zed", "xlnx,zynq-7000";
7d34c5de	15
9f9d41ba	16	aliases {
999667ca	17	ethernet0 = &gem0;
9f9d41ba	18	serial0 = &uart1;
976dfb0f	19	spi0 = &qspi;
9f9d41ba MY	20	};
9f9d41ba MY	21
7d34c5de MY	22	memory {
7d34c5de MY	23	device_type = "memory";
999667ca	24	reg = <0x0 0x20000000>;
7d34c5de	25	};
999667ca MS	26
	27	chosen {
	28	bootargs = "earlyprintk";
	29	stdout-path = "serial0:115200n8";
	30	};
	31
	32	usb_phy0: phy0 {
	33	compatible = "usb-nop-xceiv";
	34	#phy-cells = <0>;
	35	};
	36	};
	37
	38	&clkc {
	39	ps-clk-frequency = <33333333>;
	40	};
	41
	42	&gem0 {
	43	status = "okay";
	44	phy-mode = "rgmii-id";
	45	phy-handle = <&ethernet_phy>;
	46
	47	ethernet_phy: ethernet-phy@0 {
	48	reg = <0>;
	49	};
	50	};
	51
	52	&sdhci0 {
	53	status = "okay";
	54	};
	55
	56	&uart1 {
	57	status = "okay";
	58	};
	59
976dfb0f JT	60	&qspi {
	61	status = "okay";
	62	};
	63
999667ca MS	64	&usb0 {
	65	status = "okay";
	66	dr_mode = "host";
	67	usb-phy = <&usb_phy0>;
f8f36c5d	68	};