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ARM64: zynqmp: Added OOB timing settings in zynqmp-ep108.dts
[people/ms/u-boot.git] / arch / arm / dts / zynqmp-ep108.dts
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1/*
2 * dts file for Xilinx ZynqMP ep108 development board
3 *
4 * (C) Copyright 2014 - 2015, Xilinx, Inc.
5 *
6 * Michal Simek <michal.simek@xilinx.com>
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11/dts-v1/;
12
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13#include "zynqmp.dtsi"
14#include "zynqmp-ep108-clk.dtsi"
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15
16/ {
17 model = "ZynqMP EP108";
18
19 aliases {
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20 mmc0 = &sdhci0;
21 mmc1 = &sdhci1;
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22 serial0 = &uart0;
23 spi0 = &qspi;
24 spi1 = &spi0;
25 spi2 = &spi1;
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26 usb0 = &usb0;
27 usb1 = &usb1;
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28 };
29
30 chosen {
31 stdout-path = "serial0:115200n8";
32 };
33
34 memory {
35 device_type = "memory";
85d1142e 36 reg = <0x0 0x0 0x0 0x40000000>;
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37 };
38};
39
40&can0 {
41 status = "okay";
42};
43
44&gem0 {
45 status = "okay";
46 phy-handle = <&phy0>;
47 phy-mode = "rgmii-id";
cb9dcc6e 48 phy0: phy@0 {
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49 reg = <0>;
50 max-speed = <100>;
51 };
52};
53
54&gpio {
55 status = "okay";
56};
57
58&i2c0 {
59 status = "okay";
60 clock-frequency = <400000>;
61 eeprom@54 {
62 compatible = "at,24c64";
63 reg = <0x54>;
64 };
65};
66
67&i2c1 {
68 status = "okay";
69 clock-frequency = <400000>;
70 eeprom@55 {
71 compatible = "at,24c64";
72 reg = <0x55>;
73 };
74};
75
76&qspi {
77 status = "okay";
78 flash@0 {
eaae2b5d 79 compatible = "m25p80";
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80 #address-cells = <1>;
81 #size-cells = <1>;
82 reg = <0x0>;
83 spi-tx-bus-width = <1>;
84 spi-rx-bus-width = <4>;
85 spi-max-frequency = <10000000>;
86 partition@qspi-fsbl-uboot { /* for testing purpose */
87 label = "qspi-fsbl-uboot";
88 reg = <0x0 0x100000>;
89 };
90 partition@qspi-linux { /* for testing purpose */
91 label = "qspi-linux";
92 reg = <0x100000 0x500000>;
93 };
94 partition@qspi-device-tree { /* for testing purpose */
95 label = "qspi-device-tree";
96 reg = <0x600000 0x20000>;
97 };
98 partition@qspi-rootfs { /* for testing purpose */
99 label = "qspi-rootfs";
100 reg = <0x620000 0x5E0000>;
101 };
102 };
103};
104
105&sata {
106 status = "okay";
107 ceva,broken-gen2;
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108 /* SATA Phy OOB timing settings */
109 ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
110 ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
111 ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
112 ceva,p0-retry-params = /bits/ 16 <0x0216 0x7F06>;
113 ceva,p1-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
114 ceva,p1-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
115 ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
116 ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>;
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117};
118
119&sdhci0 {
120 status = "okay";
b8bf5539 121 bus-width = <8>;
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122};
123
124&sdhci1 {
125 status = "okay";
126};
127
128&spi0 {
129 status = "okay";
130 num-cs = <1>;
131 spi0_flash0: spi0_flash0@0 {
132 compatible = "m25p80";
133 #address-cells = <1>;
134 #size-cells = <1>;
135 spi-max-frequency = <50000000>;
136 reg = <0>;
137
138 spi0_flash0@00000000 {
139 label = "spi0_flash0";
140 reg = <0x0 0x100000>;
141 };
142 };
143};
144
145&spi1 {
146 status = "okay";
147 num-cs = <1>;
148 spi1_flash0: spi1_flash0@0 {
149 compatible = "m25p80";
150 #address-cells = <1>;
151 #size-cells = <1>;
152 spi-max-frequency = <50000000>;
153 reg = <0>;
154
155 spi1_flash0@00000000 {
156 label = "spi1_flash0";
157 reg = <0x0 0x100000>;
158 };
159 };
160};
161
162&uart0 {
163 status = "okay";
164};
165
166&usb0 {
167 status = "okay";
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168};
169
170&dwc3_0 {
171 status = "okay";
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172 dr_mode = "peripheral";
173 maximum-speed = "high-speed";
174};
175
176&usb1 {
177 status = "okay";
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178};
179
180&dwc3_1 {
181 status = "okay";
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182 dr_mode = "host";
183 maximum-speed = "high-speed";
184};
185
186&watchdog0 {
187 status = "okay";
188};
189
190&xlnx_dp {
191 xlnx,max-pclock-frequency = <200000>;
192};
193
194&xlnx_dpdma {
195 xlnx,axi-clock-freq = <200000000>;
196};