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arm64: zynqmp: Update device tree for gpio
[people/ms/u-boot.git] / arch / arm / dts / zynqmp-zcu102-revA.dts
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1f4f3d33 1/*
23b34d14 2 * dts file for Xilinx ZynqMP ZCU102 RevA
1f4f3d33
MS		 3 *
4 * (C) Copyright 2015, Xilinx, Inc.
5 *
6 * Michal Simek <michal.simek@xilinx.com>
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11/dts-v1/;
12
13#include "zynqmp.dtsi"
14#include "zynqmp-clk.dtsi"
e4e7f2f9 15#include <dt-bindings/gpio/gpio.h>
1f4f3d33
MS		 16
17/ {
18 model = "ZynqMP ZCU102 RevA";
be463451 19 compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
1f4f3d33
MS		 20
21 aliases {
22 ethernet0 = &gem3;
23 gpio0 = &gpio;
24 i2c0 = &i2c0;
25 i2c1 = &i2c1;
26 mmc0 = &sdhci1;
27 rtc0 = &rtc;
28 serial0 = &uart0;
29 serial1 = &uart1;
69d09dd7 30 serial2 = &dcc;
1f4f3d33
MS		 31 spi0 = &qspi;
32 usb0 = &usb0;
33 };
34
35 chosen {
36 bootargs = "earlycon";
37 stdout-path = "serial0:115200n8";
38 };
39
c926e6fb 40 memory@0 {
1f4f3d33
MS		 41 device_type = "memory";
42 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
43 };
4ae78e55 44
e4e7f2f9
MS		 45 gpio-keys {
46 compatible = "gpio-keys";
47 #address-cells = <1>;
48 #size-cells = <0>;
49 autorepeat;
50 sw19 {
51 label = "sw19";
52 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
53 linux,code = <108>; /* down */
54 gpio-key,wakeup;
55 autorepeat;
56 };
57 };
58
4ae78e55
MS		 59 leds {
60 compatible = "gpio-leds";
61 heartbeat_led {
62 label = "heartbeat";
d801ce55 63 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
4ae78e55
MS		 64 linux,default-trigger = "heartbeat";
65 };
66 };
1f4f3d33
MS		 67};
68
69&can1 {
70 status = "okay";
71};
72
69d09dd7
MS		 73&dcc {
74 status = "okay";
75};
76
1f4f3d33
MS		 77/* fpd_dma clk 667MHz, lpd_dma 500MHz */
78&fpd_dma_chan1 {
79 status = "okay";
80 xlnx,include-sg; /* for testing purpose */
81 xlnx,overfetch; /* for testing purpose */
82 xlnx,ratectrl = <0>; /* for testing purpose */
83 xlnx,src-issue = <31>;
84};
85
86&fpd_dma_chan2 {
87 status = "okay";
88 xlnx,ratectrl = <100>; /* for testing purpose */
89 xlnx,src-issue = <4>; /* for testing purpose */
90};
91
92&fpd_dma_chan3 {
93 status = "okay";
94};
95
96&fpd_dma_chan4 {
97 status = "okay";
98 xlnx,include-sg; /* for testing purpose */
99};
100
101&fpd_dma_chan5 {
102 status = "okay";
103};
104
105&fpd_dma_chan6 {
106 status = "okay";
107 xlnx,include-sg; /* for testing purpose */
108};
109
110&fpd_dma_chan7 {
111 status = "okay";
112};
113
114&fpd_dma_chan8 {
115 status = "okay";
116 xlnx,include-sg; /* for testing purpose */
117};
118
119&gem3 {
120 status = "okay";
121 local-mac-address = [00 0a 35 00 02 90];
122 phy-handle = <&phy0>;
123 phy-mode = "rgmii-id";
124 phy0: phy@21 {
125 reg = <21>;
126 ti,rx-internal-delay = <0x8>;
127 ti,tx-internal-delay = <0xa>;
128 ti,fifo-depth = <0x1>;
129 };
130};
131
132&gpio {
133 status = "okay";
134};
135
136&gpu {
137 status = "okay";
138};
139
140&i2c0 {
141 status = "okay";
142 clock-frequency = <400000>;
143
144 tca6416_u97: gpio@20 {
145 /*
146 * Enable all GTs to out from U-Boot
147 * i2c mw 20 6 0 - setup IO to output
148 * i2c mw 20 2 ef - setup output values on pins 0-7
149 * i2c mw 20 3 ff - setup output values on pins 10-17
150 */
151 compatible = "ti,tca6416";
152 reg = <0x20>;
153 gpio-controller;
154 #gpio-cells = <2>;
155 /*
156 * IRQ not connected
157 * Lines:
158 * 0 - PS_GTR_LAN_SEL0
159 * 1 - PS_GTR_LAN_SEL1
160 * 2 - PS_GTR_LAN_SEL2
161 * 3 - PS_GTR_LAN_SEL3
162 * 4 - PCI_CLK_DIR_SEL
163 * 5 - IIC_MUX_RESET_B
164 * 6 - GEM3_EXP_RESET_B
165 * 7, 10 - 17 - not connected
166 */
167
168 gtr_sel0 {
169 gpio-hog;
170 gpios = <0 0>;
171 output-high; /* PCIE = 0, DP = 1 */
172 line-name = "sel0";
173 };
174 gtr_sel1 {
175 gpio-hog;
176 gpios = <1 0>;
177 output-high; /* PCIE = 0, DP = 1 */
178 line-name = "sel1";
179 };
180 gtr_sel2 {
181 gpio-hog;
182 gpios = <2 0>;
183 output-high; /* PCIE = 0, USB0 = 1 */
184 line-name = "sel2";
185 };
186 gtr_sel3 {
187 gpio-hog;
188 gpios = <3 0>;
189 output-high; /* PCIE = 0, SATA = 1 */
190 line-name = "sel3";
191 };
192 };
193
194 tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */
195 compatible = "ti,tca6416";
196 reg = <0x21>;
197 gpio-controller;
198 #gpio-cells = <2>;
199 /*
200 * IRQ not connected
201 * Lines:
202 * 0 - VCCPSPLL_EN
203 * 1 - MGTRAVCC_EN
204 * 2 - MGTRAVTT_EN
205 * 3 - VCCPSDDRPLL_EN
206 * 4 - MIO26_PMU_INPUT_LS
207 * 5 - PL_PMBUS_ALERT
208 * 6 - PS_PMBUS_ALERT
209 * 7 - MAXIM_PMBUS_ALERT
210 * 10 - PL_DDR4_VTERM_EN
211 * 11 - PL_DDR4_VPP_2V5_EN
212 * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
213 * 13 - PS_DIMM_SUSPEND_EN
214 * 14 - PS_DDR4_VTERM_EN
215 * 15 - PS_DDR4_VPP_2V5_EN
216 * 16 - 17 - not connected
217 */
218 };
219
220 i2cswitch@75 { /* u60 */
221 compatible = "nxp,pca9544";
222 #address-cells = <1>;
223 #size-cells = <0>;
224 reg = <0x75>;
225 i2c@0 { /* i2c mw 75 0 1 */
226 #address-cells = <1>;
227 #size-cells = <0>;
228 reg = <0>;
229 /* PS_PMBUS */
230 ina226@40 { /* u76 */
231 compatible = "ti,ina226";
232 reg = <0x40>;
233 shunt-resistor = <5000>;
234 };
235 ina226@41 { /* u77 */
236 compatible = "ti,ina226";
237 reg = <0x41>;
238 shunt-resistor = <5000>;
239 };
240 ina226@42 { /* u78 */
241 compatible = "ti,ina226";
242 reg = <0x42>;
243 shunt-resistor = <5000>;
244 };
245 ina226@43 { /* u87 */
246 compatible = "ti,ina226";
247 reg = <0x43>;
248 shunt-resistor = <5000>;
249 };
250 ina226@44 { /* u85 */
251 compatible = "ti,ina226";
252 reg = <0x44>;
253 shunt-resistor = <5000>;
254 };
255 ina226@45 { /* u86 */
256 compatible = "ti,ina226";
257 reg = <0x45>;
258 shunt-resistor = <5000>;
259 };
260 ina226@46 { /* u93 */
261 compatible = "ti,ina226";
262 reg = <0x46>;
263 shunt-resistor = <5000>;
264 };
265 ina226@47 { /* u88 */
266 compatible = "ti,ina226";
267 reg = <0x47>;
268 shunt-resistor = <5000>;
269 };
270 ina226@4a { /* u15 */
271 compatible = "ti,ina226";
272 reg = <0x4a>;
273 shunt-resistor = <5000>;
274 };
275 ina226@4b { /* u92 */
276 compatible = "ti,ina226";
277 reg = <0x4b>;
278 shunt-resistor = <5000>;
279 };
280 };
281 i2c@1 { /* i2c mw 75 0 1 */
282 #address-cells = <1>;
283 #size-cells = <0>;
284 reg = <1>;
285 /* PL_PMBUS */
286 ina226@40 { /* u79 */
287 compatible = "ti,ina226";
288 reg = <0x40>;
289 shunt-resistor = <2000>;
290 };
291 ina226@41 { /* u81 */
292 compatible = "ti,ina226";
293 reg = <0x41>;
294 shunt-resistor = <5000>;
295 };
296 ina226@42 { /* u80 */
297 compatible = "ti,ina226";
298 reg = <0x42>;
299 shunt-resistor = <5000>;
300 };
301 ina226@43 { /* u84 */
302 compatible = "ti,ina226";
303 reg = <0x43>;
304 shunt-resistor = <5000>;
305 };
306 ina226@44 { /* u16 */
307 compatible = "ti,ina226";
308 reg = <0x44>;
309 shunt-resistor = <5000>;
310 };
311 ina226@45 { /* u65 */
312 compatible = "ti,ina226";
313 reg = <0x45>;
314 shunt-resistor = <5000>;
315 };
316 ina226@46 { /* u74 */
317 compatible = "ti,ina226";
318 reg = <0x46>;
319 shunt-resistor = <5000>;
320 };
321 ina226@47 { /* u75 */
322 compatible = "ti,ina226";
323 reg = <0x47>;
324 shunt-resistor = <5000>;
325 };
326 };
327 i2c@2 { /* i2c mw 75 0 1 */
328 #address-cells = <1>;
329 #size-cells = <0>;
330 reg = <2>;
331 /* MAXIM_PMBUS - 00 */
332 max15301@a { /* u46 */
333 compatible = "max15301";
334 reg = <0xa>;
335 };
336 max15303@b { /* u4 */
337 compatible = "max15303";
338 reg = <0xb>;
339 };
340 max15303@10 { /* u13 */
341 compatible = "max15303";
342 reg = <0x10>;
343 };
344 max15301@13 { /* u47 */
345 compatible = "max15301";
346 reg = <0x13>;
347 };
348 max15303@14 { /* u7 */
349 compatible = "max15303";
350 reg = <0x14>;
351 };
352 max15303@15 { /* u6 */
353 compatible = "max15303";
354 reg = <0x15>;
355 };
356 max15303@16 { /* u10 */
357 compatible = "max15303";
358 reg = <0x16>;
359 };
360 max15303@17 { /* u9 */
361 compatible = "max15303";
362 reg = <0x17>;
363 };
364 max15301@18 { /* u63 */
365 compatible = "max15301";
366 reg = <0x18>;
367 };
368 max15303@1a { /* u49 */
369 compatible = "max15303";
370 reg = <0x1a>;
371 };
372 max15303@1d { /* u18 */
373 compatible = "max15303";
374 reg = <0x1d>;
375 };
376 max15303@20 { /* u8 */
377 compatible = "max15303";
378 status = "disabled"; /* unreachable */
379 reg = <0x20>;
380 };
381
382/* drivers/hwmon/pmbus/Kconfig:86: be called max20751.
383drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o
384*/
385 max20751@72 { /* u95 FIXME - not detected */
386 compatible = "max20751";
387 reg = <0x72>;
388 };
389 max20751@73 { /* u96 FIXME - not detected */
390 compatible = "max20751";
391 reg = <0x73>;
392 };
393 };
394 /* Bus 3 is not connected */
395 };
396
bc019369 397 /* FIXME PMOD - j160 */
1f4f3d33
MS		 398 /* FIXME MSP430F - u41 - not detected */
399};
400
401&i2c1 {
402 status = "okay";
403 clock-frequency = <400000>;
404 /* FIXME PL i2c via PCA9306 - u45 */
405 /* FIXME MSP430 - u41 - not detected */
406 i2cswitch@74 { /* u34 */
407 compatible = "nxp,pca9548";
408 #address-cells = <1>;
409 #size-cells = <0>;
410 reg = <0x74>;
411 i2c@0 { /* i2c mw 74 0 1 */
412 #address-cells = <1>;
413 #size-cells = <0>;
414 reg = <0>;
415 /*
416 * IIC_EEPROM 1kB memory which uses 256B blocks
417 * where every block has different address.
418 * 0 - 256B address 0x54
419 * 256B - 512B address 0x55
420 * 512B - 768B address 0x56
421 * 768B - 1024B address 0x57
422 */
423 eeprom@54 { /* u23 */
424 compatible = "at,24c08";
425 reg = <0x54>;
426 };
427 };
428 i2c@1 { /* i2c mw 74 0 2 */
429 #address-cells = <1>;
430 #size-cells = <0>;
431 reg = <1>;
432 si5341: clock-generator1@36 { /* SI5341 - u69 */
433 compatible = "si5341";
434 reg = <0x36>;
435 };
436
437 };
438 i2c@2 { /* i2c mw 74 0 4 */
439 #address-cells = <1>;
440 #size-cells = <0>;
441 reg = <2>;
442 si570_1: clock-generator2@5d { /* USER SI570 - u42 */
443 #clock-cells = <0>;
444 compatible = "silabs,si570";
445 reg = <0x5d>;
446 temperature-stability = <50>;
447 factory-fout = <300000000>;
448 clock-frequency = <300000000>;
449 };
450 };
451 i2c@3 { /* i2c mw 74 0 8 */
452 #address-cells = <1>;
453 #size-cells = <0>;
454 reg = <3>;
455 si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */
456 #clock-cells = <0>;
457 compatible = "silabs,si570";
458 reg = <0x5d>;
459 temperature-stability = <50>; /* copy from zc702 */
460 factory-fout = <156250000>;
461 clock-frequency = <148500000>;
462 };
463 };
464 i2c@4 { /* i2c mw 74 0 10 */
465 #address-cells = <1>;
466 #size-cells = <0>;
467 reg = <4>;
468 si5328: clock-generator4@69 {/* SI5328 - u20 */
469 compatible = "silabs,si5328";
470 reg = <0x69>;
471 };
472 };
473 /* 5 - 7 unconnected */
474 };
475
476 i2cswitch@75 {
477 compatible = "nxp,pca9548"; /* u135 */
478 #address-cells = <1>;
479 #size-cells = <0>;
480 reg = <0x75>;
481
482 i2c@0 {
483 #address-cells = <1>;
484 #size-cells = <0>;
485 reg = <0>;
486 /* HPC0_IIC */
487 };
488 i2c@1 {
489 #address-cells = <1>;
490 #size-cells = <0>;
491 reg = <1>;
492 /* HPC1_IIC */
493 };
494 i2c@2 {
495 #address-cells = <1>;
496 #size-cells = <0>;
497 reg = <2>;
498 /* SYSMON */
499 };
500 i2c@3 { /* i2c mw 75 0 8 */
501 #address-cells = <1>;
502 #size-cells = <0>;
503 reg = <3>;
504 /* DDR4 SODIMM */
505 dev@19 { /* u-boot detection */
506 compatible = "xxx";
507 reg = <0x19>;
508 };
509 dev@30 { /* u-boot detection */
510 compatible = "xxx";
511 reg = <0x30>;
512 };
513 dev@35 { /* u-boot detection */
514 compatible = "xxx";
515 reg = <0x35>;
516 };
517 dev@36 { /* u-boot detection */
518 compatible = "xxx";
519 reg = <0x36>;
520 };
521 dev@51 { /* u-boot detection - maybe SPD */
522 compatible = "xxx";
523 reg = <0x51>;
524 };
525 };
526 i2c@4 {
527 #address-cells = <1>;
528 #size-cells = <0>;
529 reg = <4>;
530 /* SEP 3 */
531 };
532 i2c@5 {
533 #address-cells = <1>;
534 #size-cells = <0>;
535 reg = <5>;
536 /* SEP 2 */
537 };
538 i2c@6 {
539 #address-cells = <1>;
540 #size-cells = <0>;
541 reg = <6>;
542 /* SEP 1 */
543 };
544 i2c@7 {
545 #address-cells = <1>;
546 #size-cells = <0>;
547 reg = <7>;
548 /* SEP 0 */
549 };
550 };
551};
552
553&pcie {
554/* status = "okay"; */
555};
556
557&qspi {
558 status = "okay";
559 is-dual = <1>;
560 flash@0 {
561 compatible = "m25p80"; /* 32MB */
562 #address-cells = <1>;
563 #size-cells = <1>;
564 reg = <0x0>;
565 spi-tx-bus-width = <1>;
566 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
567 spi-max-frequency = <108000000>; /* Based on DC1 spec */
568 partition@qspi-fsbl-uboot { /* for testing purpose */
569 label = "qspi-fsbl-uboot";
570 reg = <0x0 0x100000>;
571 };
572 partition@qspi-linux { /* for testing purpose */
573 label = "qspi-linux";
574 reg = <0x100000 0x500000>;
575 };
576 partition@qspi-device-tree { /* for testing purpose */
577 label = "qspi-device-tree";
578 reg = <0x600000 0x20000>;
579 };
580 partition@qspi-rootfs { /* for testing purpose */
581 label = "qspi-rootfs";
582 reg = <0x620000 0x5E0000>;
583 };
584 };
585};
586
587&rtc {
588 status = "okay";
589};
590
591&sata {
592 status = "okay";
593 /* SATA OOB timing settings */
594 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
595 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
596 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
597 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
598 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
599 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
600 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
601 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
602};
603
604/* SD1 with level shifter */
605&sdhci1 {
606 status = "okay";
607 no-1-8-v; /* for 1.0 silicon */
0488a5e1 608 xlnx,mio_bank = <1>;
1f4f3d33
MS		 609};
610
611&uart0 {
612 status = "okay";
613};
614
615&uart1 {
616 status = "okay";
617};
618
619/* ULPI SMSC USB3320 */
620&usb0 {
621 status = "okay";
622};
623
624&dwc3_0 {
625 status = "okay";
626 dr_mode = "host";
627};
628
629&xilinx_drm {
630 status = "okay";
631 clocks = <&si570_1>;
632};
633
634&xlnx_dp {
635 status = "okay";
636};
637
638&xlnx_dp_sub {
639 status = "okay";
640 xlnx,vid-clk-pl;
641};
642
643&xlnx_dp_snd_pcm0 {
644 status = "okay";
645};
646
647&xlnx_dp_snd_pcm1 {
648 status = "okay";
649};
650
651&xlnx_dp_snd_card {
652 status = "okay";
653};
654
655&xlnx_dp_snd_codec0 {
656 status = "okay";
657};
658
659&xlnx_dpdma {
660 status = "okay";
661};
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