projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 44303dfa MS |
1 | /* |
| 2 | * dts file for Xilinx ZynqMP | |
| 3 | * | |
| 4 | * (C) Copyright 2014 - 2015, Xilinx, Inc. | |
| 5 | * | |
| 6 | * Michal Simek <michal.simek@xilinx.com> | |
| 7 | * | |
| 8 | * SPDX-License-Identifier: GPL-2.0+ | |
| 9 | */ | |
| 10 | / { | |
| 11 | compatible = "xlnx,zynqmp"; | |
| 12 | #address-cells = <2>; | |
| 85d1142e | 13 | #size-cells = <2>; |
| 44303dfa MS |
14 | |
| 15 | cpus { | |
| 16 | #address-cells = <1>; | |
| 17 | #size-cells = <0>; | |
| 18 | ||
| 19 | cpu@0 { | |
| 20 | compatible = "arm,cortex-a53", "arm,armv8"; | |
| 21 | device_type = "cpu"; | |
| 22 | enable-method = "psci"; | |
| 23 | reg = <0x0>; | |
| 24 | }; | |
| 25 | ||
| 26 | cpu@1 { | |
| 27 | compatible = "arm,cortex-a53", "arm,armv8"; | |
| 28 | device_type = "cpu"; | |
| 29 | enable-method = "psci"; | |
| 30 | reg = <0x1>; | |
| 31 | }; | |
| 32 | ||
| 33 | cpu@2 { | |
| 34 | compatible = "arm,cortex-a53", "arm,armv8"; | |
| 35 | device_type = "cpu"; | |
| 36 | enable-method = "psci"; | |
| 37 | reg = <0x2>; | |
| 38 | }; | |
| 39 | ||
| 40 | cpu@3 { | |
| 41 | compatible = "arm,cortex-a53", "arm,armv8"; | |
| 42 | device_type = "cpu"; | |
| 43 | enable-method = "psci"; | |
| 44 | reg = <0x3>; | |
| 45 | }; | |
| 46 | }; | |
| 47 | ||
| 8f4e3972 SB |
48 | power-domains { |
| 49 | compatible = "xlnx,zynqmp-genpd"; | |
| 50 | ||
| 51 | pd_usb0: pd-usb0 { | |
| 52 | #power-domain-cells = <0x0>; | |
| 53 | pd-id = <0x16>; | |
| 54 | }; | |
| 55 | ||
| 56 | pd_usb1: pd-usb1 { | |
| 57 | #power-domain-cells = <0x0>; | |
| 58 | pd-id = <0x17>; | |
| 59 | }; | |
| 60 | ||
| 61 | pd_sata: pd-sata { | |
| 62 | #power-domain-cells = <0x0>; | |
| 63 | pd-id = <0x1c>; | |
| 64 | }; | |
| 65 | ||
| 66 | pd_spi0: pd-spi0 { | |
| 67 | #power-domain-cells = <0x0>; | |
| 68 | pd-id = <0x23>; | |
| 69 | }; | |
| 70 | ||
| 71 | pd_spi1: pd-spi1 { | |
| 72 | #power-domain-cells = <0x0>; | |
| 73 | pd-id = <0x24>; | |
| 74 | }; | |
| 75 | ||
| 76 | pd_uart0: pd-uart0 { | |
| 77 | #power-domain-cells = <0x0>; | |
| 78 | pd-id = <0x21>; | |
| 79 | }; | |
| 80 | ||
| 81 | pd_uart1: pd-uart1 { | |
| 82 | #power-domain-cells = <0x0>; | |
| 83 | pd-id = <0x22>; | |
| 84 | }; | |
| 85 | ||
| 86 | pd_eth0: pd-eth0 { | |
| 87 | #power-domain-cells = <0x0>; | |
| 88 | pd-id = <0x1d>; | |
| 89 | }; | |
| 90 | ||
| 91 | pd_eth1: pd-eth1 { | |
| 92 | #power-domain-cells = <0x0>; | |
| 93 | pd-id = <0x1e>; | |
| 94 | }; | |
| 95 | ||
| 96 | pd_eth2: pd-eth2 { | |
| 97 | #power-domain-cells = <0x0>; | |
| 98 | pd-id = <0x1f>; | |
| 99 | }; | |
| 100 | ||
| 101 | pd_eth3: pd-eth3 { | |
| 102 | #power-domain-cells = <0x0>; | |
| 103 | pd-id = <0x20>; | |
| 104 | }; | |
| 105 | ||
| 106 | pd_i2c0: pd-i2c0 { | |
| 107 | #power-domain-cells = <0x0>; | |
| 108 | pd-id = <0x25>; | |
| 109 | }; | |
| 110 | ||
| 111 | pd_i2c1: pd-i2c1 { | |
| 112 | #power-domain-cells = <0x0>; | |
| 113 | pd-id = <0x26>; | |
| 114 | }; | |
| 115 | ||
| 116 | pd_dp: pd-dp { | |
| 117 | /* fixme: what to attach to */ | |
| 118 | #power-domain-cells = <0x0>; | |
| 119 | pd-id = <0x29>; | |
| 120 | }; | |
| 121 | ||
| 122 | pd_gdma: pd-gdma { | |
| 123 | #power-domain-cells = <0x0>; | |
| 124 | pd-id = <0x2a>; | |
| 125 | }; | |
| 126 | ||
| 127 | pd_adma: pd-adma { | |
| 128 | #power-domain-cells = <0x0>; | |
| 129 | pd-id = <0x2b>; | |
| 130 | }; | |
| 131 | ||
| 132 | pd_ttc0: pd-ttc0 { | |
| 133 | #power-domain-cells = <0x0>; | |
| 134 | pd-id = <0x18>; | |
| 135 | }; | |
| 136 | ||
| 137 | pd_ttc1: pd-ttc1 { | |
| 138 | #power-domain-cells = <0x0>; | |
| 139 | pd-id = <0x19>; | |
| 140 | }; | |
| 141 | ||
| 142 | pd_ttc2: pd-ttc2 { | |
| 143 | #power-domain-cells = <0x0>; | |
| 144 | pd-id = <0x1a>; | |
| 145 | }; | |
| 146 | ||
| 147 | pd_ttc3: pd-ttc3 { | |
| 148 | #power-domain-cells = <0x0>; | |
| 149 | pd-id = <0x1b>; | |
| 150 | }; | |
| 151 | ||
| 152 | pd_sd0: pd-sd0 { | |
| 153 | #power-domain-cells = <0x0>; | |
| 154 | pd-id = <0x27>; | |
| 155 | }; | |
| 156 | ||
| 157 | pd_sd1: pd-sd1 { | |
| 158 | #power-domain-cells = <0x0>; | |
| 159 | pd-id = <0x28>; | |
| 160 | }; | |
| 161 | ||
| 162 | pd_nand: pd-nand { | |
| 163 | #power-domain-cells = <0x0>; | |
| 164 | pd-id = <0x2c>; | |
| 165 | }; | |
| 166 | ||
| 167 | pd_qspi: pd-qspi { | |
| 168 | #power-domain-cells = <0x0>; | |
| 169 | pd-id = <0x2d>; | |
| 170 | }; | |
| 171 | ||
| 172 | pd_gpio: pd-gpio { | |
| 173 | #power-domain-cells = <0x0>; | |
| 174 | pd-id = <0x2e>; | |
| 175 | }; | |
| 176 | ||
| 177 | pd_can0: pd-can0 { | |
| 178 | #power-domain-cells = <0x0>; | |
| 179 | pd-id = <0x2f>; | |
| 180 | }; | |
| 181 | ||
| 182 | pd_can1: pd-can1 { | |
| 183 | #power-domain-cells = <0x0>; | |
| 184 | pd-id = <0x30>; | |
| 185 | }; | |
| 186 | ||
| 187 | pd_ddr: pd-ddr { | |
| 188 | #power-domain-cells = <0x0>; | |
| 189 | pd-id = <0x37>; | |
| 190 | }; | |
| 191 | ||
| 192 | pd_apll: pd-apll { | |
| 193 | #power-domain-cells = <0x0>; | |
| 194 | pd-id = <0x32>; | |
| 195 | }; | |
| 196 | ||
| 197 | pd_vpll: pd-vpll { | |
| 198 | #power-domain-cells = <0x0>; | |
| 199 | pd-id = <0x33>; | |
| 200 | }; | |
| 201 | ||
| 202 | pd_dpll: pd-dpll { | |
| 203 | #power-domain-cells = <0x0>; | |
| 204 | pd-id = <0x34>; | |
| 205 | }; | |
| 206 | ||
| 207 | pd_rpll: pd-rpll { | |
| 208 | #power-domain-cells = <0x0>; | |
| 209 | pd-id = <0x35>; | |
| 210 | }; | |
| 211 | ||
| 212 | pd_iopll: pd-iopll { | |
| 213 | #power-domain-cells = <0x0>; | |
| 214 | pd-id = <0x36>; | |
| 215 | }; | |
| 216 | }; | |
| 217 | ||
| 44303dfa MS |
218 | pmu { |
| 219 | compatible = "arm,armv8-pmuv3"; | |
| 14cd9eab | 220 | interrupt-parent = <&gic>; |
| 44303dfa MS |
221 | interrupts = <0 143 4>, |
| 222 | <0 144 4>, | |
| 223 | <0 145 4>, | |
| 224 | <0 146 4>; | |
| 225 | }; | |
| 226 | ||
| 227 | psci { | |
| 228 | compatible = "arm,psci-0.2"; | |
| 229 | method = "smc"; | |
| 230 | }; | |
| 231 | ||
| 232 | firmware { | |
| 233 | compatible = "xlnx,zynqmp-pm"; | |
| 234 | method = "smc"; | |
| 235 | }; | |
| 236 | ||
| 237 | timer { | |
| 238 | compatible = "arm,armv8-timer"; | |
| 239 | interrupt-parent = <&gic>; | |
| 240 | interrupts = <1 13 0xf01>, | |
| 241 | <1 14 0xf01>, | |
| 242 | <1 11 0xf01>, | |
| 243 | <1 10 0xf01>; | |
| 244 | }; | |
| 245 | ||
| 246 | amba_apu: amba_apu { | |
| 247 | compatible = "simple-bus"; | |
| 248 | #address-cells = <2>; | |
| 249 | #size-cells = <1>; | |
| 85d1142e | 250 | ranges = <0 0 0 0 0xffffffff>; |
| 44303dfa MS |
251 | |
| 252 | gic: interrupt-controller@f9010000 { | |
| 253 | compatible = "arm,gic-400", "arm,cortex-a15-gic"; | |
| 254 | #interrupt-cells = <3>; | |
| 255 | reg = <0x0 0xf9010000 0x10000>, | |
| 256 | <0x0 0xf902f000 0x2000>, | |
| 257 | <0x0 0xf9040000 0x20000>, | |
| 258 | <0x0 0xf906f000 0x2000>; | |
| 259 | interrupt-controller; | |
| 260 | interrupt-parent = <&gic>; | |
| 261 | interrupts = <1 9 0xf04>; | |
| 262 | }; | |
| 263 | }; | |
| 264 | ||
| 265 | amba: amba { | |
| 266 | compatible = "simple-bus"; | |
| 267 | #address-cells = <2>; | |
| 268 | #size-cells = <1>; | |
| 85d1142e | 269 | ranges = <0 0 0 0 0xffffffff>; |
| 44303dfa MS |
270 | |
| 271 | can0: can@ff060000 { | |
| 272 | compatible = "xlnx,zynq-can-1.0"; | |
| 273 | status = "disabled"; | |
| 274 | clock-names = "can_clk", "pclk"; | |
| 275 | reg = <0x0 0xff060000 0x1000>; | |
| 276 | interrupts = <0 23 4>; | |
| 277 | interrupt-parent = <&gic>; | |
| 278 | tx-fifo-depth = <0x40>; | |
| 279 | rx-fifo-depth = <0x40>; | |
| 8f4e3972 | 280 | power-domains = <&pd_can0>; |
| 44303dfa MS |
281 | }; |
| 282 | ||
| 283 | can1: can@ff070000 { | |
| 284 | compatible = "xlnx,zynq-can-1.0"; | |
| 285 | status = "disabled"; | |
| 286 | clock-names = "can_clk", "pclk"; | |
| 287 | reg = <0x0 0xff070000 0x1000>; | |
| 288 | interrupts = <0 24 4>; | |
| 289 | interrupt-parent = <&gic>; | |
| 290 | tx-fifo-depth = <0x40>; | |
| 291 | rx-fifo-depth = <0x40>; | |
| 8f4e3972 | 292 | power-domains = <&pd_can1>; |
| 44303dfa MS |
293 | }; |
| 294 | ||
| ff50d21b MS |
295 | cci: cci@fd6e0000 { |
| 296 | compatible = "arm,cci-400"; | |
| 297 | reg = <0x0 0xfd6e0000 0x9000>; | |
| 298 | ranges = <0x0 0x0 0xfd6e0000 0x10000>; | |
| 299 | #address-cells = <1>; | |
| 300 | #size-cells = <1>; | |
| 301 | ||
| 302 | pmu@9000 { | |
| 303 | compatible = "arm,cci-400-pmu,r1"; | |
| 304 | reg = <0x9000 0x5000>; | |
| 305 | interrupt-parent = <&gic>; | |
| 306 | interrupts = <0 123 4>, | |
| 307 | <0 123 4>, | |
| 308 | <0 123 4>, | |
| 309 | <0 123 4>, | |
| 310 | <0 123 4>; | |
| 311 | }; | |
| 312 | }; | |
| 313 | ||
| 44303dfa MS |
314 | /* GDMA */ |
| 315 | fpd_dma_chan1: dma@fd500000 { | |
| 316 | status = "disabled"; | |
| 317 | compatible = "xlnx,zynqmp-dma-1.0"; | |
| 318 | reg = <0x0 0xfd500000 0x1000>; | |
| 319 | interrupt-parent = <&gic>; | |
| 320 | interrupts = <0 124 4>; | |
| b34d11de | 321 | clock-names = "clk_main", "clk_apb"; |
| 44303dfa MS |
322 | xlnx,id = <0>; |
| 323 | xlnx,bus-width = <128>; | |
| 8f4e3972 | 324 | power-domains = <&pd_gdma>; |
| 44303dfa MS |
325 | }; |
| 326 | ||
| 327 | fpd_dma_chan2: dma@fd510000 { | |
| 328 | status = "disabled"; | |
| 329 | compatible = "xlnx,zynqmp-dma-1.0"; | |
| 330 | reg = <0x0 0xfd510000 0x1000>; | |
| 331 | interrupt-parent = <&gic>; | |
| 332 | interrupts = <0 125 4>; | |
| b34d11de | 333 | clock-names = "clk_main", "clk_apb"; |
| 44303dfa MS |
334 | xlnx,id = <1>; |
| 335 | xlnx,bus-width = <128>; | |
| 8f4e3972 | 336 | power-domains = <&pd_gdma>; |
| 44303dfa MS |
337 | }; |
| 338 | ||
| 339 | fpd_dma_chan3: dma@fd520000 { | |
| 340 | status = "disabled"; | |
| 341 | compatible = "xlnx,zynqmp-dma-1.0"; | |
| 342 | reg = <0x0 0xfd520000 0x1000>; | |
| 343 | interrupt-parent = <&gic>; | |
| 344 | interrupts = <0 126 4>; | |
| b34d11de | 345 | clock-names = "clk_main", "clk_apb"; |
| 44303dfa MS |
346 | xlnx,id = <2>; |
| 347 | xlnx,bus-width = <128>; | |
| 8f4e3972 | 348 | power-domains = <&pd_gdma>; |
| 44303dfa MS |
349 | }; |
| 350 | ||
| 351 | fpd_dma_chan4: dma@fd530000 { | |
| 352 | status = "disabled"; | |
| 353 | compatible = "xlnx,zynqmp-dma-1.0"; | |
| 354 | reg = <0x0 0xfd530000 0x1000>; | |
| 355 | interrupt-parent = <&gic>; | |
| 356 | interrupts = <0 127 4>; | |
| b34d11de | 357 | clock-names = "clk_main", "clk_apb"; |
| 44303dfa MS |
358 | xlnx,id = <3>; |
| 359 | xlnx,bus-width = <128>; | |
| 8f4e3972 | 360 | power-domains = <&pd_gdma>; |
| 44303dfa MS |
361 | }; |
| 362 | ||
| 363 | fpd_dma_chan5: dma@fd540000 { | |
| 364 | status = "disabled"; | |
| 365 | compatible = "xlnx,zynqmp-dma-1.0"; | |
| 366 | reg = <0x0 0xfd540000 0x1000>; | |
| 367 | interrupt-parent = <&gic>; | |
| 368 | interrupts = <0 128 4>; | |
| b34d11de | 369 | clock-names = "clk_main", "clk_apb"; |
| 44303dfa MS |
370 | xlnx,id = <4>; |
| 371 | xlnx,bus-width = <128>; | |
| 8f4e3972 | 372 | power-domains = <&pd_gdma>; |
| 44303dfa MS |
373 | }; |
| 374 | ||
| 375 | fpd_dma_chan6: dma@fd550000 { | |
| 376 | status = "disabled"; | |
| 377 | compatible = "xlnx,zynqmp-dma-1.0"; | |
| 378 | reg = <0x0 0xfd550000 0x1000>; | |
| 379 | interrupt-parent = <&gic>; | |
| 380 | interrupts = <0 129 4>; | |
| b34d11de | 381 | clock-names = "clk_main", "clk_apb"; |
| 44303dfa MS |
382 | xlnx,id = <5>; |
| 383 | xlnx,bus-width = <128>; | |
| 8f4e3972 | 384 | power-domains = <&pd_gdma>; |
| 44303dfa MS |
385 | }; |
| 386 | ||
| 387 | fpd_dma_chan7: dma@fd560000 { | |
| 388 | status = "disabled"; | |
| 389 | compatible = "xlnx,zynqmp-dma-1.0"; | |
| 390 | reg = <0x0 0xfd560000 0x1000>; | |
| 391 | interrupt-parent = <&gic>; | |
| 392 | interrupts = <0 130 4>; | |
| b34d11de | 393 | clock-names = "clk_main", "clk_apb"; |
| 44303dfa MS |
394 | xlnx,id = <6>; |
| 395 | xlnx,bus-width = <128>; | |
| 8f4e3972 | 396 | power-domains = <&pd_gdma>; |
| 44303dfa MS |
397 | }; |
| 398 | ||
| 399 | fpd_dma_chan8: dma@fd570000 { | |
| 400 | status = "disabled"; | |
| 401 | compatible = "xlnx,zynqmp-dma-1.0"; | |
| 402 | reg = <0x0 0xfd570000 0x1000>; | |
| 403 | interrupt-parent = <&gic>; | |
| 404 | interrupts = <0 131 4>; | |
| b34d11de | 405 | clock-names = "clk_main", "clk_apb"; |
| 44303dfa MS |
406 | xlnx,id = <7>; |
| 407 | xlnx,bus-width = <128>; | |
| 8f4e3972 | 408 | power-domains = <&pd_gdma>; |
| 44303dfa MS |
409 | }; |
| 410 | ||
| 411 | gpu: gpu@fd4b0000 { | |
| 412 | status = "disabled"; | |
| 413 | compatible = "arm,mali-400", "arm,mali-utgard"; | |
| 414 | reg = <0x0 0xfd4b0000 0x30000>; | |
| 415 | interrupt-parent = <&gic>; | |
| 416 | interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; | |
| 417 | interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; | |
| 418 | }; | |
| 419 | ||
| 420 | /* ADMA */ | |
| 421 | lpd_dma_chan1: dma@ffa80000 { | |
| 422 | status = "disabled"; | |
| 423 | compatible = "xlnx,zynqmp-dma-1.0"; | |
| 424 | reg = <0x0 0xffa80000 0x1000>; | |
| 425 | interrupt-parent = <&gic>; | |
| 426 | interrupts = <0 77 4>; | |
| 427 | xlnx,id = <0>; | |
| 428 | xlnx,bus-width = <64>; | |
| 8f4e3972 | 429 | power-domains = <&pd_adma>; |
| 44303dfa MS |
430 | }; |
| 431 | ||
| 432 | lpd_dma_chan2: dma@ffa90000 { | |
| 433 | status = "disabled"; | |
| 434 | compatible = "xlnx,zynqmp-dma-1.0"; | |
| 435 | reg = <0x0 0xffa90000 0x1000>; | |
| 436 | interrupt-parent = <&gic>; | |
| 437 | interrupts = <0 78 4>; | |
| 438 | xlnx,id = <1>; | |
| 439 | xlnx,bus-width = <64>; | |
| 8f4e3972 | 440 | power-domains = <&pd_adma>; |
| 44303dfa MS |
441 | }; |
| 442 | ||
| 443 | lpd_dma_chan3: dma@ffaa0000 { | |
| 444 | status = "disabled"; | |
| 445 | compatible = "xlnx,zynqmp-dma-1.0"; | |
| 446 | reg = <0x0 0xffaa0000 0x1000>; | |
| 447 | interrupt-parent = <&gic>; | |
| 448 | interrupts = <0 79 4>; | |
| 449 | xlnx,id = <2>; | |
| 450 | xlnx,bus-width = <64>; | |
| 8f4e3972 | 451 | power-domains = <&pd_adma>; |
| 44303dfa MS |
452 | }; |
| 453 | ||
| 454 | lpd_dma_chan4: dma@ffab0000 { | |
| 455 | status = "disabled"; | |
| 456 | compatible = "xlnx,zynqmp-dma-1.0"; | |
| 457 | reg = <0x0 0xffab0000 0x1000>; | |
| 458 | interrupt-parent = <&gic>; | |
| 459 | interrupts = <0 80 4>; | |
| 460 | xlnx,id = <3>; | |
| 461 | xlnx,bus-width = <64>; | |
| 8f4e3972 | 462 | power-domains = <&pd_adma>; |
| 44303dfa MS |
463 | }; |
| 464 | ||
| 465 | lpd_dma_chan5: dma@ffac0000 { | |
| 466 | status = "disabled"; | |
| 467 | compatible = "xlnx,zynqmp-dma-1.0"; | |
| 468 | reg = <0x0 0xffac0000 0x1000>; | |
| 469 | interrupt-parent = <&gic>; | |
| 470 | interrupts = <0 81 4>; | |
| 471 | xlnx,id = <4>; | |
| 472 | xlnx,bus-width = <64>; | |
| 8f4e3972 | 473 | power-domains = <&pd_adma>; |
| 44303dfa MS |
474 | }; |
| 475 | ||
| 476 | lpd_dma_chan6: dma@ffad0000 { | |
| 477 | status = "disabled"; | |
| 478 | compatible = "xlnx,zynqmp-dma-1.0"; | |
| 479 | reg = <0x0 0xffad0000 0x1000>; | |
| 480 | interrupt-parent = <&gic>; | |
| 481 | interrupts = <0 82 4>; | |
| 482 | xlnx,id = <5>; | |
| 483 | xlnx,bus-width = <64>; | |
| 8f4e3972 | 484 | power-domains = <&pd_adma>; |
| 44303dfa MS |
485 | }; |
| 486 | ||
| 487 | lpd_dma_chan7: dma@ffae0000 { | |
| 488 | status = "disabled"; | |
| 489 | compatible = "xlnx,zynqmp-dma-1.0"; | |
| 490 | reg = <0x0 0xffae0000 0x1000>; | |
| 491 | interrupt-parent = <&gic>; | |
| 492 | interrupts = <0 83 4>; | |
| 493 | xlnx,id = <6>; | |
| 494 | xlnx,bus-width = <64>; | |
| 8f4e3972 | 495 | power-domains = <&pd_adma>; |
| 44303dfa MS |
496 | }; |
| 497 | ||
| 498 | lpd_dma_chan8: dma@ffaf0000 { | |
| 499 | status = "disabled"; | |
| 500 | compatible = "xlnx,zynqmp-dma-1.0"; | |
| 501 | reg = <0x0 0xffaf0000 0x1000>; | |
| 502 | interrupt-parent = <&gic>; | |
| 503 | interrupts = <0 84 4>; | |
| 504 | xlnx,id = <7>; | |
| 505 | xlnx,bus-width = <64>; | |
| 8f4e3972 | 506 | power-domains = <&pd_adma>; |
| 44303dfa MS |
507 | }; |
| 508 | ||
| 90869009 NSR |
509 | mc: memory-controller@fd070000 { |
| 510 | compatible = "xlnx,zynqmp-ddrc-2.40a"; | |
| 511 | reg = <0x0 0xfd070000 0x30000>; | |
| 512 | interrupt-parent = <&gic>; | |
| 513 | interrupts = <0 112 4>; | |
| 514 | }; | |
| 515 | ||
| 44303dfa MS |
516 | nand0: nand@ff100000 { |
| 517 | compatible = "arasan,nfc-v3p10"; | |
| 518 | status = "disabled"; | |
| 519 | reg = <0x0 0xff100000 0x1000>; | |
| 520 | clock-names = "clk_sys", "clk_flash"; | |
| 521 | interrupt-parent = <&gic>; | |
| 522 | interrupts = <0 14 4>; | |
| 523 | #address-cells = <2>; | |
| 524 | #size-cells = <1>; | |
| 8f4e3972 | 525 | power-domains = <&pd_nand>; |
| 44303dfa MS |
526 | }; |
| 527 | ||
| 528 | gem0: ethernet@ff0b0000 { | |
| da2ad784 | 529 | compatible = "cdns,zynqmp-gem"; |
| 44303dfa MS |
530 | status = "disabled"; |
| 531 | interrupt-parent = <&gic>; | |
| 532 | interrupts = <0 57 4>, <0 57 4>; | |
| 533 | reg = <0x0 0xff0b0000 0x1000>; | |
| 534 | clock-names = "pclk", "hclk", "tx_clk"; | |
| 535 | #address-cells = <1>; | |
| 536 | #size-cells = <0>; | |
| 7f1d7d97 | 537 | #stream-id-cells = <1>; |
| 8f4e3972 | 538 | power-domains = <&pd_eth0>; |
| 44303dfa MS |
539 | }; |
| 540 | ||
| 541 | gem1: ethernet@ff0c0000 { | |
| da2ad784 | 542 | compatible = "cdns,zynqmp-gem"; |
| 44303dfa MS |
543 | status = "disabled"; |
| 544 | interrupt-parent = <&gic>; | |
| 545 | interrupts = <0 59 4>, <0 59 4>; | |
| 546 | reg = <0x0 0xff0c0000 0x1000>; | |
| 547 | clock-names = "pclk", "hclk", "tx_clk"; | |
| 548 | #address-cells = <1>; | |
| 549 | #size-cells = <0>; | |
| 7f1d7d97 | 550 | #stream-id-cells = <1>; |
| 8f4e3972 | 551 | power-domains = <&pd_eth1>; |
| 44303dfa MS |
552 | }; |
| 553 | ||
| 554 | gem2: ethernet@ff0d0000 { | |
| da2ad784 | 555 | compatible = "cdns,zynqmp-gem"; |
| 44303dfa MS |
556 | status = "disabled"; |
| 557 | interrupt-parent = <&gic>; | |
| 558 | interrupts = <0 61 4>, <0 61 4>; | |
| 559 | reg = <0x0 0xff0d0000 0x1000>; | |
| 560 | clock-names = "pclk", "hclk", "tx_clk"; | |
| 561 | #address-cells = <1>; | |
| 562 | #size-cells = <0>; | |
| 7f1d7d97 | 563 | #stream-id-cells = <1>; |
| 8f4e3972 | 564 | power-domains = <&pd_eth2>; |
| 44303dfa MS |
565 | }; |
| 566 | ||
| 567 | gem3: ethernet@ff0e0000 { | |
| da2ad784 | 568 | compatible = "cdns,zynqmp-gem"; |
| 44303dfa MS |
569 | status = "disabled"; |
| 570 | interrupt-parent = <&gic>; | |
| 571 | interrupts = <0 63 4>, <0 63 4>; | |
| 572 | reg = <0x0 0xff0e0000 0x1000>; | |
| 573 | clock-names = "pclk", "hclk", "tx_clk"; | |
| 574 | #address-cells = <1>; | |
| 575 | #size-cells = <0>; | |
| 7f1d7d97 | 576 | #stream-id-cells = <1>; |
| 8f4e3972 | 577 | power-domains = <&pd_eth3>; |
| 44303dfa MS |
578 | }; |
| 579 | ||
| 580 | gpio: gpio@ff0a0000 { | |
| 581 | compatible = "xlnx,zynqmp-gpio-1.0"; | |
| 582 | status = "disabled"; | |
| 583 | #gpio-cells = <0x2>; | |
| 7c38ca36 MS |
584 | #interrupt-cells = <2>; |
| 585 | interrupt-controller; | |
| 44303dfa MS |
586 | interrupt-parent = <&gic>; |
| 587 | interrupts = <0 16 4>; | |
| 588 | reg = <0x0 0xff0a0000 0x1000>; | |
| 8f4e3972 | 589 | power-domains = <&pd_gpio>; |
| 44303dfa MS |
590 | }; |
| 591 | ||
| 592 | i2c0: i2c@ff020000 { | |
| 593 | compatible = "cdns,i2c-r1p10"; | |
| 594 | status = "disabled"; | |
| 595 | interrupt-parent = <&gic>; | |
| 596 | interrupts = <0 17 4>; | |
| 597 | reg = <0x0 0xff020000 0x1000>; | |
| 598 | #address-cells = <1>; | |
| 599 | #size-cells = <0>; | |
| 8f4e3972 | 600 | power-domains = <&pd_i2c0>; |
| 44303dfa MS |
601 | }; |
| 602 | ||
| 603 | i2c1: i2c@ff030000 { | |
| 604 | compatible = "cdns,i2c-r1p10"; | |
| 605 | status = "disabled"; | |
| 606 | interrupt-parent = <&gic>; | |
| 607 | interrupts = <0 18 4>; | |
| 608 | reg = <0x0 0xff030000 0x1000>; | |
| 609 | #address-cells = <1>; | |
| 610 | #size-cells = <0>; | |
| 8f4e3972 | 611 | power-domains = <&pd_i2c1>; |
| 44303dfa MS |
612 | }; |
| 613 | ||
| 614 | pcie: pcie@fd0e0000 { | |
| 615 | compatible = "xlnx,nwl-pcie-2.11"; | |
| 616 | status = "disabled"; | |
| 617 | #address-cells = <3>; | |
| 618 | #size-cells = <2>; | |
| 619 | #interrupt-cells = <1>; | |
| 620 | device_type = "pci"; | |
| 621 | interrupt-parent = <&gic>; | |
| 91a8b0ee MS |
622 | interrupts = <0 118 4>, |
| 623 | <0 116 4>, | |
| 624 | <0 115 4>, /* MSI_1 [63...32] */ | |
| 625 | <0 114 4>; /* MSI_0 [31...0] */ | |
| 44303dfa MS |
626 | interrupt-names = "misc", "intx", "msi_1", "msi_0"; |
| 627 | reg = <0x0 0xfd0e0000 0x1000>, | |
| 628 | <0x0 0xfd480000 0x1000>, | |
| 629 | <0x0 0xe0000000 0x1000000>; | |
| 630 | reg-names = "breg", "pcireg", "cfg"; | |
| 631 | ranges = <0x02000000 0x00000000 0xe1000000 0x00000000 0xe1000000 0 0x0f000000>; | |
| 33aec517 BKG |
632 | interrupt-map-mask = <0x0 0x0 0x0 0x7>; |
| 633 | interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, | |
| 634 | <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, | |
| 635 | <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, | |
| 636 | <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; | |
| 637 | pcie_intc: legacy-interrupt-controller { | |
| 638 | interrupt-controller; | |
| 639 | #address-cells = <0>; | |
| 640 | #interrupt-cells = <1>; | |
| 641 | }; | |
| 44303dfa MS |
642 | }; |
| 643 | ||
| 644 | qspi: spi@ff0f0000 { | |
| 645 | compatible = "xlnx,zynqmp-qspi-1.0"; | |
| 646 | status = "disabled"; | |
| 647 | clock-names = "ref_clk", "pclk"; | |
| 648 | interrupts = <0 15 4>; | |
| 649 | interrupt-parent = <&gic>; | |
| 650 | num-cs = <1>; | |
| c588d154 MS |
651 | reg = <0x0 0xff0f0000 0x1000>, |
| 652 | <0x0 0xc0000000 0x8000000>; | |
| 44303dfa MS |
653 | #address-cells = <1>; |
| 654 | #size-cells = <0>; | |
| 8f4e3972 | 655 | power-domains = <&pd_qspi>; |
| 44303dfa MS |
656 | }; |
| 657 | ||
| 658 | rtc: rtc@ffa60000 { | |
| 659 | compatible = "xlnx,zynqmp-rtc"; | |
| 660 | status = "disabled"; | |
| 661 | reg = <0x0 0xffa60000 0x100>; | |
| 662 | interrupt-parent = <&gic>; | |
| 663 | interrupts = <0 26 4>, <0 27 4>; | |
| 664 | interrupt-names = "alarm", "sec"; | |
| 665 | }; | |
| 666 | ||
| 667 | sata: ahci@fd0c0000 { | |
| 668 | compatible = "ceva,ahci-1v84"; | |
| 669 | status = "disabled"; | |
| 670 | reg = <0x0 0xfd0c0000 0x2000>; | |
| 671 | interrupt-parent = <&gic>; | |
| 672 | interrupts = <0 133 4>; | |
| 8f4e3972 | 673 | power-domains = <&pd_sata>; |
| 44303dfa MS |
674 | }; |
| 675 | ||
| 676 | sdhci0: sdhci@ff160000 { | |
| 677 | compatible = "arasan,sdhci-8.9a"; | |
| 678 | status = "disabled"; | |
| 679 | interrupt-parent = <&gic>; | |
| 680 | interrupts = <0 48 4>; | |
| 681 | reg = <0x0 0xff160000 0x1000>; | |
| 682 | clock-names = "clk_xin", "clk_ahb"; | |
| bd750e7a | 683 | broken-tuning; |
| 8f4e3972 | 684 | power-domains = <&pd_sd0>; |
| 44303dfa MS |
685 | }; |
| 686 | ||
| 687 | sdhci1: sdhci@ff170000 { | |
| 688 | compatible = "arasan,sdhci-8.9a"; | |
| 689 | status = "disabled"; | |
| 690 | interrupt-parent = <&gic>; | |
| 691 | interrupts = <0 49 4>; | |
| 692 | reg = <0x0 0xff170000 0x1000>; | |
| 693 | clock-names = "clk_xin", "clk_ahb"; | |
| bd750e7a | 694 | broken-tuning; |
| 8f4e3972 | 695 | power-domains = <&pd_sd1>; |
| 44303dfa MS |
696 | }; |
| 697 | ||
| 698 | smmu: smmu@fd800000 { | |
| 699 | compatible = "arm,mmu-500"; | |
| 700 | reg = <0x0 0xfd800000 0x20000>; | |
| 701 | #global-interrupts = <1>; | |
| 702 | interrupt-parent = <&gic>; | |
| 88a85aac EI |
703 | interrupts = <0 155 4>, |
| 704 | <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, | |
| 705 | <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, | |
| 706 | <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, | |
| 707 | <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; | |
| 7f1d7d97 EI |
708 | mmu-masters = < &gem0 0x874 |
| 709 | &gem1 0x875 | |
| 710 | &gem2 0x876 | |
| 711 | &gem3 0x877 >; | |
| 44303dfa MS |
712 | }; |
| 713 | ||
| 714 | spi0: spi@ff040000 { | |
| 715 | compatible = "cdns,spi-r1p6"; | |
| 716 | status = "disabled"; | |
| 717 | interrupt-parent = <&gic>; | |
| 718 | interrupts = <0 19 4>; | |
| 719 | reg = <0x0 0xff040000 0x1000>; | |
| 720 | clock-names = "ref_clk", "pclk"; | |
| 721 | #address-cells = <1>; | |
| 722 | #size-cells = <0>; | |
| 8f4e3972 | 723 | power-domains = <&pd_spi0>; |
| 44303dfa MS |
724 | }; |
| 725 | ||
| 726 | spi1: spi@ff050000 { | |
| 727 | compatible = "cdns,spi-r1p6"; | |
| 728 | status = "disabled"; | |
| 729 | interrupt-parent = <&gic>; | |
| 730 | interrupts = <0 20 4>; | |
| 731 | reg = <0x0 0xff050000 0x1000>; | |
| 732 | clock-names = "ref_clk", "pclk"; | |
| 733 | #address-cells = <1>; | |
| 734 | #size-cells = <0>; | |
| 8f4e3972 | 735 | power-domains = <&pd_spi1>; |
| 44303dfa MS |
736 | }; |
| 737 | ||
| 738 | ttc0: timer@ff110000 { | |
| 739 | compatible = "cdns,ttc"; | |
| 740 | status = "disabled"; | |
| 741 | interrupt-parent = <&gic>; | |
| 742 | interrupts = <0 36 4>, <0 37 4>, <0 38 4>; | |
| 743 | reg = <0x0 0xff110000 0x1000>; | |
| 744 | timer-width = <32>; | |
| 8f4e3972 | 745 | power-domains = <&pd_ttc0>; |
| 44303dfa MS |
746 | }; |
| 747 | ||
| 748 | ttc1: timer@ff120000 { | |
| 749 | compatible = "cdns,ttc"; | |
| 750 | status = "disabled"; | |
| 751 | interrupt-parent = <&gic>; | |
| 752 | interrupts = <0 39 4>, <0 40 4>, <0 41 4>; | |
| 753 | reg = <0x0 0xff120000 0x1000>; | |
| 754 | timer-width = <32>; | |
| 8f4e3972 | 755 | power-domains = <&pd_ttc1>; |
| 44303dfa MS |
756 | }; |
| 757 | ||
| 758 | ttc2: timer@ff130000 { | |
| 759 | compatible = "cdns,ttc"; | |
| 760 | status = "disabled"; | |
| 761 | interrupt-parent = <&gic>; | |
| 762 | interrupts = <0 42 4>, <0 43 4>, <0 44 4>; | |
| 763 | reg = <0x0 0xff130000 0x1000>; | |
| 764 | timer-width = <32>; | |
| 8f4e3972 | 765 | power-domains = <&pd_ttc2>; |
| 44303dfa MS |
766 | }; |
| 767 | ||
| 768 | ttc3: timer@ff140000 { | |
| 769 | compatible = "cdns,ttc"; | |
| 770 | status = "disabled"; | |
| 771 | interrupt-parent = <&gic>; | |
| 772 | interrupts = <0 45 4>, <0 46 4>, <0 47 4>; | |
| 773 | reg = <0x0 0xff140000 0x1000>; | |
| 774 | timer-width = <32>; | |
| 8f4e3972 | 775 | power-domains = <&pd_ttc3>; |
| 44303dfa MS |
776 | }; |
| 777 | ||
| 778 | uart0: serial@ff000000 { | |
| ca2f5878 | 779 | compatible = "cdns,uart-r1p12", "xlnx,xuartps"; |
| 44303dfa MS |
780 | status = "disabled"; |
| 781 | interrupt-parent = <&gic>; | |
| 782 | interrupts = <0 21 4>; | |
| 783 | reg = <0x0 0xff000000 0x1000>; | |
| 784 | clock-names = "uart_clk", "pclk"; | |
| 8f4e3972 | 785 | power-domains = <&pd_uart0>; |
| 44303dfa MS |
786 | }; |
| 787 | ||
| 788 | uart1: serial@ff010000 { | |
| ca2f5878 | 789 | compatible = "cdns,uart-r1p12", "xlnx,xuartps"; |
| 44303dfa MS |
790 | status = "disabled"; |
| 791 | interrupt-parent = <&gic>; | |
| 792 | interrupts = <0 22 4>; | |
| 793 | reg = <0x0 0xff010000 0x1000>; | |
| 794 | clock-names = "uart_clk", "pclk"; | |
| 8f4e3972 | 795 | power-domains = <&pd_uart1>; |
| 44303dfa MS |
796 | }; |
| 797 | ||
| 798 | usb0: usb@fe200000 { | |
| a84de48e MS |
799 | #address-cells = <2>; |
| 800 | #size-cells = <1>; | |
| 44303dfa | 801 | status = "disabled"; |
| a84de48e MS |
802 | compatible = "xlnx,zynqmp-dwc3"; |
| 803 | clock-names = "bus_clk", "ref_clk"; | |
| 804 | clocks = <&clk125>, <&clk125>; | |
| 8f4e3972 | 805 | power-domains = <&pd_usb0>; |
| a84de48e MS |
806 | ranges; |
| 807 | ||
| 808 | dwc3_0: dwc3@fe200000 { | |
| 809 | compatible = "snps,dwc3"; | |
| 810 | status = "disabled"; | |
| 811 | reg = <0x0 0xfe200000 0x40000>; | |
| 812 | interrupt-parent = <&gic>; | |
| 813 | interrupts = <0 65 4>; | |
| 814 | /* snps,quirk-frame-length-adjustment = <0x20>; */ | |
| 815 | snps,refclk_fladj; | |
| 816 | }; | |
| 44303dfa MS |
817 | }; |
| 818 | ||
| 819 | usb1: usb@fe300000 { | |
| a84de48e MS |
820 | #address-cells = <2>; |
| 821 | #size-cells = <1>; | |
| 44303dfa | 822 | status = "disabled"; |
| a84de48e MS |
823 | compatible = "xlnx,zynqmp-dwc3"; |
| 824 | clock-names = "bus_clk", "ref_clk"; | |
| 825 | clocks = <&clk125>, <&clk125>; | |
| 8f4e3972 | 826 | power-domains = <&pd_usb1>; |
| a84de48e MS |
827 | ranges; |
| 828 | ||
| 829 | dwc3_1: dwc3@fe300000 { | |
| 830 | compatible = "snps,dwc3"; | |
| 831 | status = "disabled"; | |
| 832 | reg = <0x0 0xfe300000 0x40000>; | |
| 833 | interrupt-parent = <&gic>; | |
| 834 | interrupts = <0 70 4>; | |
| 835 | /* snps,quirk-frame-length-adjustment = <0x20>; */ | |
| 836 | snps,refclk_fladj; | |
| 837 | }; | |
| 44303dfa MS |
838 | }; |
| 839 | ||
| 840 | watchdog0: watchdog@fd4d0000 { | |
| 841 | compatible = "cdns,wdt-r1p2"; | |
| 842 | status = "disabled"; | |
| 843 | interrupt-parent = <&gic>; | |
| d3fd433f | 844 | interrupts = <0 113 1>; |
| 44303dfa MS |
845 | reg = <0x0 0xfd4d0000 0x1000>; |
| 846 | timeout-sec = <10>; | |
| 847 | }; | |
| 848 | ||
| 849 | xilinx_drm: xilinx_drm { | |
| 850 | compatible = "xlnx,drm"; | |
| 851 | status = "disabled"; | |
| 852 | xlnx,encoder-slave = <&xlnx_dp>; | |
| 853 | xlnx,connector-type = "DisplayPort"; | |
| 854 | xlnx,dp-sub = <&xlnx_dp_sub>; | |
| 855 | planes { | |
| 856 | xlnx,pixel-format = "rgb565"; | |
| 857 | plane0 { | |
| 858 | dmas = <&xlnx_dpdma 3>; | |
| 859 | dma-names = "dma"; | |
| 860 | }; | |
| 861 | plane1 { | |
| 862 | dmas = <&xlnx_dpdma 0>; | |
| 863 | dma-names = "dma"; | |
| 864 | }; | |
| 865 | }; | |
| 866 | }; | |
| 867 | ||
| 695d75a1 | 868 | xlnx_dp: dp@fd4a0000 { |
| 44303dfa MS |
869 | compatible = "xlnx,v-dp"; |
| 870 | status = "disabled"; | |
| 786db82b MS |
871 | reg = <0x0 0xfd4a0000 0x1000>, |
| 872 | <0x0 0xfd400000 0x20000>; | |
| 44303dfa MS |
873 | interrupts = <0 119 4>; |
| 874 | interrupt-parent = <&gic>; | |
| 875 | clock-names = "aclk", "aud_clk"; | |
| 876 | xlnx,dp-version = "v1.2"; | |
| 877 | xlnx,max-lanes = <2>; | |
| 878 | xlnx,max-link-rate = <540000>; | |
| 879 | xlnx,max-bpc = <16>; | |
| 880 | xlnx,enable-ycrcb; | |
| 881 | xlnx,colormetry = "rgb"; | |
| 882 | xlnx,bpc = <8>; | |
| 883 | xlnx,audio-chan = <2>; | |
| 884 | xlnx,dp-sub = <&xlnx_dp_sub>; | |
| 939cfeaf | 885 | xlnx,max-pclock-frequency = <300000>; |
| 44303dfa MS |
886 | }; |
| 887 | ||
| 888 | xlnx_dp_snd_card: dp_snd_card { | |
| 889 | compatible = "xlnx,dp-snd-card"; | |
| 890 | status = "disabled"; | |
| 891 | xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>; | |
| 892 | xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>; | |
| 893 | }; | |
| 894 | ||
| 895 | xlnx_dp_snd_codec0: dp_snd_codec0 { | |
| 896 | compatible = "xlnx,dp-snd-codec"; | |
| 897 | status = "disabled"; | |
| 898 | clock-names = "aud_clk"; | |
| 899 | }; | |
| 900 | ||
| 901 | xlnx_dp_snd_pcm0: dp_snd_pcm0 { | |
| 902 | compatible = "xlnx,dp-snd-pcm"; | |
| 903 | status = "disabled"; | |
| 904 | dmas = <&xlnx_dpdma 4>; | |
| 905 | dma-names = "tx"; | |
| 906 | }; | |
| 907 | ||
| 908 | xlnx_dp_snd_pcm1: dp_snd_pcm1 { | |
| 909 | compatible = "xlnx,dp-snd-pcm"; | |
| 910 | status = "disabled"; | |
| 911 | dmas = <&xlnx_dpdma 5>; | |
| 912 | dma-names = "tx"; | |
| 913 | }; | |
| 914 | ||
| 695d75a1 | 915 | xlnx_dp_sub: dp_sub@fd4aa000 { |
| 44303dfa MS |
916 | compatible = "xlnx,dp-sub"; |
| 917 | status = "disabled"; | |
| c588d154 MS |
918 | reg = <0x0 0xfd4aa000 0x1000>, |
| 919 | <0x0 0xfd4ab000 0x1000>, | |
| 920 | <0x0 0xfd4ac000 0x1000>; | |
| 44303dfa MS |
921 | reg-names = "blend", "av_buf", "aud"; |
| 922 | xlnx,output-fmt = "rgb"; | |
| 939cfeaf HK |
923 | xlnx,vid-fmt = "yuyv"; |
| 924 | xlnx,gfx-fmt = "rgb565"; | |
| 44303dfa MS |
925 | }; |
| 926 | ||
| 927 | xlnx_dpdma: dma@fd4c0000 { | |
| 928 | compatible = "xlnx,dpdma"; | |
| 929 | status = "disabled"; | |
| 930 | reg = <0x0 0xfd4c0000 0x1000>; | |
| 931 | interrupts = <0 122 4>; | |
| 932 | interrupt-parent = <&gic>; | |
| 933 | clock-names = "axi_clk"; | |
| 934 | dma-channels = <6>; | |
| 935 | #dma-cells = <1>; | |
| 4e31d27b | 936 | dma-video0channel@fd4c0000 { |
| 44303dfa MS |
937 | compatible = "xlnx,video0"; |
| 938 | }; | |
| 4e31d27b | 939 | dma-video1channel@fd4c0000 { |
| 44303dfa MS |
940 | compatible = "xlnx,video1"; |
| 941 | }; | |
| 4e31d27b | 942 | dma-video2channel@fd4c0000 { |
| 44303dfa MS |
943 | compatible = "xlnx,video2"; |
| 944 | }; | |
| 4e31d27b | 945 | dma-graphicschannel@fd4c0000 { |
| 44303dfa MS |
946 | compatible = "xlnx,graphics"; |
| 947 | }; | |
| 4e31d27b | 948 | dma-audio0channel@fd4c0000 { |
| 44303dfa MS |
949 | compatible = "xlnx,audio0"; |
| 950 | }; | |
| 4e31d27b | 951 | dma-audio1channel@fd4c0000 { |
| 44303dfa MS |
952 | compatible = "xlnx,audio1"; |
| 953 | }; | |
| 954 | }; | |
| 955 | }; | |
| 956 | }; |