]>
Commit | Line | Data |
---|---|---|
44303dfa MS |
1 | /* |
2 | * dts file for Xilinx ZynqMP | |
3 | * | |
4 | * (C) Copyright 2014 - 2015, Xilinx, Inc. | |
5 | * | |
6 | * Michal Simek <michal.simek@xilinx.com> | |
7 | * | |
8 | * SPDX-License-Identifier: GPL-2.0+ | |
9 | */ | |
91d11536 | 10 | |
44303dfa MS |
11 | / { |
12 | compatible = "xlnx,zynqmp"; | |
13 | #address-cells = <2>; | |
85d1142e | 14 | #size-cells = <2>; |
44303dfa MS |
15 | |
16 | cpus { | |
17 | #address-cells = <1>; | |
18 | #size-cells = <0>; | |
19 | ||
20 | cpu@0 { | |
21 | compatible = "arm,cortex-a53", "arm,armv8"; | |
22 | device_type = "cpu"; | |
23 | enable-method = "psci"; | |
24 | reg = <0x0>; | |
2e15b071 | 25 | cpu-idle-states = <&CPU_SLEEP_0>; |
44303dfa MS |
26 | }; |
27 | ||
28 | cpu@1 { | |
29 | compatible = "arm,cortex-a53", "arm,armv8"; | |
30 | device_type = "cpu"; | |
31 | enable-method = "psci"; | |
32 | reg = <0x1>; | |
2e15b071 | 33 | cpu-idle-states = <&CPU_SLEEP_0>; |
44303dfa MS |
34 | }; |
35 | ||
36 | cpu@2 { | |
37 | compatible = "arm,cortex-a53", "arm,armv8"; | |
38 | device_type = "cpu"; | |
39 | enable-method = "psci"; | |
40 | reg = <0x2>; | |
2e15b071 | 41 | cpu-idle-states = <&CPU_SLEEP_0>; |
44303dfa MS |
42 | }; |
43 | ||
44 | cpu@3 { | |
45 | compatible = "arm,cortex-a53", "arm,armv8"; | |
46 | device_type = "cpu"; | |
47 | enable-method = "psci"; | |
48 | reg = <0x3>; | |
2e15b071 SK |
49 | cpu-idle-states = <&CPU_SLEEP_0>; |
50 | }; | |
51 | ||
52 | idle-states { | |
53 | entry-mehod = "arm,psci"; | |
54 | ||
55 | CPU_SLEEP_0: cpu-sleep-0 { | |
56 | compatible = "arm,idle-state"; | |
57 | arm,psci-suspend-param = <0x40000000>; | |
58 | local-timer-stop; | |
59 | entry-latency-us = <300>; | |
60 | exit-latency-us = <600>; | |
61 | min-residency-us = <800000>; | |
62 | }; | |
44303dfa MS |
63 | }; |
64 | }; | |
65 | ||
69d09dd7 MS |
66 | dcc: dcc { |
67 | compatible = "arm,dcc"; | |
68 | status = "disabled"; | |
69 | u-boot,dm-pre-reloc; | |
70 | }; | |
71 | ||
8f4e3972 SB |
72 | power-domains { |
73 | compatible = "xlnx,zynqmp-genpd"; | |
74 | ||
75 | pd_usb0: pd-usb0 { | |
76 | #power-domain-cells = <0x0>; | |
77 | pd-id = <0x16>; | |
78 | }; | |
79 | ||
80 | pd_usb1: pd-usb1 { | |
81 | #power-domain-cells = <0x0>; | |
82 | pd-id = <0x17>; | |
83 | }; | |
84 | ||
85 | pd_sata: pd-sata { | |
86 | #power-domain-cells = <0x0>; | |
87 | pd-id = <0x1c>; | |
88 | }; | |
89 | ||
90 | pd_spi0: pd-spi0 { | |
91 | #power-domain-cells = <0x0>; | |
92 | pd-id = <0x23>; | |
93 | }; | |
94 | ||
95 | pd_spi1: pd-spi1 { | |
96 | #power-domain-cells = <0x0>; | |
97 | pd-id = <0x24>; | |
98 | }; | |
99 | ||
100 | pd_uart0: pd-uart0 { | |
101 | #power-domain-cells = <0x0>; | |
102 | pd-id = <0x21>; | |
103 | }; | |
104 | ||
105 | pd_uart1: pd-uart1 { | |
106 | #power-domain-cells = <0x0>; | |
107 | pd-id = <0x22>; | |
108 | }; | |
109 | ||
110 | pd_eth0: pd-eth0 { | |
111 | #power-domain-cells = <0x0>; | |
112 | pd-id = <0x1d>; | |
113 | }; | |
114 | ||
115 | pd_eth1: pd-eth1 { | |
116 | #power-domain-cells = <0x0>; | |
117 | pd-id = <0x1e>; | |
118 | }; | |
119 | ||
120 | pd_eth2: pd-eth2 { | |
121 | #power-domain-cells = <0x0>; | |
122 | pd-id = <0x1f>; | |
123 | }; | |
124 | ||
125 | pd_eth3: pd-eth3 { | |
126 | #power-domain-cells = <0x0>; | |
127 | pd-id = <0x20>; | |
128 | }; | |
129 | ||
130 | pd_i2c0: pd-i2c0 { | |
131 | #power-domain-cells = <0x0>; | |
132 | pd-id = <0x25>; | |
133 | }; | |
134 | ||
135 | pd_i2c1: pd-i2c1 { | |
136 | #power-domain-cells = <0x0>; | |
137 | pd-id = <0x26>; | |
138 | }; | |
139 | ||
140 | pd_dp: pd-dp { | |
141 | /* fixme: what to attach to */ | |
142 | #power-domain-cells = <0x0>; | |
143 | pd-id = <0x29>; | |
144 | }; | |
145 | ||
146 | pd_gdma: pd-gdma { | |
147 | #power-domain-cells = <0x0>; | |
148 | pd-id = <0x2a>; | |
149 | }; | |
150 | ||
151 | pd_adma: pd-adma { | |
152 | #power-domain-cells = <0x0>; | |
153 | pd-id = <0x2b>; | |
154 | }; | |
155 | ||
156 | pd_ttc0: pd-ttc0 { | |
157 | #power-domain-cells = <0x0>; | |
158 | pd-id = <0x18>; | |
159 | }; | |
160 | ||
161 | pd_ttc1: pd-ttc1 { | |
162 | #power-domain-cells = <0x0>; | |
163 | pd-id = <0x19>; | |
164 | }; | |
165 | ||
166 | pd_ttc2: pd-ttc2 { | |
167 | #power-domain-cells = <0x0>; | |
168 | pd-id = <0x1a>; | |
169 | }; | |
170 | ||
171 | pd_ttc3: pd-ttc3 { | |
172 | #power-domain-cells = <0x0>; | |
173 | pd-id = <0x1b>; | |
174 | }; | |
175 | ||
176 | pd_sd0: pd-sd0 { | |
177 | #power-domain-cells = <0x0>; | |
178 | pd-id = <0x27>; | |
179 | }; | |
180 | ||
181 | pd_sd1: pd-sd1 { | |
182 | #power-domain-cells = <0x0>; | |
183 | pd-id = <0x28>; | |
184 | }; | |
185 | ||
186 | pd_nand: pd-nand { | |
187 | #power-domain-cells = <0x0>; | |
188 | pd-id = <0x2c>; | |
189 | }; | |
190 | ||
191 | pd_qspi: pd-qspi { | |
192 | #power-domain-cells = <0x0>; | |
193 | pd-id = <0x2d>; | |
194 | }; | |
195 | ||
196 | pd_gpio: pd-gpio { | |
197 | #power-domain-cells = <0x0>; | |
198 | pd-id = <0x2e>; | |
199 | }; | |
200 | ||
201 | pd_can0: pd-can0 { | |
202 | #power-domain-cells = <0x0>; | |
203 | pd-id = <0x2f>; | |
204 | }; | |
205 | ||
206 | pd_can1: pd-can1 { | |
207 | #power-domain-cells = <0x0>; | |
208 | pd-id = <0x30>; | |
209 | }; | |
2af3932f FD |
210 | |
211 | pd_pcie: pd-pcie { | |
212 | #power-domain-cells = <0x0>; | |
213 | pd-id = <0x3b>; | |
214 | }; | |
215 | ||
216 | pd_gpu: pd-gpu { | |
217 | #power-domain-cells = <0x0>; | |
a4d7d560 | 218 | pd-id = <0x3a 0x14 0x15>; |
2af3932f | 219 | }; |
8f4e3972 SB |
220 | }; |
221 | ||
44303dfa MS |
222 | pmu { |
223 | compatible = "arm,armv8-pmuv3"; | |
14cd9eab | 224 | interrupt-parent = <&gic>; |
44303dfa MS |
225 | interrupts = <0 143 4>, |
226 | <0 144 4>, | |
227 | <0 145 4>, | |
228 | <0 146 4>; | |
229 | }; | |
230 | ||
231 | psci { | |
232 | compatible = "arm,psci-0.2"; | |
233 | method = "smc"; | |
234 | }; | |
235 | ||
236 | firmware { | |
237 | compatible = "xlnx,zynqmp-pm"; | |
238 | method = "smc"; | |
239 | }; | |
240 | ||
241 | timer { | |
242 | compatible = "arm,armv8-timer"; | |
243 | interrupt-parent = <&gic>; | |
244 | interrupts = <1 13 0xf01>, | |
245 | <1 14 0xf01>, | |
246 | <1 11 0xf01>, | |
247 | <1 10 0xf01>; | |
248 | }; | |
249 | ||
aaf232f3 NSR |
250 | edac { |
251 | compatible = "arm,cortex-a53-edac"; | |
252 | }; | |
253 | ||
d64e43f1 NM |
254 | pcap { |
255 | compatible = "xlnx,zynqmp-pcap-fpga"; | |
256 | }; | |
257 | ||
c926e6fb | 258 | amba_apu: amba_apu@0 { |
44303dfa MS |
259 | compatible = "simple-bus"; |
260 | #address-cells = <2>; | |
261 | #size-cells = <1>; | |
85d1142e | 262 | ranges = <0 0 0 0 0xffffffff>; |
44303dfa MS |
263 | |
264 | gic: interrupt-controller@f9010000 { | |
265 | compatible = "arm,gic-400", "arm,cortex-a15-gic"; | |
266 | #interrupt-cells = <3>; | |
267 | reg = <0x0 0xf9010000 0x10000>, | |
0a8c4f67 | 268 | <0x0 0xf9020000 0x20000>, |
44303dfa | 269 | <0x0 0xf9040000 0x20000>, |
0a8c4f67 | 270 | <0x0 0xf9060000 0x20000>; |
44303dfa MS |
271 | interrupt-controller; |
272 | interrupt-parent = <&gic>; | |
273 | interrupts = <1 9 0xf04>; | |
274 | }; | |
275 | }; | |
276 | ||
b976fd63 | 277 | amba: amba { |
44303dfa | 278 | compatible = "simple-bus"; |
c9811e14 | 279 | u-boot,dm-pre-reloc; |
44303dfa | 280 | #address-cells = <2>; |
b976fd63 MS |
281 | #size-cells = <2>; |
282 | ranges; | |
44303dfa MS |
283 | |
284 | can0: can@ff060000 { | |
285 | compatible = "xlnx,zynq-can-1.0"; | |
286 | status = "disabled"; | |
287 | clock-names = "can_clk", "pclk"; | |
b976fd63 | 288 | reg = <0x0 0xff060000 0x0 0x1000>; |
44303dfa MS |
289 | interrupts = <0 23 4>; |
290 | interrupt-parent = <&gic>; | |
291 | tx-fifo-depth = <0x40>; | |
292 | rx-fifo-depth = <0x40>; | |
8f4e3972 | 293 | power-domains = <&pd_can0>; |
44303dfa MS |
294 | }; |
295 | ||
296 | can1: can@ff070000 { | |
297 | compatible = "xlnx,zynq-can-1.0"; | |
298 | status = "disabled"; | |
299 | clock-names = "can_clk", "pclk"; | |
b976fd63 | 300 | reg = <0x0 0xff070000 0x0 0x1000>; |
44303dfa MS |
301 | interrupts = <0 24 4>; |
302 | interrupt-parent = <&gic>; | |
303 | tx-fifo-depth = <0x40>; | |
304 | rx-fifo-depth = <0x40>; | |
8f4e3972 | 305 | power-domains = <&pd_can1>; |
44303dfa MS |
306 | }; |
307 | ||
ff50d21b MS |
308 | cci: cci@fd6e0000 { |
309 | compatible = "arm,cci-400"; | |
b976fd63 | 310 | reg = <0x0 0xfd6e0000 0x0 0x9000>; |
ff50d21b MS |
311 | ranges = <0x0 0x0 0xfd6e0000 0x10000>; |
312 | #address-cells = <1>; | |
313 | #size-cells = <1>; | |
314 | ||
315 | pmu@9000 { | |
316 | compatible = "arm,cci-400-pmu,r1"; | |
317 | reg = <0x9000 0x5000>; | |
318 | interrupt-parent = <&gic>; | |
319 | interrupts = <0 123 4>, | |
320 | <0 123 4>, | |
321 | <0 123 4>, | |
322 | <0 123 4>, | |
323 | <0 123 4>; | |
324 | }; | |
325 | }; | |
326 | ||
44303dfa MS |
327 | /* GDMA */ |
328 | fpd_dma_chan1: dma@fd500000 { | |
329 | status = "disabled"; | |
330 | compatible = "xlnx,zynqmp-dma-1.0"; | |
b976fd63 | 331 | reg = <0x0 0xfd500000 0x0 0x1000>; |
44303dfa MS |
332 | interrupt-parent = <&gic>; |
333 | interrupts = <0 124 4>; | |
b34d11de | 334 | clock-names = "clk_main", "clk_apb"; |
44303dfa | 335 | xlnx,bus-width = <128>; |
ba6ad317 MS |
336 | #stream-id-cells = <1>; |
337 | iommus = <&smmu 0x14e8>; | |
8f4e3972 | 338 | power-domains = <&pd_gdma>; |
44303dfa MS |
339 | }; |
340 | ||
341 | fpd_dma_chan2: dma@fd510000 { | |
342 | status = "disabled"; | |
343 | compatible = "xlnx,zynqmp-dma-1.0"; | |
b976fd63 | 344 | reg = <0x0 0xfd510000 0x0 0x1000>; |
44303dfa MS |
345 | interrupt-parent = <&gic>; |
346 | interrupts = <0 125 4>; | |
b34d11de | 347 | clock-names = "clk_main", "clk_apb"; |
44303dfa | 348 | xlnx,bus-width = <128>; |
ba6ad317 MS |
349 | #stream-id-cells = <1>; |
350 | iommus = <&smmu 0x14e9>; | |
8f4e3972 | 351 | power-domains = <&pd_gdma>; |
44303dfa MS |
352 | }; |
353 | ||
354 | fpd_dma_chan3: dma@fd520000 { | |
355 | status = "disabled"; | |
356 | compatible = "xlnx,zynqmp-dma-1.0"; | |
b976fd63 | 357 | reg = <0x0 0xfd520000 0x0 0x1000>; |
44303dfa MS |
358 | interrupt-parent = <&gic>; |
359 | interrupts = <0 126 4>; | |
b34d11de | 360 | clock-names = "clk_main", "clk_apb"; |
44303dfa | 361 | xlnx,bus-width = <128>; |
ba6ad317 MS |
362 | #stream-id-cells = <1>; |
363 | iommus = <&smmu 0x14ea>; | |
8f4e3972 | 364 | power-domains = <&pd_gdma>; |
44303dfa MS |
365 | }; |
366 | ||
367 | fpd_dma_chan4: dma@fd530000 { | |
368 | status = "disabled"; | |
369 | compatible = "xlnx,zynqmp-dma-1.0"; | |
b976fd63 | 370 | reg = <0x0 0xfd530000 0x0 0x1000>; |
44303dfa MS |
371 | interrupt-parent = <&gic>; |
372 | interrupts = <0 127 4>; | |
b34d11de | 373 | clock-names = "clk_main", "clk_apb"; |
44303dfa | 374 | xlnx,bus-width = <128>; |
ba6ad317 MS |
375 | #stream-id-cells = <1>; |
376 | iommus = <&smmu 0x14eb>; | |
8f4e3972 | 377 | power-domains = <&pd_gdma>; |
44303dfa MS |
378 | }; |
379 | ||
380 | fpd_dma_chan5: dma@fd540000 { | |
381 | status = "disabled"; | |
382 | compatible = "xlnx,zynqmp-dma-1.0"; | |
b976fd63 | 383 | reg = <0x0 0xfd540000 0x0 0x1000>; |
44303dfa MS |
384 | interrupt-parent = <&gic>; |
385 | interrupts = <0 128 4>; | |
b34d11de | 386 | clock-names = "clk_main", "clk_apb"; |
44303dfa | 387 | xlnx,bus-width = <128>; |
ba6ad317 MS |
388 | #stream-id-cells = <1>; |
389 | iommus = <&smmu 0x14ec>; | |
8f4e3972 | 390 | power-domains = <&pd_gdma>; |
44303dfa MS |
391 | }; |
392 | ||
393 | fpd_dma_chan6: dma@fd550000 { | |
394 | status = "disabled"; | |
395 | compatible = "xlnx,zynqmp-dma-1.0"; | |
b976fd63 | 396 | reg = <0x0 0xfd550000 0x0 0x1000>; |
44303dfa MS |
397 | interrupt-parent = <&gic>; |
398 | interrupts = <0 129 4>; | |
b34d11de | 399 | clock-names = "clk_main", "clk_apb"; |
44303dfa | 400 | xlnx,bus-width = <128>; |
ba6ad317 MS |
401 | #stream-id-cells = <1>; |
402 | iommus = <&smmu 0x14ed>; | |
8f4e3972 | 403 | power-domains = <&pd_gdma>; |
44303dfa MS |
404 | }; |
405 | ||
406 | fpd_dma_chan7: dma@fd560000 { | |
407 | status = "disabled"; | |
408 | compatible = "xlnx,zynqmp-dma-1.0"; | |
b976fd63 | 409 | reg = <0x0 0xfd560000 0x0 0x1000>; |
44303dfa MS |
410 | interrupt-parent = <&gic>; |
411 | interrupts = <0 130 4>; | |
b34d11de | 412 | clock-names = "clk_main", "clk_apb"; |
44303dfa | 413 | xlnx,bus-width = <128>; |
ba6ad317 MS |
414 | #stream-id-cells = <1>; |
415 | iommus = <&smmu 0x14ee>; | |
8f4e3972 | 416 | power-domains = <&pd_gdma>; |
44303dfa MS |
417 | }; |
418 | ||
419 | fpd_dma_chan8: dma@fd570000 { | |
420 | status = "disabled"; | |
421 | compatible = "xlnx,zynqmp-dma-1.0"; | |
b976fd63 | 422 | reg = <0x0 0xfd570000 0x0 0x1000>; |
44303dfa MS |
423 | interrupt-parent = <&gic>; |
424 | interrupts = <0 131 4>; | |
b34d11de | 425 | clock-names = "clk_main", "clk_apb"; |
44303dfa | 426 | xlnx,bus-width = <128>; |
ba6ad317 MS |
427 | #stream-id-cells = <1>; |
428 | iommus = <&smmu 0x14ef>; | |
8f4e3972 | 429 | power-domains = <&pd_gdma>; |
44303dfa MS |
430 | }; |
431 | ||
432 | gpu: gpu@fd4b0000 { | |
433 | status = "disabled"; | |
434 | compatible = "arm,mali-400", "arm,mali-utgard"; | |
b976fd63 | 435 | reg = <0x0 0xfd4b0000 0x0 0x30000>; |
44303dfa MS |
436 | interrupt-parent = <&gic>; |
437 | interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; | |
438 | interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; | |
2af3932f | 439 | power-domains = <&pd_gpu>; |
44303dfa MS |
440 | }; |
441 | ||
6af57737 KA |
442 | /* LPDDMA default allows only secured access. inorder to enable |
443 | * These dma channels, Users should ensure that these dma | |
444 | * Channels are allowed for non secure access. | |
445 | */ | |
44303dfa MS |
446 | lpd_dma_chan1: dma@ffa80000 { |
447 | status = "disabled"; | |
448 | compatible = "xlnx,zynqmp-dma-1.0"; | |
d33046aa | 449 | clock-names = "clk_main", "clk_apb"; |
b976fd63 | 450 | reg = <0x0 0xffa80000 0x0 0x1000>; |
44303dfa MS |
451 | interrupt-parent = <&gic>; |
452 | interrupts = <0 77 4>; | |
44303dfa | 453 | xlnx,bus-width = <64>; |
ba6ad317 MS |
454 | #stream-id-cells = <1>; |
455 | iommus = <&smmu 0x868>; | |
8f4e3972 | 456 | power-domains = <&pd_adma>; |
44303dfa MS |
457 | }; |
458 | ||
459 | lpd_dma_chan2: dma@ffa90000 { | |
460 | status = "disabled"; | |
461 | compatible = "xlnx,zynqmp-dma-1.0"; | |
d33046aa | 462 | clock-names = "clk_main", "clk_apb"; |
b976fd63 | 463 | reg = <0x0 0xffa90000 0x0 0x1000>; |
44303dfa MS |
464 | interrupt-parent = <&gic>; |
465 | interrupts = <0 78 4>; | |
44303dfa | 466 | xlnx,bus-width = <64>; |
ba6ad317 MS |
467 | #stream-id-cells = <1>; |
468 | iommus = <&smmu 0x869>; | |
8f4e3972 | 469 | power-domains = <&pd_adma>; |
44303dfa MS |
470 | }; |
471 | ||
472 | lpd_dma_chan3: dma@ffaa0000 { | |
473 | status = "disabled"; | |
474 | compatible = "xlnx,zynqmp-dma-1.0"; | |
d33046aa | 475 | clock-names = "clk_main", "clk_apb"; |
b976fd63 | 476 | reg = <0x0 0xffaa0000 0x0 0x1000>; |
44303dfa MS |
477 | interrupt-parent = <&gic>; |
478 | interrupts = <0 79 4>; | |
44303dfa | 479 | xlnx,bus-width = <64>; |
ba6ad317 MS |
480 | #stream-id-cells = <1>; |
481 | iommus = <&smmu 0x86a>; | |
8f4e3972 | 482 | power-domains = <&pd_adma>; |
44303dfa MS |
483 | }; |
484 | ||
485 | lpd_dma_chan4: dma@ffab0000 { | |
486 | status = "disabled"; | |
487 | compatible = "xlnx,zynqmp-dma-1.0"; | |
d33046aa | 488 | clock-names = "clk_main", "clk_apb"; |
b976fd63 | 489 | reg = <0x0 0xffab0000 0x0 0x1000>; |
44303dfa MS |
490 | interrupt-parent = <&gic>; |
491 | interrupts = <0 80 4>; | |
44303dfa | 492 | xlnx,bus-width = <64>; |
ba6ad317 MS |
493 | #stream-id-cells = <1>; |
494 | iommus = <&smmu 0x86b>; | |
8f4e3972 | 495 | power-domains = <&pd_adma>; |
44303dfa MS |
496 | }; |
497 | ||
498 | lpd_dma_chan5: dma@ffac0000 { | |
499 | status = "disabled"; | |
500 | compatible = "xlnx,zynqmp-dma-1.0"; | |
d33046aa | 501 | clock-names = "clk_main", "clk_apb"; |
b976fd63 | 502 | reg = <0x0 0xffac0000 0x0 0x1000>; |
44303dfa MS |
503 | interrupt-parent = <&gic>; |
504 | interrupts = <0 81 4>; | |
44303dfa | 505 | xlnx,bus-width = <64>; |
ba6ad317 MS |
506 | #stream-id-cells = <1>; |
507 | iommus = <&smmu 0x86c>; | |
8f4e3972 | 508 | power-domains = <&pd_adma>; |
44303dfa MS |
509 | }; |
510 | ||
511 | lpd_dma_chan6: dma@ffad0000 { | |
512 | status = "disabled"; | |
513 | compatible = "xlnx,zynqmp-dma-1.0"; | |
d33046aa | 514 | clock-names = "clk_main", "clk_apb"; |
b976fd63 | 515 | reg = <0x0 0xffad0000 0x0 0x1000>; |
44303dfa MS |
516 | interrupt-parent = <&gic>; |
517 | interrupts = <0 82 4>; | |
44303dfa | 518 | xlnx,bus-width = <64>; |
ba6ad317 MS |
519 | #stream-id-cells = <1>; |
520 | iommus = <&smmu 0x86d>; | |
8f4e3972 | 521 | power-domains = <&pd_adma>; |
44303dfa MS |
522 | }; |
523 | ||
524 | lpd_dma_chan7: dma@ffae0000 { | |
525 | status = "disabled"; | |
526 | compatible = "xlnx,zynqmp-dma-1.0"; | |
d33046aa | 527 | clock-names = "clk_main", "clk_apb"; |
b976fd63 | 528 | reg = <0x0 0xffae0000 0x0 0x1000>; |
44303dfa MS |
529 | interrupt-parent = <&gic>; |
530 | interrupts = <0 83 4>; | |
44303dfa | 531 | xlnx,bus-width = <64>; |
ba6ad317 MS |
532 | #stream-id-cells = <1>; |
533 | iommus = <&smmu 0x86e>; | |
8f4e3972 | 534 | power-domains = <&pd_adma>; |
44303dfa MS |
535 | }; |
536 | ||
537 | lpd_dma_chan8: dma@ffaf0000 { | |
538 | status = "disabled"; | |
539 | compatible = "xlnx,zynqmp-dma-1.0"; | |
d33046aa | 540 | clock-names = "clk_main", "clk_apb"; |
b976fd63 | 541 | reg = <0x0 0xffaf0000 0x0 0x1000>; |
44303dfa MS |
542 | interrupt-parent = <&gic>; |
543 | interrupts = <0 84 4>; | |
44303dfa | 544 | xlnx,bus-width = <64>; |
ba6ad317 MS |
545 | #stream-id-cells = <1>; |
546 | iommus = <&smmu 0x86f>; | |
8f4e3972 | 547 | power-domains = <&pd_adma>; |
44303dfa MS |
548 | }; |
549 | ||
90869009 NSR |
550 | mc: memory-controller@fd070000 { |
551 | compatible = "xlnx,zynqmp-ddrc-2.40a"; | |
b976fd63 | 552 | reg = <0x0 0xfd070000 0x0 0x30000>; |
90869009 NSR |
553 | interrupt-parent = <&gic>; |
554 | interrupts = <0 112 4>; | |
555 | }; | |
556 | ||
44303dfa MS |
557 | nand0: nand@ff100000 { |
558 | compatible = "arasan,nfc-v3p10"; | |
559 | status = "disabled"; | |
b976fd63 | 560 | reg = <0x0 0xff100000 0x0 0x1000>; |
44303dfa MS |
561 | clock-names = "clk_sys", "clk_flash"; |
562 | interrupt-parent = <&gic>; | |
563 | interrupts = <0 14 4>; | |
564 | #address-cells = <2>; | |
565 | #size-cells = <1>; | |
ba6ad317 MS |
566 | #stream-id-cells = <1>; |
567 | iommus = <&smmu 0x872>; | |
8f4e3972 | 568 | power-domains = <&pd_nand>; |
44303dfa MS |
569 | }; |
570 | ||
571 | gem0: ethernet@ff0b0000 { | |
da2ad784 | 572 | compatible = "cdns,zynqmp-gem"; |
44303dfa MS |
573 | status = "disabled"; |
574 | interrupt-parent = <&gic>; | |
575 | interrupts = <0 57 4>, <0 57 4>; | |
b976fd63 | 576 | reg = <0x0 0xff0b0000 0x0 0x1000>; |
44303dfa MS |
577 | clock-names = "pclk", "hclk", "tx_clk"; |
578 | #address-cells = <1>; | |
579 | #size-cells = <0>; | |
7f1d7d97 | 580 | #stream-id-cells = <1>; |
ba6ad317 | 581 | iommus = <&smmu 0x874>; |
8f4e3972 | 582 | power-domains = <&pd_eth0>; |
44303dfa MS |
583 | }; |
584 | ||
585 | gem1: ethernet@ff0c0000 { | |
da2ad784 | 586 | compatible = "cdns,zynqmp-gem"; |
44303dfa MS |
587 | status = "disabled"; |
588 | interrupt-parent = <&gic>; | |
589 | interrupts = <0 59 4>, <0 59 4>; | |
b976fd63 | 590 | reg = <0x0 0xff0c0000 0x0 0x1000>; |
44303dfa MS |
591 | clock-names = "pclk", "hclk", "tx_clk"; |
592 | #address-cells = <1>; | |
593 | #size-cells = <0>; | |
7f1d7d97 | 594 | #stream-id-cells = <1>; |
ba6ad317 | 595 | iommus = <&smmu 0x875>; |
8f4e3972 | 596 | power-domains = <&pd_eth1>; |
44303dfa MS |
597 | }; |
598 | ||
599 | gem2: ethernet@ff0d0000 { | |
da2ad784 | 600 | compatible = "cdns,zynqmp-gem"; |
44303dfa MS |
601 | status = "disabled"; |
602 | interrupt-parent = <&gic>; | |
603 | interrupts = <0 61 4>, <0 61 4>; | |
b976fd63 | 604 | reg = <0x0 0xff0d0000 0x0 0x1000>; |
44303dfa MS |
605 | clock-names = "pclk", "hclk", "tx_clk"; |
606 | #address-cells = <1>; | |
607 | #size-cells = <0>; | |
7f1d7d97 | 608 | #stream-id-cells = <1>; |
ba6ad317 | 609 | iommus = <&smmu 0x876>; |
8f4e3972 | 610 | power-domains = <&pd_eth2>; |
44303dfa MS |
611 | }; |
612 | ||
613 | gem3: ethernet@ff0e0000 { | |
da2ad784 | 614 | compatible = "cdns,zynqmp-gem"; |
44303dfa MS |
615 | status = "disabled"; |
616 | interrupt-parent = <&gic>; | |
617 | interrupts = <0 63 4>, <0 63 4>; | |
b976fd63 | 618 | reg = <0x0 0xff0e0000 0x0 0x1000>; |
44303dfa MS |
619 | clock-names = "pclk", "hclk", "tx_clk"; |
620 | #address-cells = <1>; | |
621 | #size-cells = <0>; | |
7f1d7d97 | 622 | #stream-id-cells = <1>; |
ba6ad317 | 623 | iommus = <&smmu 0x877>; |
8f4e3972 | 624 | power-domains = <&pd_eth3>; |
44303dfa MS |
625 | }; |
626 | ||
627 | gpio: gpio@ff0a0000 { | |
628 | compatible = "xlnx,zynqmp-gpio-1.0"; | |
629 | status = "disabled"; | |
630 | #gpio-cells = <0x2>; | |
631 | interrupt-parent = <&gic>; | |
632 | interrupts = <0 16 4>; | |
9e826b68 MS |
633 | interrupt-controller; |
634 | #interrupt-cells = <2>; | |
b976fd63 | 635 | reg = <0x0 0xff0a0000 0x0 0x1000>; |
8f4e3972 | 636 | power-domains = <&pd_gpio>; |
44303dfa MS |
637 | }; |
638 | ||
639 | i2c0: i2c@ff020000 { | |
de4914b4 | 640 | compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; |
44303dfa MS |
641 | status = "disabled"; |
642 | interrupt-parent = <&gic>; | |
643 | interrupts = <0 17 4>; | |
b976fd63 | 644 | reg = <0x0 0xff020000 0x0 0x1000>; |
44303dfa MS |
645 | #address-cells = <1>; |
646 | #size-cells = <0>; | |
8f4e3972 | 647 | power-domains = <&pd_i2c0>; |
44303dfa MS |
648 | }; |
649 | ||
650 | i2c1: i2c@ff030000 { | |
de4914b4 | 651 | compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; |
44303dfa MS |
652 | status = "disabled"; |
653 | interrupt-parent = <&gic>; | |
654 | interrupts = <0 18 4>; | |
b976fd63 | 655 | reg = <0x0 0xff030000 0x0 0x1000>; |
44303dfa MS |
656 | #address-cells = <1>; |
657 | #size-cells = <0>; | |
8f4e3972 | 658 | power-domains = <&pd_i2c1>; |
44303dfa MS |
659 | }; |
660 | ||
5534480a NSR |
661 | ocm: memory-controller@ff960000 { |
662 | compatible = "xlnx,zynqmp-ocmc-1.0"; | |
b976fd63 | 663 | reg = <0x0 0xff960000 0x0 0x1000>; |
5534480a NSR |
664 | interrupt-parent = <&gic>; |
665 | interrupts = <0 10 4>; | |
666 | }; | |
667 | ||
44303dfa MS |
668 | pcie: pcie@fd0e0000 { |
669 | compatible = "xlnx,nwl-pcie-2.11"; | |
670 | status = "disabled"; | |
671 | #address-cells = <3>; | |
672 | #size-cells = <2>; | |
673 | #interrupt-cells = <1>; | |
7d6ca73a | 674 | msi-controller; |
44303dfa MS |
675 | device_type = "pci"; |
676 | interrupt-parent = <&gic>; | |
91a8b0ee | 677 | interrupts = <0 118 4>, |
7d6ca73a | 678 | <0 117 4>, |
91a8b0ee MS |
679 | <0 116 4>, |
680 | <0 115 4>, /* MSI_1 [63...32] */ | |
681 | <0 114 4>; /* MSI_0 [31...0] */ | |
7d6ca73a BKG |
682 | interrupt-names = "misc","dummy","intx", "msi1", "msi0"; |
683 | msi-parent = <&pcie>; | |
b976fd63 MS |
684 | reg = <0x0 0xfd0e0000 0x0 0x1000>, |
685 | <0x0 0xfd480000 0x0 0x1000>, | |
688d1be5 | 686 | <0x80 0x00000000 0x0 0x1000000>; |
44303dfa | 687 | reg-names = "breg", "pcireg", "cfg"; |
688d1be5 BKG |
688 | ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ |
689 | 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ | |
33aec517 BKG |
690 | interrupt-map-mask = <0x0 0x0 0x0 0x7>; |
691 | interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, | |
692 | <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, | |
693 | <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, | |
694 | <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; | |
2af3932f | 695 | power-domains = <&pd_pcie>; |
33aec517 BKG |
696 | pcie_intc: legacy-interrupt-controller { |
697 | interrupt-controller; | |
698 | #address-cells = <0>; | |
699 | #interrupt-cells = <1>; | |
700 | }; | |
44303dfa MS |
701 | }; |
702 | ||
703 | qspi: spi@ff0f0000 { | |
704 | compatible = "xlnx,zynqmp-qspi-1.0"; | |
705 | status = "disabled"; | |
706 | clock-names = "ref_clk", "pclk"; | |
707 | interrupts = <0 15 4>; | |
708 | interrupt-parent = <&gic>; | |
709 | num-cs = <1>; | |
b976fd63 MS |
710 | reg = <0x0 0xff0f0000 0x0 0x1000>, |
711 | <0x0 0xc0000000 0x0 0x8000000>; | |
44303dfa MS |
712 | #address-cells = <1>; |
713 | #size-cells = <0>; | |
ba6ad317 MS |
714 | #stream-id-cells = <1>; |
715 | iommus = <&smmu 0x873>; | |
8f4e3972 | 716 | power-domains = <&pd_qspi>; |
44303dfa MS |
717 | }; |
718 | ||
719 | rtc: rtc@ffa60000 { | |
720 | compatible = "xlnx,zynqmp-rtc"; | |
721 | status = "disabled"; | |
b976fd63 | 722 | reg = <0x0 0xffa60000 0x0 0x100>; |
44303dfa MS |
723 | interrupt-parent = <&gic>; |
724 | interrupts = <0 26 4>, <0 27 4>; | |
725 | interrupt-names = "alarm", "sec"; | |
726 | }; | |
727 | ||
db6c62e1 AKV |
728 | serdes: zynqmp_phy@fd400000 { |
729 | compatible = "xlnx,zynqmp-psgtr"; | |
730 | status = "disabled"; | |
b976fd63 MS |
731 | reg = <0x0 0xfd400000 0x0 0x40000>, |
732 | <0x0 0xfd3d0000 0x0 0x1000>, | |
733 | <0x0 0xfd1a0000 0x0 0x1000>, | |
734 | <0x0 0xff5e0000 0x0 0x1000>; | |
db6c62e1 AKV |
735 | reg-names = "serdes", "siou", "fpd", "lpd"; |
736 | xlnx,tx_termination_fix; | |
737 | lane0: lane0 { | |
738 | #phy-cells = <4>; | |
739 | }; | |
740 | lane1: lane1 { | |
741 | #phy-cells = <4>; | |
742 | }; | |
743 | lane2: lane2 { | |
744 | #phy-cells = <4>; | |
745 | }; | |
746 | lane3: lane3 { | |
747 | #phy-cells = <4>; | |
748 | }; | |
749 | }; | |
750 | ||
44303dfa MS |
751 | sata: ahci@fd0c0000 { |
752 | compatible = "ceva,ahci-1v84"; | |
753 | status = "disabled"; | |
b976fd63 | 754 | reg = <0x0 0xfd0c0000 0x0 0x2000>; |
44303dfa MS |
755 | interrupt-parent = <&gic>; |
756 | interrupts = <0 133 4>; | |
8f4e3972 | 757 | power-domains = <&pd_sata>; |
44303dfa MS |
758 | }; |
759 | ||
760 | sdhci0: sdhci@ff160000 { | |
c9811e14 | 761 | u-boot,dm-pre-reloc; |
0488a5e1 | 762 | compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; |
44303dfa MS |
763 | status = "disabled"; |
764 | interrupt-parent = <&gic>; | |
765 | interrupts = <0 48 4>; | |
b976fd63 | 766 | reg = <0x0 0xff160000 0x0 0x1000>; |
44303dfa | 767 | clock-names = "clk_xin", "clk_ahb"; |
0488a5e1 | 768 | xlnx,device_id = <0>; |
ba6ad317 MS |
769 | #stream-id-cells = <1>; |
770 | iommus = <&smmu 0x870>; | |
8f4e3972 | 771 | power-domains = <&pd_sd0>; |
44303dfa MS |
772 | }; |
773 | ||
774 | sdhci1: sdhci@ff170000 { | |
c9811e14 | 775 | u-boot,dm-pre-reloc; |
0488a5e1 | 776 | compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; |
44303dfa MS |
777 | status = "disabled"; |
778 | interrupt-parent = <&gic>; | |
779 | interrupts = <0 49 4>; | |
b976fd63 | 780 | reg = <0x0 0xff170000 0x0 0x1000>; |
44303dfa | 781 | clock-names = "clk_xin", "clk_ahb"; |
0488a5e1 | 782 | xlnx,device_id = <1>; |
ba6ad317 MS |
783 | #stream-id-cells = <1>; |
784 | iommus = <&smmu 0x871>; | |
8f4e3972 | 785 | power-domains = <&pd_sd1>; |
44303dfa MS |
786 | }; |
787 | ||
788 | smmu: smmu@fd800000 { | |
789 | compatible = "arm,mmu-500"; | |
b976fd63 | 790 | reg = <0x0 0xfd800000 0x0 0x20000>; |
ba6ad317 | 791 | #iommu-cells = <1>; |
44303dfa MS |
792 | #global-interrupts = <1>; |
793 | interrupt-parent = <&gic>; | |
88a85aac EI |
794 | interrupts = <0 155 4>, |
795 | <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, | |
796 | <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, | |
797 | <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, | |
798 | <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; | |
7f1d7d97 EI |
799 | mmu-masters = < &gem0 0x874 |
800 | &gem1 0x875 | |
801 | &gem2 0x876 | |
ba6ad317 MS |
802 | &gem3 0x877 |
803 | &usb0 0x860 | |
804 | &usb1 0x861 | |
805 | &qspi 0x873 | |
806 | &lpd_dma_chan1 0x868 | |
807 | &lpd_dma_chan2 0x869 | |
808 | &lpd_dma_chan3 0x86a | |
809 | &lpd_dma_chan4 0x86b | |
810 | &lpd_dma_chan5 0x86c | |
811 | &lpd_dma_chan6 0x86d | |
812 | &lpd_dma_chan7 0x86e | |
813 | &lpd_dma_chan8 0x86f | |
814 | &fpd_dma_chan1 0x14e8 | |
815 | &fpd_dma_chan2 0x14e9 | |
816 | &fpd_dma_chan3 0x14ea | |
817 | &fpd_dma_chan4 0x14eb | |
818 | &fpd_dma_chan5 0x14ec | |
819 | &fpd_dma_chan6 0x14ed | |
820 | &fpd_dma_chan7 0x14ee | |
821 | &fpd_dma_chan8 0x14ef | |
822 | &sdhci0 0x870 | |
823 | &sdhci1 0x871 | |
824 | &nand0 0x872>; | |
44303dfa MS |
825 | }; |
826 | ||
827 | spi0: spi@ff040000 { | |
828 | compatible = "cdns,spi-r1p6"; | |
829 | status = "disabled"; | |
830 | interrupt-parent = <&gic>; | |
831 | interrupts = <0 19 4>; | |
b976fd63 | 832 | reg = <0x0 0xff040000 0x0 0x1000>; |
44303dfa MS |
833 | clock-names = "ref_clk", "pclk"; |
834 | #address-cells = <1>; | |
835 | #size-cells = <0>; | |
8f4e3972 | 836 | power-domains = <&pd_spi0>; |
44303dfa MS |
837 | }; |
838 | ||
839 | spi1: spi@ff050000 { | |
840 | compatible = "cdns,spi-r1p6"; | |
841 | status = "disabled"; | |
842 | interrupt-parent = <&gic>; | |
843 | interrupts = <0 20 4>; | |
b976fd63 | 844 | reg = <0x0 0xff050000 0x0 0x1000>; |
44303dfa MS |
845 | clock-names = "ref_clk", "pclk"; |
846 | #address-cells = <1>; | |
847 | #size-cells = <0>; | |
8f4e3972 | 848 | power-domains = <&pd_spi1>; |
44303dfa MS |
849 | }; |
850 | ||
851 | ttc0: timer@ff110000 { | |
852 | compatible = "cdns,ttc"; | |
853 | status = "disabled"; | |
854 | interrupt-parent = <&gic>; | |
855 | interrupts = <0 36 4>, <0 37 4>, <0 38 4>; | |
b976fd63 | 856 | reg = <0x0 0xff110000 0x0 0x1000>; |
44303dfa | 857 | timer-width = <32>; |
8f4e3972 | 858 | power-domains = <&pd_ttc0>; |
44303dfa MS |
859 | }; |
860 | ||
861 | ttc1: timer@ff120000 { | |
862 | compatible = "cdns,ttc"; | |
863 | status = "disabled"; | |
864 | interrupt-parent = <&gic>; | |
865 | interrupts = <0 39 4>, <0 40 4>, <0 41 4>; | |
b976fd63 | 866 | reg = <0x0 0xff120000 0x0 0x1000>; |
44303dfa | 867 | timer-width = <32>; |
8f4e3972 | 868 | power-domains = <&pd_ttc1>; |
44303dfa MS |
869 | }; |
870 | ||
871 | ttc2: timer@ff130000 { | |
872 | compatible = "cdns,ttc"; | |
873 | status = "disabled"; | |
874 | interrupt-parent = <&gic>; | |
875 | interrupts = <0 42 4>, <0 43 4>, <0 44 4>; | |
b976fd63 | 876 | reg = <0x0 0xff130000 0x0 0x1000>; |
44303dfa | 877 | timer-width = <32>; |
8f4e3972 | 878 | power-domains = <&pd_ttc2>; |
44303dfa MS |
879 | }; |
880 | ||
881 | ttc3: timer@ff140000 { | |
882 | compatible = "cdns,ttc"; | |
883 | status = "disabled"; | |
884 | interrupt-parent = <&gic>; | |
885 | interrupts = <0 45 4>, <0 46 4>, <0 47 4>; | |
b976fd63 | 886 | reg = <0x0 0xff140000 0x0 0x1000>; |
44303dfa | 887 | timer-width = <32>; |
8f4e3972 | 888 | power-domains = <&pd_ttc3>; |
44303dfa MS |
889 | }; |
890 | ||
891 | uart0: serial@ff000000 { | |
c9811e14 | 892 | u-boot,dm-pre-reloc; |
ca2f5878 | 893 | compatible = "cdns,uart-r1p12", "xlnx,xuartps"; |
44303dfa MS |
894 | status = "disabled"; |
895 | interrupt-parent = <&gic>; | |
896 | interrupts = <0 21 4>; | |
b976fd63 | 897 | reg = <0x0 0xff000000 0x0 0x1000>; |
44303dfa | 898 | clock-names = "uart_clk", "pclk"; |
8f4e3972 | 899 | power-domains = <&pd_uart0>; |
44303dfa MS |
900 | }; |
901 | ||
902 | uart1: serial@ff010000 { | |
c9811e14 | 903 | u-boot,dm-pre-reloc; |
ca2f5878 | 904 | compatible = "cdns,uart-r1p12", "xlnx,xuartps"; |
44303dfa MS |
905 | status = "disabled"; |
906 | interrupt-parent = <&gic>; | |
907 | interrupts = <0 22 4>; | |
b976fd63 | 908 | reg = <0x0 0xff010000 0x0 0x1000>; |
44303dfa | 909 | clock-names = "uart_clk", "pclk"; |
8f4e3972 | 910 | power-domains = <&pd_uart1>; |
44303dfa MS |
911 | }; |
912 | ||
c926e6fb | 913 | usb0: usb0 { |
a84de48e | 914 | #address-cells = <2>; |
b976fd63 | 915 | #size-cells = <2>; |
44303dfa | 916 | status = "disabled"; |
a84de48e MS |
917 | compatible = "xlnx,zynqmp-dwc3"; |
918 | clock-names = "bus_clk", "ref_clk"; | |
919 | clocks = <&clk125>, <&clk125>; | |
ba6ad317 MS |
920 | #stream-id-cells = <1>; |
921 | iommus = <&smmu 0x860>; | |
8f4e3972 | 922 | power-domains = <&pd_usb0>; |
a84de48e MS |
923 | ranges; |
924 | ||
925 | dwc3_0: dwc3@fe200000 { | |
926 | compatible = "snps,dwc3"; | |
927 | status = "disabled"; | |
b976fd63 | 928 | reg = <0x0 0xfe200000 0x0 0x40000>; |
a84de48e MS |
929 | interrupt-parent = <&gic>; |
930 | interrupts = <0 65 4>; | |
931 | /* snps,quirk-frame-length-adjustment = <0x20>; */ | |
932 | snps,refclk_fladj; | |
933 | }; | |
44303dfa MS |
934 | }; |
935 | ||
c926e6fb | 936 | usb1: usb1 { |
a84de48e | 937 | #address-cells = <2>; |
b976fd63 | 938 | #size-cells = <2>; |
44303dfa | 939 | status = "disabled"; |
a84de48e MS |
940 | compatible = "xlnx,zynqmp-dwc3"; |
941 | clock-names = "bus_clk", "ref_clk"; | |
942 | clocks = <&clk125>, <&clk125>; | |
ba6ad317 MS |
943 | #stream-id-cells = <1>; |
944 | iommus = <&smmu 0x861>; | |
8f4e3972 | 945 | power-domains = <&pd_usb1>; |
a84de48e MS |
946 | ranges; |
947 | ||
948 | dwc3_1: dwc3@fe300000 { | |
949 | compatible = "snps,dwc3"; | |
950 | status = "disabled"; | |
b976fd63 | 951 | reg = <0x0 0xfe300000 0x0 0x40000>; |
a84de48e MS |
952 | interrupt-parent = <&gic>; |
953 | interrupts = <0 70 4>; | |
954 | /* snps,quirk-frame-length-adjustment = <0x20>; */ | |
955 | snps,refclk_fladj; | |
956 | }; | |
44303dfa MS |
957 | }; |
958 | ||
959 | watchdog0: watchdog@fd4d0000 { | |
960 | compatible = "cdns,wdt-r1p2"; | |
961 | status = "disabled"; | |
962 | interrupt-parent = <&gic>; | |
d3fd433f | 963 | interrupts = <0 113 1>; |
b976fd63 | 964 | reg = <0x0 0xfd4d0000 0x0 0x1000>; |
44303dfa MS |
965 | timeout-sec = <10>; |
966 | }; | |
967 | ||
968 | xilinx_drm: xilinx_drm { | |
969 | compatible = "xlnx,drm"; | |
970 | status = "disabled"; | |
971 | xlnx,encoder-slave = <&xlnx_dp>; | |
972 | xlnx,connector-type = "DisplayPort"; | |
973 | xlnx,dp-sub = <&xlnx_dp_sub>; | |
974 | planes { | |
975 | xlnx,pixel-format = "rgb565"; | |
976 | plane0 { | |
977 | dmas = <&xlnx_dpdma 3>; | |
bfe27980 | 978 | dma-names = "dma0"; |
44303dfa MS |
979 | }; |
980 | plane1 { | |
bfe27980 HK |
981 | dmas = <&xlnx_dpdma 0>, |
982 | <&xlnx_dpdma 1>, | |
983 | <&xlnx_dpdma 2>; | |
984 | dma-names = "dma0", "dma1", "dma2"; | |
44303dfa MS |
985 | }; |
986 | }; | |
987 | }; | |
988 | ||
695d75a1 | 989 | xlnx_dp: dp@fd4a0000 { |
44303dfa MS |
990 | compatible = "xlnx,v-dp"; |
991 | status = "disabled"; | |
b976fd63 | 992 | reg = <0x0 0xfd4a0000 0x0 0x1000>; |
44303dfa MS |
993 | interrupts = <0 119 4>; |
994 | interrupt-parent = <&gic>; | |
995 | clock-names = "aclk", "aud_clk"; | |
996 | xlnx,dp-version = "v1.2"; | |
997 | xlnx,max-lanes = <2>; | |
998 | xlnx,max-link-rate = <540000>; | |
999 | xlnx,max-bpc = <16>; | |
1000 | xlnx,enable-ycrcb; | |
1001 | xlnx,colormetry = "rgb"; | |
1002 | xlnx,bpc = <8>; | |
1003 | xlnx,audio-chan = <2>; | |
1004 | xlnx,dp-sub = <&xlnx_dp_sub>; | |
939cfeaf | 1005 | xlnx,max-pclock-frequency = <300000>; |
44303dfa MS |
1006 | }; |
1007 | ||
1008 | xlnx_dp_snd_card: dp_snd_card { | |
1009 | compatible = "xlnx,dp-snd-card"; | |
1010 | status = "disabled"; | |
1011 | xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>; | |
1012 | xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>; | |
1013 | }; | |
1014 | ||
1015 | xlnx_dp_snd_codec0: dp_snd_codec0 { | |
1016 | compatible = "xlnx,dp-snd-codec"; | |
1017 | status = "disabled"; | |
1018 | clock-names = "aud_clk"; | |
1019 | }; | |
1020 | ||
1021 | xlnx_dp_snd_pcm0: dp_snd_pcm0 { | |
1022 | compatible = "xlnx,dp-snd-pcm"; | |
1023 | status = "disabled"; | |
1024 | dmas = <&xlnx_dpdma 4>; | |
1025 | dma-names = "tx"; | |
1026 | }; | |
1027 | ||
1028 | xlnx_dp_snd_pcm1: dp_snd_pcm1 { | |
1029 | compatible = "xlnx,dp-snd-pcm"; | |
1030 | status = "disabled"; | |
1031 | dmas = <&xlnx_dpdma 5>; | |
1032 | dma-names = "tx"; | |
1033 | }; | |
1034 | ||
695d75a1 | 1035 | xlnx_dp_sub: dp_sub@fd4aa000 { |
44303dfa MS |
1036 | compatible = "xlnx,dp-sub"; |
1037 | status = "disabled"; | |
b976fd63 MS |
1038 | reg = <0x0 0xfd4aa000 0x0 0x1000>, |
1039 | <0x0 0xfd4ab000 0x0 0x1000>, | |
1040 | <0x0 0xfd4ac000 0x0 0x1000>; | |
44303dfa MS |
1041 | reg-names = "blend", "av_buf", "aud"; |
1042 | xlnx,output-fmt = "rgb"; | |
939cfeaf HK |
1043 | xlnx,vid-fmt = "yuyv"; |
1044 | xlnx,gfx-fmt = "rgb565"; | |
44303dfa MS |
1045 | }; |
1046 | ||
1047 | xlnx_dpdma: dma@fd4c0000 { | |
1048 | compatible = "xlnx,dpdma"; | |
1049 | status = "disabled"; | |
b976fd63 | 1050 | reg = <0x0 0xfd4c0000 0x0 0x1000>; |
44303dfa MS |
1051 | interrupts = <0 122 4>; |
1052 | interrupt-parent = <&gic>; | |
1053 | clock-names = "axi_clk"; | |
1054 | dma-channels = <6>; | |
1055 | #dma-cells = <1>; | |
c926e6fb | 1056 | dma-video0channel { |
44303dfa MS |
1057 | compatible = "xlnx,video0"; |
1058 | }; | |
c926e6fb | 1059 | dma-video1channel { |
44303dfa MS |
1060 | compatible = "xlnx,video1"; |
1061 | }; | |
c926e6fb | 1062 | dma-video2channel { |
44303dfa MS |
1063 | compatible = "xlnx,video2"; |
1064 | }; | |
c926e6fb | 1065 | dma-graphicschannel { |
44303dfa MS |
1066 | compatible = "xlnx,graphics"; |
1067 | }; | |
c926e6fb | 1068 | dma-audio0channel { |
44303dfa MS |
1069 | compatible = "xlnx,audio0"; |
1070 | }; | |
c926e6fb | 1071 | dma-audio1channel { |
44303dfa MS |
1072 | compatible = "xlnx,audio1"; |
1073 | }; | |
1074 | }; | |
1075 | }; | |
1076 | }; |