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|---|---|---|
| 62d7fe7c CN |
1 | /* |
| 2 | * ddr_defs.h | |
| 3 | * | |
| 4 | * ddr specific header | |
| 5 | * | |
| 6 | * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or | |
| 9 | * modify it under the terms of the GNU General Public License as | |
| 10 | * published by the Free Software Foundation; either version 2 of | |
| 11 | * the License, or (at your option) any later version. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, | |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the | |
| 16 | * GNU General Public License for more details. | |
| 17 | */ | |
| 18 | ||
| 19 | #ifndef _DDR_DEFS_H | |
| 20 | #define _DDR_DEFS_H | |
| 21 | ||
| 22 | #include <asm/arch/hardware.h> | |
| ff7ec0f9 | 23 | #include <asm/emif.h> |
| 62d7fe7c CN |
24 | |
| 25 | /* AM335X EMIF Register values */ | |
| 62d7fe7c CN |
26 | #define VTP_CTRL_READY (0x1 << 5) |
| 27 | #define VTP_CTRL_ENABLE (0x1 << 6) | |
| 62d7fe7c | 28 | #define VTP_CTRL_START_EN (0x1) |
| c8da4a58 | 29 | #define PHY_DLL_LOCK_DIFF 0x0 |
| c48c8954 | 30 | #define DDR_CKE_CTRL_NORMAL 0x1 |
| 59dcf970 | 31 | #define PHY_EN_DYN_PWRDN (0x1 << 20) |
| 62d7fe7c | 32 | |
| c00f69db | 33 | /* Micron MT47H128M16RT-25E */ |
| c7d35bef PK |
34 | #define MT47H128M16RT25E_EMIF_READ_LATENCY 0x100005 |
| 35 | #define MT47H128M16RT25E_EMIF_TIM1 0x0666B3C9 | |
| 36 | #define MT47H128M16RT25E_EMIF_TIM2 0x243631CA | |
| 37 | #define MT47H128M16RT25E_EMIF_TIM3 0x0000033F | |
| 38 | #define MT47H128M16RT25E_EMIF_SDCFG 0x41805332 | |
| 39 | #define MT47H128M16RT25E_EMIF_SDREF 0x0000081a | |
| 40 | #define MT47H128M16RT25E_DLL_LOCK_DIFF 0x0 | |
| 41 | #define MT47H128M16RT25E_RATIO 0x80 | |
| 42 | #define MT47H128M16RT25E_INVERT_CLKOUT 0x00 | |
| 43 | #define MT47H128M16RT25E_RD_DQS 0x12 | |
| 44 | #define MT47H128M16RT25E_WR_DQS 0x00 | |
| 45 | #define MT47H128M16RT25E_PHY_WRLVL 0x00 | |
| 46 | #define MT47H128M16RT25E_PHY_GATELVL 0x00 | |
| 47 | #define MT47H128M16RT25E_PHY_WR_DATA 0x40 | |
| 48 | #define MT47H128M16RT25E_PHY_FIFO_WE 0x80 | |
| 49 | #define MT47H128M16RT25E_PHY_RANK0_DELAY 0x1 | |
| 50 | #define MT47H128M16RT25E_IOCTRL_VALUE 0x18B | |
| 62d7fe7c | 51 | |
| d4898ea8 | 52 | /* Micron MT41J128M16JT-125 */ |
| c7d35bef PK |
53 | #define MT41J128MJT125_EMIF_READ_LATENCY 0x06 |
| 54 | #define MT41J128MJT125_EMIF_TIM1 0x0888A39B | |
| 55 | #define MT41J128MJT125_EMIF_TIM2 0x26337FDA | |
| 56 | #define MT41J128MJT125_EMIF_TIM3 0x501F830F | |
| 57 | #define MT41J128MJT125_EMIF_SDCFG 0x61C04AB2 | |
| 58 | #define MT41J128MJT125_EMIF_SDREF 0x0000093B | |
| 59 | #define MT41J128MJT125_ZQ_CFG 0x50074BE4 | |
| 60 | #define MT41J128MJT125_DLL_LOCK_DIFF 0x1 | |
| 61 | #define MT41J128MJT125_RATIO 0x40 | |
| 62 | #define MT41J128MJT125_INVERT_CLKOUT 0x1 | |
| 63 | #define MT41J128MJT125_RD_DQS 0x3B | |
| 64 | #define MT41J128MJT125_WR_DQS 0x85 | |
| 65 | #define MT41J128MJT125_PHY_WR_DATA 0xC1 | |
| 66 | #define MT41J128MJT125_PHY_FIFO_WE 0x100 | |
| 67 | #define MT41J128MJT125_IOCTRL_VALUE 0x18B | |
| d4898ea8 | 68 | |
| 1c1b7c37 LP |
69 | /* Micron MT41J256M8HX-15E */ |
| 70 | #define MT41J256M8HX15E_EMIF_READ_LATENCY 0x06 | |
| 71 | #define MT41J256M8HX15E_EMIF_TIM1 0x0888A39B | |
| 72 | #define MT41J256M8HX15E_EMIF_TIM2 0x26337FDA | |
| 73 | #define MT41J256M8HX15E_EMIF_TIM3 0x501F830F | |
| 74 | #define MT41J256M8HX15E_EMIF_SDCFG 0x61C04B32 | |
| 75 | #define MT41J256M8HX15E_EMIF_SDREF 0x0000093B | |
| 76 | #define MT41J256M8HX15E_ZQ_CFG 0x50074BE4 | |
| 77 | #define MT41J256M8HX15E_DLL_LOCK_DIFF 0x1 | |
| 78 | #define MT41J256M8HX15E_RATIO 0x40 | |
| 79 | #define MT41J256M8HX15E_INVERT_CLKOUT 0x1 | |
| 80 | #define MT41J256M8HX15E_RD_DQS 0x3B | |
| 81 | #define MT41J256M8HX15E_WR_DQS 0x85 | |
| 82 | #define MT41J256M8HX15E_PHY_WR_DATA 0xC1 | |
| 83 | #define MT41J256M8HX15E_PHY_FIFO_WE 0x100 | |
| 84 | #define MT41J256M8HX15E_IOCTRL_VALUE 0x18B | |
| 85 | ||
| 13526f71 JL |
86 | /* Micron MT41J512M8RH-125 on EVM v1.5 */ |
| 87 | #define MT41J512M8RH125_EMIF_READ_LATENCY 0x06 | |
| 88 | #define MT41J512M8RH125_EMIF_TIM1 0x0888A39B | |
| 89 | #define MT41J512M8RH125_EMIF_TIM2 0x26517FDA | |
| 90 | #define MT41J512M8RH125_EMIF_TIM3 0x501F84EF | |
| 91 | #define MT41J512M8RH125_EMIF_SDCFG 0x61C04BB2 | |
| 92 | #define MT41J512M8RH125_EMIF_SDREF 0x0000093B | |
| 93 | #define MT41J512M8RH125_ZQ_CFG 0x50074BE4 | |
| 94 | #define MT41J512M8RH125_DLL_LOCK_DIFF 0x1 | |
| 95 | #define MT41J512M8RH125_RATIO 0x80 | |
| 96 | #define MT41J512M8RH125_INVERT_CLKOUT 0x0 | |
| 97 | #define MT41J512M8RH125_RD_DQS 0x3B | |
| 98 | #define MT41J512M8RH125_WR_DQS 0x3C | |
| 99 | #define MT41J512M8RH125_PHY_FIFO_WE 0xA5 | |
| 100 | #define MT41J512M8RH125_PHY_WR_DATA 0x74 | |
| 101 | #define MT41J512M8RH125_IOCTRL_VALUE 0x18B | |
| 1c1b7c37 | 102 | |
| 62d7fe7c CN |
103 | /** |
| 104 | * Configure SDRAM | |
| 105 | */ | |
| 3ba65f97 | 106 | void config_sdram(const struct emif_regs *regs, int nr); |
| 62d7fe7c CN |
107 | |
| 108 | /** | |
| 109 | * Set SDRAM timings | |
| 110 | */ | |
| 3ba65f97 | 111 | void set_sdram_timings(const struct emif_regs *regs, int nr); |
| 62d7fe7c CN |
112 | |
| 113 | /** | |
| 114 | * Configure DDR PHY | |
| 115 | */ | |
| 3ba65f97 MP |
116 | void config_ddr_phy(const struct emif_regs *regs, int nr); |
| 117 | ||
| 118 | struct ddr_cmd_regs { | |
| 119 | unsigned int resv0[7]; | |
| 120 | unsigned int cm0csratio; /* offset 0x01C */ | |
| 121 | unsigned int resv1[2]; | |
| 122 | unsigned int cm0dldiff; /* offset 0x028 */ | |
| 123 | unsigned int cm0iclkout; /* offset 0x02C */ | |
| 124 | unsigned int resv2[8]; | |
| 125 | unsigned int cm1csratio; /* offset 0x050 */ | |
| 126 | unsigned int resv3[2]; | |
| 127 | unsigned int cm1dldiff; /* offset 0x05C */ | |
| 128 | unsigned int cm1iclkout; /* offset 0x060 */ | |
| 129 | unsigned int resv4[8]; | |
| 130 | unsigned int cm2csratio; /* offset 0x084 */ | |
| 131 | unsigned int resv5[2]; | |
| 132 | unsigned int cm2dldiff; /* offset 0x090 */ | |
| 133 | unsigned int cm2iclkout; /* offset 0x094 */ | |
| 134 | unsigned int resv6[3]; | |
| 135 | }; | |
| 136 | ||
| 137 | struct ddr_data_regs { | |
| 138 | unsigned int dt0rdsratio0; /* offset 0x0C8 */ | |
| 139 | unsigned int resv1[4]; | |
| 140 | unsigned int dt0wdsratio0; /* offset 0x0DC */ | |
| 141 | unsigned int resv2[4]; | |
| 142 | unsigned int dt0wiratio0; /* offset 0x0F0 */ | |
| 143 | unsigned int resv3; | |
| 144 | unsigned int dt0wimode0; /* offset 0x0F8 */ | |
| 145 | unsigned int dt0giratio0; /* offset 0x0FC */ | |
| 146 | unsigned int resv4; | |
| 147 | unsigned int dt0gimode0; /* offset 0x104 */ | |
| 148 | unsigned int dt0fwsratio0; /* offset 0x108 */ | |
| 149 | unsigned int resv5[4]; | |
| 150 | unsigned int dt0dqoffset; /* offset 0x11C */ | |
| 151 | unsigned int dt0wrsratio0; /* offset 0x120 */ | |
| 152 | unsigned int resv6[4]; | |
| 153 | unsigned int dt0rdelays0; /* offset 0x134 */ | |
| 154 | unsigned int dt0dldiff0; /* offset 0x138 */ | |
| 155 | unsigned int resv7[12]; | |
| 156 | }; | |
| 62d7fe7c CN |
157 | |
| 158 | /** | |
| 159 | * This structure represents the DDR registers on AM33XX devices. | |
| a74f0c7c TR |
160 | * We make use of DDR_PHY_BASE_ADDR2 to address the DATA1 registers that |
| 161 | * correspond to DATA1 registers defined here. | |
| 62d7fe7c CN |
162 | */ |
| 163 | struct ddr_regs { | |
| 164 | unsigned int resv0[7]; | |
| 165 | unsigned int cm0csratio; /* offset 0x01C */ | |
| a74f0c7c | 166 | unsigned int resv1[2]; |
| 62d7fe7c CN |
167 | unsigned int cm0dldiff; /* offset 0x028 */ |
| 168 | unsigned int cm0iclkout; /* offset 0x02C */ | |
| a74f0c7c | 169 | unsigned int resv2[8]; |
| 62d7fe7c | 170 | unsigned int cm1csratio; /* offset 0x050 */ |
| a74f0c7c | 171 | unsigned int resv3[2]; |
| 62d7fe7c CN |
172 | unsigned int cm1dldiff; /* offset 0x05C */ |
| 173 | unsigned int cm1iclkout; /* offset 0x060 */ | |
| a74f0c7c | 174 | unsigned int resv4[8]; |
| 62d7fe7c | 175 | unsigned int cm2csratio; /* offset 0x084 */ |
| a74f0c7c | 176 | unsigned int resv5[2]; |
| 62d7fe7c CN |
177 | unsigned int cm2dldiff; /* offset 0x090 */ |
| 178 | unsigned int cm2iclkout; /* offset 0x094 */ | |
| a74f0c7c | 179 | unsigned int resv6[12]; |
| 62d7fe7c | 180 | unsigned int dt0rdsratio0; /* offset 0x0C8 */ |
| a74f0c7c | 181 | unsigned int resv7[4]; |
| 62d7fe7c | 182 | unsigned int dt0wdsratio0; /* offset 0x0DC */ |
| a74f0c7c | 183 | unsigned int resv8[4]; |
| 62d7fe7c | 184 | unsigned int dt0wiratio0; /* offset 0x0F0 */ |
| a74f0c7c TR |
185 | unsigned int resv9; |
| 186 | unsigned int dt0wimode0; /* offset 0x0F8 */ | |
| 62d7fe7c | 187 | unsigned int dt0giratio0; /* offset 0x0FC */ |
| a74f0c7c TR |
188 | unsigned int resv10; |
| 189 | unsigned int dt0gimode0; /* offset 0x104 */ | |
| 62d7fe7c | 190 | unsigned int dt0fwsratio0; /* offset 0x108 */ |
| a74f0c7c TR |
191 | unsigned int resv11[4]; |
| 192 | unsigned int dt0dqoffset; /* offset 0x11C */ | |
| 62d7fe7c | 193 | unsigned int dt0wrsratio0; /* offset 0x120 */ |
| a74f0c7c | 194 | unsigned int resv12[4]; |
| 62d7fe7c CN |
195 | unsigned int dt0rdelays0; /* offset 0x134 */ |
| 196 | unsigned int dt0dldiff0; /* offset 0x138 */ | |
| 62d7fe7c CN |
197 | }; |
| 198 | ||
| 199 | /** | |
| 200 | * Encapsulates DDR CMD control registers. | |
| 201 | */ | |
| 202 | struct cmd_control { | |
| 203 | unsigned long cmd0csratio; | |
| 204 | unsigned long cmd0csforce; | |
| 205 | unsigned long cmd0csdelay; | |
| 206 | unsigned long cmd0dldiff; | |
| 207 | unsigned long cmd0iclkout; | |
| 208 | unsigned long cmd1csratio; | |
| 209 | unsigned long cmd1csforce; | |
| 210 | unsigned long cmd1csdelay; | |
| 211 | unsigned long cmd1dldiff; | |
| 212 | unsigned long cmd1iclkout; | |
| 213 | unsigned long cmd2csratio; | |
| 214 | unsigned long cmd2csforce; | |
| 215 | unsigned long cmd2csdelay; | |
| 216 | unsigned long cmd2dldiff; | |
| 217 | unsigned long cmd2iclkout; | |
| 218 | }; | |
| 219 | ||
| 220 | /** | |
| 221 | * Encapsulates DDR DATA registers. | |
| 222 | */ | |
| 223 | struct ddr_data { | |
| 224 | unsigned long datardsratio0; | |
| 62d7fe7c | 225 | unsigned long datawdsratio0; |
| 62d7fe7c | 226 | unsigned long datawiratio0; |
| 62d7fe7c | 227 | unsigned long datagiratio0; |
| 62d7fe7c | 228 | unsigned long datafwsratio0; |
| 62d7fe7c | 229 | unsigned long datawrsratio0; |
| a74f0c7c | 230 | unsigned long datauserank0delay; |
| 62d7fe7c CN |
231 | unsigned long datadldiff0; |
| 232 | }; | |
| 233 | ||
| 234 | /** | |
| 235 | * Configure DDR CMD control registers | |
| 236 | */ | |
| 3ba65f97 | 237 | void config_cmd_ctrl(const struct cmd_control *cmd, int nr); |
| 62d7fe7c CN |
238 | |
| 239 | /** | |
| 240 | * Configure DDR DATA registers | |
| 241 | */ | |
| 3ba65f97 | 242 | void config_ddr_data(const struct ddr_data *data, int nr); |
| 62d7fe7c CN |
243 | |
| 244 | /** | |
| 245 | * This structure represents the DDR io control on AM33XX devices. | |
| 246 | */ | |
| 247 | struct ddr_cmdtctrl { | |
| 248 | unsigned int resv1[1]; | |
| 249 | unsigned int cm0ioctl; | |
| 250 | unsigned int cm1ioctl; | |
| 251 | unsigned int cm2ioctl; | |
| 252 | unsigned int resv2[12]; | |
| 253 | unsigned int dt0ioctl; | |
| 254 | unsigned int dt1ioctl; | |
| 255 | }; | |
| 256 | ||
| 62d7fe7c CN |
257 | /** |
| 258 | * Configure DDR io control registers | |
| 259 | */ | |
| 5ac3b7ad | 260 | void config_io_ctrl(unsigned long val); |
| 62d7fe7c CN |
261 | |
| 262 | struct ddr_ctrl { | |
| 263 | unsigned int ddrioctrl; | |
| 264 | unsigned int resv1[325]; | |
| 265 | unsigned int ddrckectrl; | |
| 266 | }; | |
| 267 | ||
| c00f69db PK |
268 | void config_ddr(unsigned int pll, unsigned int ioctrl, |
| 269 | const struct ddr_data *data, const struct cmd_control *ctrl, | |
| 3ba65f97 | 270 | const struct emif_regs *regs, int nr); |
| 62d7fe7c CN |
271 | |
| 272 | #endif /* _DDR_DEFS_H */ |