[people/ms/u-boot.git] / arch / arm / include / asm / arch-am33xx / hardware_am43xx.h

/*
 * hardware_am43xx.h
 *
 * AM43xx hardware specific header
 *
 * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __AM43XX_HARDWARE_AM43XX_H
#define __AM43XX_HARDWARE_AM43XX_H

/* Module base addresses */

/* UART Base Address */
#define UART0_BASE			0x44E09000

/* GPIO Base address */
#define GPIO2_BASE			0x481AC000

/* Watchdog Timer */
#define WDT_BASE			0x44E35000

/* Control Module Base Address */
#define CTRL_BASE			0x44E10000
#define CTRL_DEVICE_BASE		0x44E10600

/* PRCM Base Address */
#define PRCM_BASE			0x44DF0000
#define	CM_WKUP				0x44DF2800
#define	CM_PER				0x44DF8800

#define PRM_RSTCTRL			(PRCM_BASE + 0x4000)
#define PRM_RSTST			(PRM_RSTCTRL + 4)

/* VTP Base address */
#define VTP0_CTRL_ADDR			0x44E10E0C
#define VTP1_CTRL_ADDR			0x48140E10

/* DDR Base address */
#define DDR_PHY_CMD_ADDR		0x44E12000
#define DDR_PHY_DATA_ADDR		0x44E120C8
#define DDR_PHY_CMD_ADDR2		0x47C0C800
#define DDR_PHY_DATA_ADDR2		0x47C0C8C8
#define DDR_DATA_REGS_NR		2

/* CPSW Config space */
#define CPSW_MDIO_BASE			0x4A101000

/* RTC base address */
#define RTC_BASE			0x44E3E000

#endif /* __AM43XX_HARDWARE_AM43XX_H */
Commit	Line	Data
c06e498a LV	1	/*
	2	* hardware_am43xx.h
	3	*
	4	* AM43xx hardware specific header
	5	*
	6	* Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
	7	*
	8	* SPDX-License-Identifier: GPL-2.0+
	9	*/
	10
	11	#ifndef __AM43XX_HARDWARE_AM43XX_H
	12	#define __AM43XX_HARDWARE_AM43XX_H
	13
	14	/* Module base addresses */
	15
	16	/* UART Base Address */
	17	#define UART0_BASE 0x44E09000
	18
	19	/* GPIO Base address */
	20	#define GPIO2_BASE 0x481AC000
	21
	22	/* Watchdog Timer */
	23	#define WDT_BASE 0x44E35000
	24
	25	/* Control Module Base Address */
	26	#define CTRL_BASE 0x44E10000
	27	#define CTRL_DEVICE_BASE 0x44E10600
	28
	29	/* PRCM Base Address */
	30	#define PRCM_BASE 0x44DF0000
	31	#define CM_WKUP 0x44DF2800
	32	#define CM_PER 0x44DF8800
	33
	34	#define PRM_RSTCTRL (PRCM_BASE + 0x4000)
	35	#define PRM_RSTST (PRM_RSTCTRL + 4)
	36
	37	/* VTP Base address */
	38	#define VTP0_CTRL_ADDR 0x44E10E0C
dcf846d5	39	#define VTP1_CTRL_ADDR 0x48140E10
c06e498a LV	40
	41	/* DDR Base address */
	42	#define DDR_PHY_CMD_ADDR 0x44E12000
	43	#define DDR_PHY_DATA_ADDR 0x44E120C8
dcf846d5 TA	44	#define DDR_PHY_CMD_ADDR2 0x47C0C800
dcf846d5 TA	45	#define DDR_PHY_DATA_ADDR2 0x47C0C8C8
c06e498a LV	46	#define DDR_DATA_REGS_NR 2
	47
	48	/* CPSW Config space */
	49	#define CPSW_MDIO_BASE 0x4A101000
	50
	51	/* RTC base address */
	52	#define RTC_BASE 0x44E3E000
	53
	54	#endif /* __AM43XX_HARDWARE_AM43XX_H */