projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 843a2654 JCPV |
1 | /* |
| 2 | * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_wdt.h] | |
| 3 | * | |
| 4 | * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | |
| 5 | * Copyright (C) 2007 Andrew Victor | |
| 6 | * Copyright (C) 2007 Atmel Corporation. | |
| 7 | * | |
| 8 | * Watchdog Timer (WDT) - System peripherals regsters. | |
| 9 | * Based on AT91SAM9261 datasheet revision D. | |
| 10 | * | |
| 11 | * This program is free software; you can redistribute it and/or modify | |
| 12 | * it under the terms of the GNU General Public License as published by | |
| 13 | * the Free Software Foundation; either version 2 of the License, or | |
| 14 | * (at your option) any later version. | |
| 15 | */ | |
| 16 | ||
| 17 | #ifndef AT91_WDT_H | |
| 18 | #define AT91_WDT_H | |
| 19 | ||
| 5d8e359c JS |
20 | #ifdef __ASSEMBLY__ |
| 21 | ||
| 22 | #define AT91_ASM_WDT_MR (AT91_WDT_BASE + 0x04) | |
| 23 | ||
| 24 | #else | |
| 25 | ||
| 26 | typedef struct at91_wdt { | |
| 27 | u32 cr; | |
| 28 | u32 mr; | |
| 29 | u32 sr; | |
| 30 | } at91_wdt_t; | |
| 31 | ||
| 32 | #endif | |
| 33 | ||
| 34 | #define AT91_WDT_CR_WDRSTT 1 | |
| 35 | #define AT91_WDT_CR_KEY 0xa5000000 /* KEY Password */ | |
| 36 | ||
| 37 | #define AT91_WDT_MR_WDV(x) (x & 0xfff) | |
| 38 | #define AT91_WDT_MR_WDFIEN 0x00001000 | |
| 39 | #define AT91_WDT_MR_WDRSTEN 0x00002000 | |
| 40 | #define AT91_WDT_MR_WDRPROC 0x00004000 | |
| 41 | #define AT91_WDT_MR_WDDIS 0x00008000 | |
| 42 | #define AT91_WDT_MR_WDD(x) ((x & 0xfff) << 16) | |
| 43 | #define AT91_WDT_MR_WDDBGHLT 0x10000000 | |
| 44 | #define AT91_WDT_MR_WDIDLEHLT 0x20000000 | |
| 45 | ||
| 46 | #ifdef CONFIG_AT91_LEGACY | |
| 47 | ||
| 843a2654 JCPV |
48 | #define AT91_WDT_CR (AT91_WDT + 0x00) /* Watchdog Control Register */ |
| 49 | #define AT91_WDT_WDRSTT (1 << 0) /* Restart */ | |
| 50 | #define AT91_WDT_KEY (0xa5 << 24) /* KEY Password */ | |
| 51 | ||
| 52 | #define AT91_WDT_MR (AT91_WDT + 0x04) /* Watchdog Mode Register */ | |
| 53 | #define AT91_WDT_WDV (0xfff << 0) /* Counter Value */ | |
| 54 | #define AT91_WDT_WDFIEN (1 << 12) /* Fault Interrupt Enable */ | |
| 55 | #define AT91_WDT_WDRSTEN (1 << 13) /* Reset Processor */ | |
| 56 | #define AT91_WDT_WDRPROC (1 << 14) /* Timer Restart */ | |
| 57 | #define AT91_WDT_WDDIS (1 << 15) /* Watchdog Disable */ | |
| 58 | #define AT91_WDT_WDD (0xfff << 16) /* Delta Value */ | |
| 59 | #define AT91_WDT_WDDBGHLT (1 << 28) /* Debug Halt */ | |
| 60 | #define AT91_WDT_WDIDLEHLT (1 << 29) /* Idle Halt */ | |
| 61 | ||
| 62 | #define AT91_WDT_SR (AT91_WDT + 0x08) /* Watchdog Status Register */ | |
| 63 | #define AT91_WDT_WDUNF (1 << 0) /* Watchdog Underflow */ | |
| 64 | #define AT91_WDT_WDERR (1 << 1) /* Watchdog Error */ | |
| 65 | ||
| 5d8e359c | 66 | #endif /* CONFIG_AT91_LEGACY */ |
| 843a2654 | 67 | #endif |