projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 6d1dbbbf | 1 | /* |
| 4f6c8101 | 2 | * [origin: Linux kernel include/asm-arm/arch-at91/at91cap9.h] |
| 6d1dbbbf | 3 | * |
| c9e798d3 | 4 | * Copyright (C) 2007 Stelian Pop <stelian@popies.net> |
| 6d1dbbbf SP |
5 | * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com> |
| 6 | * Copyright (C) 2007 Atmel Corporation. | |
| 7 | * | |
| 8 | * Common definitions. | |
| 9 | * Based on AT91CAP9 datasheet revision B (Preliminary). | |
| 10 | * | |
| 1a459660 | 11 | * SPDX-License-Identifier: GPL-2.0+ |
| 6d1dbbbf SP |
12 | */ |
| 13 | ||
| 14 | #ifndef AT91CAP9_H | |
| 15 | #define AT91CAP9_H | |
| 16 | ||
| 17 | /* | |
| 18 | * Peripheral identifiers/interrupts. | |
| 19 | */ | |
| 20 | #define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ | |
| 21 | #define AT91_ID_SYS 1 /* System Peripherals */ | |
| 22 | #define AT91CAP9_ID_PIOABCD 2 /* Parallel IO Controller A, B, C and D */ | |
| 23 | #define AT91CAP9_ID_MPB0 3 /* MP Block Peripheral 0 */ | |
| 24 | #define AT91CAP9_ID_MPB1 4 /* MP Block Peripheral 1 */ | |
| 25 | #define AT91CAP9_ID_MPB2 5 /* MP Block Peripheral 2 */ | |
| 26 | #define AT91CAP9_ID_MPB3 6 /* MP Block Peripheral 3 */ | |
| 27 | #define AT91CAP9_ID_MPB4 7 /* MP Block Peripheral 4 */ | |
| 28 | #define AT91CAP9_ID_US0 8 /* USART 0 */ | |
| 29 | #define AT91CAP9_ID_US1 9 /* USART 1 */ | |
| 30 | #define AT91CAP9_ID_US2 10 /* USART 2 */ | |
| 31 | #define AT91CAP9_ID_MCI0 11 /* Multimedia Card Interface 0 */ | |
| 32 | #define AT91CAP9_ID_MCI1 12 /* Multimedia Card Interface 1 */ | |
| 33 | #define AT91CAP9_ID_CAN 13 /* CAN */ | |
| 34 | #define AT91CAP9_ID_TWI 14 /* Two-Wire Interface */ | |
| 35 | #define AT91CAP9_ID_SPI0 15 /* Serial Peripheral Interface 0 */ | |
| 36 | #define AT91CAP9_ID_SPI1 16 /* Serial Peripheral Interface 0 */ | |
| 37 | #define AT91CAP9_ID_SSC0 17 /* Serial Synchronous Controller 0 */ | |
| 38 | #define AT91CAP9_ID_SSC1 18 /* Serial Synchronous Controller 1 */ | |
| 39 | #define AT91CAP9_ID_AC97C 19 /* AC97 Controller */ | |
| 40 | #define AT91CAP9_ID_TCB 20 /* Timer Counter 0, 1 and 2 */ | |
| 41 | #define AT91CAP9_ID_PWMC 21 /* Pulse Width Modulation Controller */ | |
| 42 | #define AT91CAP9_ID_EMAC 22 /* Ethernet */ | |
| 43 | #define AT91CAP9_ID_AESTDES 23 /* Advanced Encryption Standard, Triple DES */ | |
| 44 | #define AT91CAP9_ID_ADC 24 /* Analog-to-Digital Converter */ | |
| 45 | #define AT91CAP9_ID_ISI 25 /* Image Sensor Interface */ | |
| 46 | #define AT91CAP9_ID_LCDC 26 /* LCD Controller */ | |
| 47 | #define AT91CAP9_ID_DMA 27 /* DMA Controller */ | |
| 48 | #define AT91CAP9_ID_UDPHS 28 /* USB High Speed Device Port */ | |
| 49 | #define AT91CAP9_ID_UHP 29 /* USB Host Port */ | |
| 50 | #define AT91CAP9_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ | |
| 51 | #define AT91CAP9_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */ | |
| 52 | ||
| 5d8e359c JS |
53 | #define AT91_PIO_BASE 0xfffff200 |
| 54 | #define AT91_PMC_BASE 0xfffffc00 | |
| 55 | #define AT91_RSTC_BASE 0xfffffd00 | |
| 56 | #define AT91_PIT_BASE 0xfffffd30 | |
| 57 | ||
| 6d1dbbbf SP |
58 | /* |
| 59 | * Internal Memory. | |
| 60 | */ | |
| 61 | #define AT91CAP9_SRAM_BASE 0x00100000 /* Internal SRAM base address */ | |
| 62 | #define AT91CAP9_SRAM_SIZE (32 * SZ_1K) /* Internal SRAM size (32Kb) */ | |
| 63 | ||
| 64 | #define AT91CAP9_ROM_BASE 0x00400000 /* Internal ROM base address */ | |
| 65 | #define AT91CAP9_ROM_SIZE (32 * SZ_1K) /* Internal ROM size (32Kb) */ | |
| 66 | ||
| 67 | #define AT91CAP9_LCDC_BASE 0x00500000 /* LCD Controller */ | |
| 68 | #define AT91CAP9_UDPHS_BASE 0x00600000 /* USB High Speed Device Port */ | |
| 69 | #define AT91CAP9_UHP_BASE 0x00700000 /* USB Host controller */ | |
| 70 | ||
| 71 | #define CONFIG_DRAM_BASE AT91_CHIPSELECT_6 | |
| 72 | ||
| b32e1890 JCPV |
73 | /* |
| 74 | * Cpu Name | |
| 75 | */ | |
| 7c966a8b | 76 | #define CONFIG_SYS_AT91_CPU_NAME "AT91CAP9" |
| b32e1890 | 77 | |
| 6d1dbbbf | 78 | #endif |