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1 | /* |
2 | * Chip-specific header file for the AT91SAM9x5 family | |
3 | * | |
e542377a | 4 | * Copyright (C) 2012-2013 Atmel Corporation. |
f7fa2f37 BS |
5 | * |
6 | * Definitions for the SoC: | |
e542377a | 7 | * AT91SAM9x5 & AT91SAM9N12 |
f7fa2f37 | 8 | * |
1a459660 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
f7fa2f37 BS |
10 | */ |
11 | ||
12 | #ifndef __AT91SAM9X5_H__ | |
13 | #define __AT91SAM9X5_H__ | |
14 | ||
15 | /* | |
16 | * Peripheral identifiers/interrupts. | |
17 | */ | |
18 | #define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ | |
19 | #define ATMEL_ID_SYS 1 /* System Controller Interrupt */ | |
20 | #define ATMEL_ID_PIOAB 2 /* Parallel I/O Controller A and B */ | |
21 | #define ATMEL_ID_PIOCD 3 /* Parallel I/O Controller C and D */ | |
e542377a WJ |
22 | #define ATMEL_ID_SMD 4 /* SMD Soft Modem (SMD), only for AT91SAM9X5 */ |
23 | #define ATMEL_ID_FUSE 4 /* FUSE Controller, only for AT91SAM9N12 */ | |
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24 | #define ATMEL_ID_USART0 5 /* USART 0 */ |
25 | #define ATMEL_ID_USART1 6 /* USART 1 */ | |
26 | #define ATMEL_ID_USART2 7 /* USART 2 */ | |
e542377a | 27 | #define ATMEL_ID_USART3 8 /* USART 3 */ |
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28 | #define ATMEL_ID_TWI0 9 /* Two-Wire Interface 0 */ |
29 | #define ATMEL_ID_TWI1 10 /* Two-Wire Interface 1 */ | |
30 | #define ATMEL_ID_TWI2 11 /* Two-Wire Interface 2 */ | |
31 | #define ATMEL_ID_HSMCI0 12 /* High Speed Multimedia Card Interface 0 */ | |
32 | #define ATMEL_ID_SPI0 13 /* Serial Peripheral Interface 0 */ | |
33 | #define ATMEL_ID_SPI1 14 /* Serial Peripheral Interface 1 */ | |
34 | #define ATMEL_ID_UART0 15 /* UART 0 */ | |
35 | #define ATMEL_ID_UART1 16 /* UART 1 */ | |
36 | #define ATMEL_ID_TC01 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */ | |
37 | #define ATMEL_ID_PWM 18 /* Pulse Width Modulation Controller */ | |
38 | #define ATMEL_ID_ADC 19 /* ADC Controller */ | |
39 | #define ATMEL_ID_DMAC0 20 /* DMA Controller 0 */ | |
40 | #define ATMEL_ID_DMAC1 21 /* DMA Controller 1 */ | |
41 | #define ATMEL_ID_UHPHS 22 /* USB Host High Speed */ | |
42 | #define ATMEL_ID_UDPHS 23 /* USB Device High Speed */ | |
43 | #define ATMEL_ID_EMAC0 24 /* Ethernet MAC0 */ | |
44 | #define ATMEL_ID_LCDC 25 /* LCD Controller */ | |
45 | #define ATMEL_ID_HSMCI1 26 /* High Speed Multimedia Card Interface 1 */ | |
46 | #define ATMEL_ID_EMAC1 27 /* Ethernet MAC1 */ | |
47 | #define ATMEL_ID_SSC 28 /* Synchronous Serial Controller */ | |
e542377a | 48 | #define ATMEL_ID_TRNG 30 /* True Random Number Generator */ |
f7fa2f37 BS |
49 | #define ATMEL_ID_IRQ 31 /* Advanced Interrupt Controller */ |
50 | ||
51 | /* | |
52 | * User Peripheral physical base addresses. | |
53 | */ | |
54 | #define ATMEL_BASE_SPI0 0xf0000000 | |
55 | #define ATMEL_BASE_SPI1 0xf0004000 | |
56 | #define ATMEL_BASE_HSMCI0 0xf0008000 | |
57 | #define ATMEL_BASE_HSMCI1 0xf000c000 | |
58 | #define ATMEL_BASE_SSC 0xf0010000 | |
59 | #define ATMEL_BASE_CAN0 0xf8000000 | |
60 | #define ATMEL_BASE_CAN1 0xf8004000 | |
61 | #define ATMEL_BASE_TC0 0xf8008000 | |
62 | #define ATMEL_BASE_TC1 0xf8008040 | |
63 | #define ATMEL_BASE_TC2 0xf8008080 | |
64 | #define ATMEL_BASE_TC3 0xf800c000 | |
65 | #define ATMEL_BASE_TC4 0xf800c040 | |
66 | #define ATMEL_BASE_TC5 0xf800c080 | |
67 | #define ATMEL_BASE_TWI0 0xf8010000 | |
68 | #define ATMEL_BASE_TWI1 0xf8014000 | |
69 | #define ATMEL_BASE_TWI2 0xf8018000 | |
70 | #define ATMEL_BASE_USART0 0xf801c000 | |
71 | #define ATMEL_BASE_USART1 0xf8020000 | |
72 | #define ATMEL_BASE_USART2 0xf8024000 | |
73 | #define ATMEL_BASE_USART3 0xf8028000 | |
74 | #define ATMEL_BASE_EMAC0 0xf802c000 | |
75 | #define ATMEL_BASE_EMAC1 0xf8030000 | |
76 | #define ATMEL_BASE_PWM 0xf8034000 | |
77 | #define ATMEL_BASE_LCDC 0xf8038000 | |
78 | #define ATMEL_BASE_UDPHS 0xf803c000 | |
79 | #define ATMEL_BASE_UART0 0xf8040000 | |
80 | #define ATMEL_BASE_UART1 0xf8044000 | |
81 | #define ATMEL_BASE_ISI 0xf8048000 | |
82 | #define ATMEL_BASE_ADC 0xf804c000 | |
83 | #define ATMEL_BASE_SYS 0xffffc000 | |
84 | ||
85 | /* | |
86 | * System Peripherals | |
87 | */ | |
e542377a | 88 | #define ATMEL_BASE_FUSE 0xffffdc00 |
f7fa2f37 BS |
89 | #define ATMEL_BASE_MATRIX 0xffffde00 |
90 | #define ATMEL_BASE_PMECC 0xffffe000 | |
91 | #define ATMEL_BASE_PMERRLOC 0xffffe600 | |
92 | #define ATMEL_BASE_DDRSDRC 0xffffe800 | |
93 | #define ATMEL_BASE_SMC 0xffffea00 | |
94 | #define ATMEL_BASE_DMAC0 0xffffec00 | |
95 | #define ATMEL_BASE_DMAC1 0xffffee00 | |
96 | #define ATMEL_BASE_AIC 0xfffff000 | |
97 | #define ATMEL_BASE_DBGU 0xfffff200 | |
98 | #define ATMEL_BASE_PIOA 0xfffff400 | |
99 | #define ATMEL_BASE_PIOB 0xfffff600 | |
100 | #define ATMEL_BASE_PIOC 0xfffff800 | |
101 | #define ATMEL_BASE_PIOD 0xfffffa00 | |
102 | #define ATMEL_BASE_PMC 0xfffffc00 | |
103 | #define ATMEL_BASE_RSTC 0xfffffe00 | |
104 | #define ATMEL_BASE_SHDWC 0xfffffe10 | |
105 | #define ATMEL_BASE_PIT 0xfffffe30 | |
106 | #define ATMEL_BASE_WDT 0xfffffe40 | |
107 | #define ATMEL_BASE_GPBR 0xfffffe60 | |
108 | #define ATMEL_BASE_RTC 0xfffffeb0 | |
109 | ||
110 | /* | |
111 | * Internal Memory. | |
112 | */ | |
113 | #define ATMEL_BASE_ROM 0x00100000 /* Internal ROM base address */ | |
114 | #define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM base address */ | |
e542377a WJ |
115 | |
116 | #ifdef CONFIG_AT91SAM9N12 | |
117 | #define ATMEL_BASE_OHCI 0x00500000 /* USB Host controller */ | |
118 | #else /* AT91SAM9X5 */ | |
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119 | #define ATMEL_BASE_SMD 0x00400000 /* SMD Controller */ |
120 | #define ATMEL_BASE_UDPHS_FIFO 0x00500000 /* USB Device HS controller */ | |
121 | #define ATMEL_BASE_OHCI 0x00600000 /* USB Host controller (OHCI) */ | |
122 | #define ATMEL_BASE_EHCI 0x00700000 /* USB Host controller (EHCI) */ | |
e542377a | 123 | #endif |
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124 | |
125 | /* 9x5 series chip id definitions */ | |
126 | #define ARCH_ID_AT91SAM9X5 0x819a05a0 | |
127 | #define ARCH_ID_VERSION_MASK 0x1f | |
128 | #define ARCH_EXID_AT91SAM9G15 0x00000000 | |
129 | #define ARCH_EXID_AT91SAM9G35 0x00000001 | |
130 | #define ARCH_EXID_AT91SAM9X35 0x00000002 | |
131 | #define ARCH_EXID_AT91SAM9G25 0x00000003 | |
132 | #define ARCH_EXID_AT91SAM9X25 0x00000004 | |
133 | ||
134 | #define cpu_is_at91sam9x5() (get_chip_id() == ARCH_ID_AT91SAM9X5) | |
135 | #define cpu_is_at91sam9g15() (cpu_is_at91sam9x5() && \ | |
136 | (get_extension_chip_id() == ARCH_EXID_AT91SAM9G15)) | |
137 | #define cpu_is_at91sam9g25() (cpu_is_at91sam9x5() && \ | |
138 | (get_extension_chip_id() == ARCH_EXID_AT91SAM9G25)) | |
139 | #define cpu_is_at91sam9g35() (cpu_is_at91sam9x5() && \ | |
140 | (get_extension_chip_id() == ARCH_EXID_AT91SAM9G35)) | |
141 | #define cpu_is_at91sam9x25() (cpu_is_at91sam9x5() && \ | |
142 | (get_extension_chip_id() == ARCH_EXID_AT91SAM9X25)) | |
143 | #define cpu_is_at91sam9x35() (cpu_is_at91sam9x5() && \ | |
144 | (get_extension_chip_id() == ARCH_EXID_AT91SAM9X35)) | |
145 | ||
146 | /* | |
147 | * Cpu Name | |
148 | */ | |
e542377a WJ |
149 | #ifdef CONFIG_AT91SAM9N12 |
150 | #define ATMEL_CPU_NAME "AT91SAM9N12" | |
151 | #else /* AT91SAM9X5 */ | |
f7fa2f37 | 152 | #define ATMEL_CPU_NAME get_cpu_name() |
e542377a | 153 | #endif |
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154 | |
155 | /* | |
156 | * Other misc defines | |
157 | */ | |
158 | #define ATMEL_PIO_PORTS 4 | |
159 | #define CPU_HAS_PIO3 | |
160 | #define PIO_SCDR_DIV (0x3fff << 0) /* Slow Clock Divider Mask */ | |
bcfc8976 RG |
161 | #define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP |
162 | #define ATMEL_ID_UHP ATMEL_ID_UHPHS | |
f7fa2f37 | 163 | |
b2d96dc2 WJ |
164 | /* |
165 | * PMECC table in ROM | |
166 | */ | |
167 | #define ATMEL_PMECC_INDEX_OFFSET_512 0x8000 | |
168 | #define ATMEL_PMECC_INDEX_OFFSET_1024 0x10000 | |
169 | ||
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170 | /* |
171 | * at91sam9x5 specific prototypes | |
172 | */ | |
173 | #ifndef __ASSEMBLY__ | |
174 | unsigned int get_chip_id(void); | |
175 | unsigned int get_extension_chip_id(void); | |
176 | unsigned int has_emac1(void); | |
177 | unsigned int has_emac0(void); | |
178 | unsigned int has_lcdc(void); | |
179 | char *get_cpu_name(void); | |
180 | #endif | |
181 | ||
182 | #endif |