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fa506a92 SP |
1 | /* |
2 | * (C) Copyright 2007 | |
c9e798d3 | 3 | * Stelian Pop <stelian@popies.net> |
fa506a92 | 4 | * Lead Tech Design <www.leadtechdesign.com> |
dc39ae95 | 5 | * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
fa506a92 | 6 | * |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
fa506a92 SP |
8 | */ |
9 | #ifndef __ASM_ARM_ARCH_CLK_H__ | |
10 | #define __ASM_ARM_ARCH_CLK_H__ | |
11 | ||
12 | #include <asm/arch/hardware.h> | |
c3a383f5 | 13 | #include <asm/global_data.h> |
fa506a92 | 14 | |
c3a383f5 AB |
15 | static inline unsigned long get_cpu_clk_rate(void) |
16 | { | |
17 | DECLARE_GLOBAL_DATA_PTR; | |
f47e6ecd | 18 | return gd->arch.cpu_clk_rate_hz; |
c3a383f5 AB |
19 | } |
20 | ||
21 | static inline unsigned long get_main_clk_rate(void) | |
22 | { | |
23 | DECLARE_GLOBAL_DATA_PTR; | |
f47e6ecd | 24 | return gd->arch.main_clk_rate_hz; |
c3a383f5 AB |
25 | } |
26 | ||
27 | static inline unsigned long get_mck_clk_rate(void) | |
28 | { | |
29 | DECLARE_GLOBAL_DATA_PTR; | |
f47e6ecd | 30 | return gd->arch.mck_rate_hz; |
c3a383f5 AB |
31 | } |
32 | ||
33 | static inline unsigned long get_plla_clk_rate(void) | |
34 | { | |
35 | DECLARE_GLOBAL_DATA_PTR; | |
f47e6ecd | 36 | return gd->arch.plla_rate_hz; |
c3a383f5 AB |
37 | } |
38 | ||
39 | static inline unsigned long get_pllb_clk_rate(void) | |
40 | { | |
41 | DECLARE_GLOBAL_DATA_PTR; | |
f47e6ecd | 42 | return gd->arch.pllb_rate_hz; |
c3a383f5 AB |
43 | } |
44 | ||
45 | static inline u32 get_pllb_init(void) | |
46 | { | |
47 | DECLARE_GLOBAL_DATA_PTR; | |
f47e6ecd | 48 | return gd->arch.at91_pllb_usb_init; |
c3a383f5 | 49 | } |
dc39ae95 | 50 | |
fa506a92 SP |
51 | static inline unsigned long get_macb_pclk_rate(unsigned int dev_id) |
52 | { | |
dc39ae95 | 53 | return get_mck_clk_rate(); |
fa506a92 SP |
54 | } |
55 | ||
56 | static inline unsigned long get_usart_clk_rate(unsigned int dev_id) | |
57 | { | |
dc39ae95 | 58 | return get_mck_clk_rate(); |
fa506a92 SP |
59 | } |
60 | ||
39cf4804 SP |
61 | static inline unsigned long get_lcdc_clk_rate(unsigned int dev_id) |
62 | { | |
dc39ae95 | 63 | return get_mck_clk_rate(); |
39cf4804 SP |
64 | } |
65 | ||
22ee6473 SG |
66 | static inline unsigned long get_spi_clk_rate(unsigned int dev_id) |
67 | { | |
68 | return get_mck_clk_rate(); | |
69 | } | |
70 | ||
dc39ae95 JCPV |
71 | static inline unsigned long get_twi_clk_rate(unsigned int dev_id) |
72 | { | |
73 | return get_mck_clk_rate(); | |
74 | } | |
39cf4804 | 75 | |
1592ef85 RM |
76 | static inline unsigned long get_mci_clk_rate(void) |
77 | { | |
78 | return get_mck_clk_rate(); | |
79 | } | |
80 | ||
dc39ae95 | 81 | int at91_clock_init(unsigned long main_clock); |
3225f34e | 82 | void at91_periph_clk_enable(int id); |
fa506a92 | 83 | #endif /* __ASM_ARM_ARCH_CLK_H__ */ |