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88077280 SW |
1 | /* |
2 | * (C) Copyright 2012 Stephen Warren | |
3 | * | |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
88077280 SW |
5 | */ |
6 | ||
7 | #ifndef _BCM2835_MBOX_H | |
8 | #define _BCM2835_MBOX_H | |
9 | ||
10 | #include <linux/compiler.h> | |
11 | ||
12 | /* | |
13 | * The BCM2835 SoC contains (at least) two CPUs; the VideoCore (a/k/a "GPU") | |
14 | * and the ARM CPU. The ARM CPU is often thought of as the main CPU. | |
15 | * However, the VideoCore actually controls the initial SoC boot, and hides | |
16 | * much of the hardware behind a protocol. This protocol is transported | |
17 | * using the SoC's mailbox hardware module. | |
18 | * | |
19 | * The mailbox hardware supports passing 32-bit values back and forth. | |
20 | * Presumably by software convention of the firmware, the bottom 4 bits of the | |
21 | * value are used to indicate a logical channel, and the upper 28 bits are the | |
22 | * actual payload. Various channels exist using these simple raw messages. See | |
23 | * https://github.com/raspberrypi/firmware/wiki/Mailboxes for a list. As an | |
24 | * example, the messages on the power management channel are a bitmask of | |
25 | * devices whose power should be enabled. | |
26 | * | |
27 | * The property mailbox channel passes messages that contain the (16-byte | |
28 | * aligned) ARM physical address of a memory buffer. This buffer is passed to | |
29 | * the VC for processing, is modified in-place by the VC, and the address then | |
30 | * passed back to the ARM CPU as the response mailbox message to indicate | |
31 | * request completion. The buffers have a generic and extensible format; each | |
32 | * buffer contains a standard header, a list of "tags", and a terminating zero | |
33 | * entry. Each tag contains an ID indicating its type, and length fields for | |
34 | * generic parsing. With some limitations, an arbitrary set of tags may be | |
35 | * combined together into a single message buffer. This file defines structs | |
36 | * representing the header and many individual tag layouts and IDs. | |
37 | */ | |
38 | ||
39 | /* Raw mailbox HW */ | |
40 | ||
41 | #define BCM2835_MBOX_PHYSADDR 0x2000b880 | |
42 | ||
43 | struct bcm2835_mbox_regs { | |
44 | u32 read; | |
45 | u32 rsvd0[5]; | |
46 | u32 status; | |
47 | u32 config; | |
48 | u32 write; | |
49 | }; | |
50 | ||
51 | #define BCM2835_MBOX_STATUS_WR_FULL 0x80000000 | |
52 | #define BCM2835_MBOX_STATUS_RD_EMPTY 0x40000000 | |
53 | ||
54 | /* Lower 4-bits are channel ID */ | |
55 | #define BCM2835_CHAN_MASK 0xf | |
56 | #define BCM2835_MBOX_PACK(chan, data) (((data) & (~BCM2835_CHAN_MASK)) | \ | |
57 | (chan & BCM2835_CHAN_MASK)) | |
58 | #define BCM2835_MBOX_UNPACK_CHAN(val) ((val) & BCM2835_CHAN_MASK) | |
59 | #define BCM2835_MBOX_UNPACK_DATA(val) ((val) & (~BCM2835_CHAN_MASK)) | |
60 | ||
61 | /* Property mailbox buffer structures */ | |
62 | ||
63 | #define BCM2835_MBOX_PROP_CHAN 8 | |
64 | ||
65 | /* All message buffers must start with this header */ | |
66 | struct bcm2835_mbox_hdr { | |
67 | u32 buf_size; | |
68 | u32 code; | |
69 | }; | |
70 | ||
71 | #define BCM2835_MBOX_REQ_CODE 0 | |
72 | #define BCM2835_MBOX_RESP_CODE_SUCCESS 0x80000000 | |
73 | ||
74 | #define BCM2835_MBOX_INIT_HDR(_m_) { \ | |
75 | memset((_m_), 0, sizeof(*(_m_))); \ | |
76 | (_m_)->hdr.buf_size = sizeof(*(_m_)); \ | |
77 | (_m_)->hdr.code = 0; \ | |
78 | (_m_)->end_tag = 0; \ | |
79 | } | |
80 | ||
81 | /* | |
82 | * A message buffer contains a list of tags. Each tag must also start with | |
83 | * a standardized header. | |
84 | */ | |
85 | struct bcm2835_mbox_tag_hdr { | |
86 | u32 tag; | |
87 | u32 val_buf_size; | |
88 | u32 val_len; | |
89 | }; | |
90 | ||
91 | #define BCM2835_MBOX_INIT_TAG(_t_, _id_) { \ | |
92 | (_t_)->tag_hdr.tag = BCM2835_MBOX_TAG_##_id_; \ | |
93 | (_t_)->tag_hdr.val_buf_size = sizeof((_t_)->body); \ | |
94 | (_t_)->tag_hdr.val_len = sizeof((_t_)->body.req); \ | |
95 | } | |
96 | ||
97 | #define BCM2835_MBOX_INIT_TAG_NO_REQ(_t_, _id_) { \ | |
98 | (_t_)->tag_hdr.tag = BCM2835_MBOX_TAG_##_id_; \ | |
99 | (_t_)->tag_hdr.val_buf_size = sizeof((_t_)->body); \ | |
100 | (_t_)->tag_hdr.val_len = 0; \ | |
101 | } | |
102 | ||
103 | /* When responding, the VC sets this bit in val_len to indicate a response */ | |
104 | #define BCM2835_MBOX_TAG_VAL_LEN_RESPONSE 0x80000000 | |
105 | ||
106 | /* | |
107 | * Below we define the ID and struct for many possible tags. This header only | |
108 | * defines individual tag structs, not entire message structs, since in | |
109 | * general an arbitrary set of tags may be combined into a single message. | |
110 | * Clients of the mbox API are expected to define their own overall message | |
111 | * structures by combining the header, a set of tags, and a terminating | |
112 | * entry. For example, | |
113 | * | |
114 | * struct msg { | |
115 | * struct bcm2835_mbox_hdr hdr; | |
116 | * struct bcm2835_mbox_tag_get_arm_mem get_arm_mem; | |
117 | * ... perhaps other tags here ... | |
118 | * u32 end_tag; | |
119 | * }; | |
120 | */ | |
121 | ||
4f80a06d SW |
122 | #define BCM2835_MBOX_TAG_GET_MAC_ADDRESS 0x00010003 |
123 | ||
124 | struct bcm2835_mbox_tag_get_mac_address { | |
125 | struct bcm2835_mbox_tag_hdr tag_hdr; | |
126 | union { | |
127 | struct { | |
128 | } req; | |
129 | struct { | |
130 | u8 mac[6]; | |
131 | u8 pad[2]; | |
132 | } resp; | |
133 | } body; | |
134 | }; | |
135 | ||
88077280 SW |
136 | #define BCM2835_MBOX_TAG_GET_ARM_MEMORY 0x00010005 |
137 | ||
138 | struct bcm2835_mbox_tag_get_arm_mem { | |
139 | struct bcm2835_mbox_tag_hdr tag_hdr; | |
140 | union { | |
141 | struct { | |
142 | } req; | |
143 | struct { | |
144 | u32 mem_base; | |
145 | u32 mem_size; | |
146 | } resp; | |
147 | } body; | |
148 | }; | |
149 | ||
f66f2aa2 SW |
150 | #define BCM2835_MBOX_POWER_DEVID_SDHCI 0 |
151 | #define BCM2835_MBOX_POWER_DEVID_UART0 1 | |
152 | #define BCM2835_MBOX_POWER_DEVID_UART1 2 | |
153 | #define BCM2835_MBOX_POWER_DEVID_USB_HCD 3 | |
154 | #define BCM2835_MBOX_POWER_DEVID_I2C0 4 | |
155 | #define BCM2835_MBOX_POWER_DEVID_I2C1 5 | |
156 | #define BCM2835_MBOX_POWER_DEVID_I2C2 6 | |
157 | #define BCM2835_MBOX_POWER_DEVID_SPI 7 | |
158 | #define BCM2835_MBOX_POWER_DEVID_CCP2TX 8 | |
159 | ||
5e77a745 | 160 | #define BCM2835_MBOX_POWER_STATE_RESP_ON (1 << 0) |
f66f2aa2 SW |
161 | /* Device doesn't exist */ |
162 | #define BCM2835_MBOX_POWER_STATE_RESP_NODEV (1 << 1) | |
163 | ||
164 | #define BCM2835_MBOX_TAG_GET_POWER_STATE 0x00020001 | |
165 | ||
166 | struct bcm2835_mbox_tag_get_power_state { | |
167 | struct bcm2835_mbox_tag_hdr tag_hdr; | |
168 | union { | |
169 | struct { | |
170 | u32 device_id; | |
171 | } req; | |
172 | struct { | |
173 | u32 device_id; | |
174 | u32 state; | |
175 | } resp; | |
176 | } body; | |
177 | }; | |
178 | ||
179 | #define BCM2835_MBOX_TAG_SET_POWER_STATE 0x00028001 | |
180 | ||
181 | #define BCM2835_MBOX_SET_POWER_STATE_REQ_ON (1 << 0) | |
182 | #define BCM2835_MBOX_SET_POWER_STATE_REQ_WAIT (1 << 1) | |
183 | ||
184 | struct bcm2835_mbox_tag_set_power_state { | |
185 | struct bcm2835_mbox_tag_hdr tag_hdr; | |
186 | union { | |
187 | struct { | |
188 | u32 device_id; | |
189 | u32 state; | |
190 | } req; | |
191 | struct { | |
192 | u32 device_id; | |
193 | u32 state; | |
194 | } resp; | |
195 | } body; | |
196 | }; | |
197 | ||
131a1e60 SW |
198 | #define BCM2835_MBOX_TAG_GET_CLOCK_RATE 0x00030002 |
199 | ||
200 | #define BCM2835_MBOX_CLOCK_ID_EMMC 1 | |
201 | #define BCM2835_MBOX_CLOCK_ID_UART 2 | |
202 | #define BCM2835_MBOX_CLOCK_ID_ARM 3 | |
203 | #define BCM2835_MBOX_CLOCK_ID_CORE 4 | |
204 | #define BCM2835_MBOX_CLOCK_ID_V3D 5 | |
205 | #define BCM2835_MBOX_CLOCK_ID_H264 6 | |
206 | #define BCM2835_MBOX_CLOCK_ID_ISP 7 | |
207 | #define BCM2835_MBOX_CLOCK_ID_SDRAM 8 | |
208 | #define BCM2835_MBOX_CLOCK_ID_PIXEL 9 | |
209 | #define BCM2835_MBOX_CLOCK_ID_PWM 10 | |
210 | ||
211 | struct bcm2835_mbox_tag_get_clock_rate { | |
212 | struct bcm2835_mbox_tag_hdr tag_hdr; | |
213 | union { | |
214 | struct { | |
215 | u32 clock_id; | |
216 | } req; | |
217 | struct { | |
218 | u32 clock_id; | |
219 | u32 rate_hz; | |
220 | } resp; | |
221 | } body; | |
222 | }; | |
223 | ||
88077280 SW |
224 | #define BCM2835_MBOX_TAG_ALLOCATE_BUFFER 0x00040001 |
225 | ||
226 | struct bcm2835_mbox_tag_allocate_buffer { | |
227 | struct bcm2835_mbox_tag_hdr tag_hdr; | |
228 | union { | |
229 | struct { | |
230 | u32 alignment; | |
231 | } req; | |
232 | struct { | |
233 | u32 fb_address; | |
234 | u32 fb_size; | |
235 | } resp; | |
236 | } body; | |
237 | }; | |
238 | ||
239 | #define BCM2835_MBOX_TAG_RELEASE_BUFFER 0x00048001 | |
240 | ||
241 | struct bcm2835_mbox_tag_release_buffer { | |
242 | struct bcm2835_mbox_tag_hdr tag_hdr; | |
243 | union { | |
244 | struct { | |
245 | } req; | |
246 | struct { | |
247 | } resp; | |
248 | } body; | |
249 | }; | |
250 | ||
251 | #define BCM2835_MBOX_TAG_BLANK_SCREEN 0x00040002 | |
252 | ||
253 | struct bcm2835_mbox_tag_blank_screen { | |
254 | struct bcm2835_mbox_tag_hdr tag_hdr; | |
255 | union { | |
256 | struct { | |
257 | /* bit 0 means on, other bots reserved */ | |
258 | u32 state; | |
259 | } req; | |
260 | struct { | |
261 | u32 state; | |
262 | } resp; | |
263 | } body; | |
264 | }; | |
265 | ||
266 | /* Physical means output signal */ | |
267 | #define BCM2835_MBOX_TAG_GET_PHYSICAL_W_H 0x00040003 | |
268 | #define BCM2835_MBOX_TAG_TEST_PHYSICAL_W_H 0x00044003 | |
269 | #define BCM2835_MBOX_TAG_SET_PHYSICAL_W_H 0x00048003 | |
270 | ||
271 | struct bcm2835_mbox_tag_physical_w_h { | |
272 | struct bcm2835_mbox_tag_hdr tag_hdr; | |
273 | union { | |
274 | /* req not used for get */ | |
275 | struct { | |
276 | u32 width; | |
277 | u32 height; | |
278 | } req; | |
279 | struct { | |
280 | u32 width; | |
281 | u32 height; | |
282 | } resp; | |
283 | } body; | |
284 | }; | |
285 | ||
286 | /* Virtual means display buffer */ | |
287 | #define BCM2835_MBOX_TAG_GET_VIRTUAL_W_H 0x00040004 | |
288 | #define BCM2835_MBOX_TAG_TEST_VIRTUAL_W_H 0x00044004 | |
289 | #define BCM2835_MBOX_TAG_SET_VIRTUAL_W_H 0x00048004 | |
290 | ||
291 | struct bcm2835_mbox_tag_virtual_w_h { | |
292 | struct bcm2835_mbox_tag_hdr tag_hdr; | |
293 | union { | |
294 | /* req not used for get */ | |
295 | struct { | |
296 | u32 width; | |
297 | u32 height; | |
298 | } req; | |
299 | struct { | |
300 | u32 width; | |
301 | u32 height; | |
302 | } resp; | |
303 | } body; | |
304 | }; | |
305 | ||
306 | #define BCM2835_MBOX_TAG_GET_DEPTH 0x00040005 | |
307 | #define BCM2835_MBOX_TAG_TEST_DEPTH 0x00044005 | |
308 | #define BCM2835_MBOX_TAG_SET_DEPTH 0x00048005 | |
309 | ||
310 | struct bcm2835_mbox_tag_depth { | |
311 | struct bcm2835_mbox_tag_hdr tag_hdr; | |
312 | union { | |
313 | /* req not used for get */ | |
314 | struct { | |
315 | u32 bpp; | |
316 | } req; | |
317 | struct { | |
318 | u32 bpp; | |
319 | } resp; | |
320 | } body; | |
321 | }; | |
322 | ||
323 | #define BCM2835_MBOX_TAG_GET_PIXEL_ORDER 0x00040006 | |
324 | #define BCM2835_MBOX_TAG_TEST_PIXEL_ORDER 0x00044005 | |
325 | #define BCM2835_MBOX_TAG_SET_PIXEL_ORDER 0x00048006 | |
326 | ||
327 | #define BCM2835_MBOX_PIXEL_ORDER_BGR 0 | |
328 | #define BCM2835_MBOX_PIXEL_ORDER_RGB 1 | |
329 | ||
330 | struct bcm2835_mbox_tag_pixel_order { | |
331 | struct bcm2835_mbox_tag_hdr tag_hdr; | |
332 | union { | |
333 | /* req not used for get */ | |
334 | struct { | |
335 | u32 order; | |
336 | } req; | |
337 | struct { | |
338 | u32 order; | |
339 | } resp; | |
340 | } body; | |
341 | }; | |
342 | ||
343 | #define BCM2835_MBOX_TAG_GET_ALPHA_MODE 0x00040007 | |
344 | #define BCM2835_MBOX_TAG_TEST_ALPHA_MODE 0x00044007 | |
345 | #define BCM2835_MBOX_TAG_SET_ALPHA_MODE 0x00048007 | |
346 | ||
347 | #define BCM2835_MBOX_ALPHA_MODE_0_OPAQUE 0 | |
348 | #define BCM2835_MBOX_ALPHA_MODE_0_TRANSPARENT 1 | |
349 | #define BCM2835_MBOX_ALPHA_MODE_IGNORED 2 | |
350 | ||
351 | struct bcm2835_mbox_tag_alpha_mode { | |
352 | struct bcm2835_mbox_tag_hdr tag_hdr; | |
353 | union { | |
354 | /* req not used for get */ | |
355 | struct { | |
356 | u32 alpha; | |
357 | } req; | |
358 | struct { | |
359 | u32 alpha; | |
360 | } resp; | |
361 | } body; | |
362 | }; | |
363 | ||
364 | #define BCM2835_MBOX_TAG_GET_PITCH 0x00040008 | |
365 | ||
366 | struct bcm2835_mbox_tag_pitch { | |
367 | struct bcm2835_mbox_tag_hdr tag_hdr; | |
368 | union { | |
369 | struct { | |
370 | } req; | |
371 | struct { | |
372 | u32 pitch; | |
373 | } resp; | |
374 | } body; | |
375 | }; | |
376 | ||
377 | /* Offset of display window within buffer */ | |
378 | #define BCM2835_MBOX_TAG_GET_VIRTUAL_OFFSET 0x00040009 | |
379 | #define BCM2835_MBOX_TAG_TEST_VIRTUAL_OFFSET 0x00044009 | |
380 | #define BCM2835_MBOX_TAG_SET_VIRTUAL_OFFSET 0x00048009 | |
381 | ||
382 | struct bcm2835_mbox_tag_virtual_offset { | |
383 | struct bcm2835_mbox_tag_hdr tag_hdr; | |
384 | union { | |
385 | /* req not used for get */ | |
386 | struct { | |
387 | u32 x; | |
388 | u32 y; | |
389 | } req; | |
390 | struct { | |
391 | u32 x; | |
392 | u32 y; | |
393 | } resp; | |
394 | } body; | |
395 | }; | |
396 | ||
397 | #define BCM2835_MBOX_TAG_GET_OVERSCAN 0x0004000a | |
398 | #define BCM2835_MBOX_TAG_TEST_OVERSCAN 0x0004400a | |
399 | #define BCM2835_MBOX_TAG_SET_OVERSCAN 0x0004800a | |
400 | ||
401 | struct bcm2835_mbox_tag_overscan { | |
402 | struct bcm2835_mbox_tag_hdr tag_hdr; | |
403 | union { | |
404 | /* req not used for get */ | |
405 | struct { | |
406 | u32 top; | |
407 | u32 bottom; | |
408 | u32 left; | |
409 | u32 right; | |
410 | } req; | |
411 | struct { | |
412 | u32 top; | |
413 | u32 bottom; | |
414 | u32 left; | |
e2788afe | 415 | u32 right; |
88077280 SW |
416 | } resp; |
417 | } body; | |
418 | }; | |
419 | ||
420 | #define BCM2835_MBOX_TAG_GET_PALETTE 0x0004000b | |
421 | ||
422 | struct bcm2835_mbox_tag_get_palette { | |
423 | struct bcm2835_mbox_tag_hdr tag_hdr; | |
424 | union { | |
425 | struct { | |
426 | } req; | |
427 | struct { | |
428 | u32 data[1024]; | |
429 | } resp; | |
430 | } body; | |
431 | }; | |
432 | ||
433 | #define BCM2835_MBOX_TAG_TEST_PALETTE 0x0004400b | |
434 | ||
435 | struct bcm2835_mbox_tag_test_palette { | |
436 | struct bcm2835_mbox_tag_hdr tag_hdr; | |
437 | union { | |
438 | struct { | |
439 | u32 offset; | |
440 | u32 num_entries; | |
441 | u32 data[256]; | |
442 | } req; | |
443 | struct { | |
444 | u32 is_invalid; | |
445 | } resp; | |
446 | } body; | |
447 | }; | |
448 | ||
449 | #define BCM2835_MBOX_TAG_SET_PALETTE 0x0004800b | |
450 | ||
451 | struct bcm2835_mbox_tag_set_palette { | |
452 | struct bcm2835_mbox_tag_hdr tag_hdr; | |
453 | union { | |
454 | struct { | |
455 | u32 offset; | |
456 | u32 num_entries; | |
457 | u32 data[256]; | |
458 | } req; | |
459 | struct { | |
460 | u32 is_invalid; | |
461 | } resp; | |
462 | } body; | |
463 | }; | |
464 | ||
465 | /* | |
466 | * Pass a raw u32 message to the VC, and receive a raw u32 back. | |
467 | * | |
468 | * Returns 0 for success, any other value for error. | |
469 | */ | |
470 | int bcm2835_mbox_call_raw(u32 chan, u32 send, u32 *recv); | |
471 | ||
472 | /* | |
473 | * Pass a complete property-style buffer to the VC, and wait until it has | |
474 | * been processed. | |
475 | * | |
476 | * This function expects a pointer to the mbox_hdr structure in an attempt | |
477 | * to ensure some degree of type safety. However, some number of tags and | |
478 | * a termination value are expected to immediately follow the header in | |
479 | * memory, as required by the property protocol. | |
480 | * | |
481 | * Returns 0 for success, any other value for error. | |
482 | */ | |
483 | int bcm2835_mbox_call_prop(u32 chan, struct bcm2835_mbox_hdr *buffer); | |
484 | ||
485 | #endif |