[people/ms/u-boot.git] / arch / arm / include / asm / arch-davinci / sdmmc_defs.h

/*
 * Davinci MMC Controller Defines - Based on Linux davinci_mmc.c
 *
 * Copyright (C) 2010 Texas Instruments Incorporated
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _SDMMC_DEFS_H_
#define _SDMMC_DEFS_H_

#include <asm/arch/hardware.h>

/* MMC Control Reg fields */
#define MMCCTL_DATRST		(1 << 0)
#define MMCCTL_CMDRST		(1 << 1)
#define MMCCTL_WIDTH_4_BIT	(1 << 2)
#define MMCCTL_DATEG_DISABLED	(0 << 6)
#define MMCCTL_DATEG_RISING	(1 << 6)
#define MMCCTL_DATEG_FALLING	(2 << 6)
#define MMCCTL_DATEG_BOTH	(3 << 6)
#define MMCCTL_PERMDR_LE	(0 << 9)
#define MMCCTL_PERMDR_BE	(1 << 9)
#define MMCCTL_PERMDX_LE	(0 << 10)
#define MMCCTL_PERMDX_BE	(1 << 10)

/* MMC Clock Control Reg fields */
#define MMCCLK_CLKEN		(1 << 8)
#define MMCCLK_CLKRT_MASK	(0xFF << 0)

/* MMC Status Reg0 fields */
#define MMCST0_DATDNE		(1 << 0)
#define MMCST0_BSYDNE		(1 << 1)
#define MMCST0_RSPDNE		(1 << 2)
#define MMCST0_TOUTRD		(1 << 3)
#define MMCST0_TOUTRS		(1 << 4)
#define MMCST0_CRCWR		(1 << 5)
#define MMCST0_CRCRD		(1 << 6)
#define MMCST0_CRCRS		(1 << 7)
#define MMCST0_DXRDY		(1 << 9)
#define MMCST0_DRRDY		(1 << 10)
#define MMCST0_DATED		(1 << 11)
#define MMCST0_TRNDNE		(1 << 12)

#define MMCST0_ERR_MASK		(0x00F8)

/* MMC Status Reg1 fields */
#define MMCST1_BUSY		(1 << 0)
#define MMCST1_CLKSTP		(1 << 1)
#define MMCST1_DXEMP		(1 << 2)
#define MMCST1_DRFUL		(1 << 3)
#define MMCST1_DAT3ST		(1 << 4)
#define MMCST1_FIFOEMP		(1 << 5)
#define MMCST1_FIFOFUL		(1 << 6)

/* MMC INT Mask Reg fields */
#define MMCIM_EDATDNE		(1 << 0)
#define MMCIM_EBSYDNE		(1 << 1)
#define MMCIM_ERSPDNE		(1 << 2)
#define MMCIM_ETOUTRD		(1 << 3)
#define MMCIM_ETOUTRS		(1 << 4)
#define MMCIM_ECRCWR		(1 << 5)
#define MMCIM_ECRCRD		(1 << 6)
#define MMCIM_ECRCRS		(1 << 7)
#define MMCIM_EDXRDY		(1 << 9)
#define MMCIM_EDRRDY		(1 << 10)
#define MMCIM_EDATED		(1 << 11)
#define MMCIM_ETRNDNE		(1 << 12)

#define MMCIM_MASKALL		(0xFFFFFFFF)

/* MMC Resp Tout Reg fields */
#define MMCTOR_TOR_MASK		(0xFF)		/* dont write to reg, | it */
#define MMCTOR_TOD_20_16_SHIFT  (8)

/* MMC Data Read Tout Reg fields */
#define MMCTOD_TOD_0_15_MASK	(0xFFFF)

/* MMC Block len Reg fields */
#define MMCBLEN_BLEN_MASK	(0xFFF)

/* MMC Num Blocks Reg fields */
#define MMCNBLK_NBLK_MASK	(0xFFFF)
#define MMCNBLK_NBLK_MAX	(0xFFFF)

/* MMC Num Blocks Counter Reg fields */
#define MMCNBLC_NBLC_MASK	(0xFFFF)

/* MMC Cmd Reg fields */
#define MMCCMD_CMD_MASK		(0x3F)
#define MMCCMD_PPLEN		(1 << 7)
#define MMCCMD_BSYEXP		(1 << 8)
#define MMCCMD_RSPFMT_NONE	(0 << 9)
#define MMCCMD_RSPFMT_R1567	(1 << 9)
#define MMCCMD_RSPFMT_R2	(2 << 9)
#define MMCCMD_RSPFMT_R3	(3 << 9)
#define MMCCMD_DTRW		(1 << 11)
#define MMCCMD_STRMTP		(1 << 12)
#define MMCCMD_WDATX		(1 << 13)
#define MMCCMD_INITCK		(1 << 14)
#define MMCCMD_DCLR		(1 << 15)
#define MMCCMD_DMATRIG		(1 << 16)

/* FIFO control Reg fields */
#define MMCFIFOCTL_FIFORST	(1 << 0)
#define MMCFIFOCTL_FIFODIR	(1 << 1)
#define MMCFIFOCTL_FIFOLEV	(1 << 2)
#define MMCFIFOCTL_ACCWD_4	(0 << 3)	/* access width of 4 bytes */
#define MMCFIFOCTL_ACCWD_3	(1 << 3)	/* access width of 3 bytes */
#define MMCFIFOCTL_ACCWD_2	(2 << 3)	/* access width of 2 bytes */
#define MMCFIFOCTL_ACCWD_1	(3 << 3)	/* access width of 1 byte */

/* Davinci MMC Register definitions */
struct davinci_mmc_regs {
	dv_reg mmcctl;
	dv_reg mmcclk;
	dv_reg mmcst0;
	dv_reg mmcst1;
	dv_reg mmcim;
	dv_reg mmctor;
	dv_reg mmctod;
	dv_reg mmcblen;
	dv_reg mmcnblk;
	dv_reg mmcnblc;
	dv_reg mmcdrr;
	dv_reg mmcdxr;
	dv_reg mmccmd;
	dv_reg mmcarghl;
	dv_reg mmcrsp01;
	dv_reg mmcrsp23;
	dv_reg mmcrsp45;
	dv_reg mmcrsp67;
	dv_reg mmcdrsp;
	dv_reg mmcetok;
	dv_reg mmccidx;
	dv_reg mmcckc;
	dv_reg mmctorc;
	dv_reg mmctodc;
	dv_reg mmcblnc;
	dv_reg sdioctl;
	dv_reg sdiost0;
	dv_reg sdioien;
	dv_reg sdioist;
	dv_reg mmcfifoctl;
};

/* Davinci MMC board definitions */
struct davinci_mmc {
	struct davinci_mmc_regs *reg_base;	/* Register base address */
	uint input_clk;		/* Input clock to MMC controller */
	uint host_caps;		/* Host capabilities */
	uint voltages;		/* Host supported voltages */
	uint version;		/* MMC Controller version */
	struct mmc_config cfg;
};

enum {
	MMC_CTLR_VERSION_1 = 0,	/* DM644x and DM355 */
	MMC_CTLR_VERSION_2,	/* DA830 */
};

int davinci_mmc_init(bd_t *bis, struct davinci_mmc *host);

#endif /* _SDMMC_DEFS_H */
Commit	Line	Data
57418d21 SP	1	/*
	2	* Davinci MMC Controller Defines - Based on Linux davinci_mmc.c
	3	*
	4	* Copyright (C) 2010 Texas Instruments Incorporated
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
57418d21 SP	7	*/
	8
	9	#ifndef _SDMMC_DEFS_H_
	10	#define _SDMMC_DEFS_H_
	11
	12	#include <asm/arch/hardware.h>
	13
	14	/* MMC Control Reg fields */
	15	#define MMCCTL_DATRST (1 << 0)
	16	#define MMCCTL_CMDRST (1 << 1)
	17	#define MMCCTL_WIDTH_4_BIT (1 << 2)
	18	#define MMCCTL_DATEG_DISABLED (0 << 6)
	19	#define MMCCTL_DATEG_RISING (1 << 6)
	20	#define MMCCTL_DATEG_FALLING (2 << 6)
	21	#define MMCCTL_DATEG_BOTH (3 << 6)
	22	#define MMCCTL_PERMDR_LE (0 << 9)
	23	#define MMCCTL_PERMDR_BE (1 << 9)
	24	#define MMCCTL_PERMDX_LE (0 << 10)
	25	#define MMCCTL_PERMDX_BE (1 << 10)
	26
	27	/* MMC Clock Control Reg fields */
	28	#define MMCCLK_CLKEN (1 << 8)
	29	#define MMCCLK_CLKRT_MASK (0xFF << 0)
	30
	31	/* MMC Status Reg0 fields */
	32	#define MMCST0_DATDNE (1 << 0)
	33	#define MMCST0_BSYDNE (1 << 1)
	34	#define MMCST0_RSPDNE (1 << 2)
	35	#define MMCST0_TOUTRD (1 << 3)
	36	#define MMCST0_TOUTRS (1 << 4)
	37	#define MMCST0_CRCWR (1 << 5)
	38	#define MMCST0_CRCRD (1 << 6)
	39	#define MMCST0_CRCRS (1 << 7)
	40	#define MMCST0_DXRDY (1 << 9)
	41	#define MMCST0_DRRDY (1 << 10)
	42	#define MMCST0_DATED (1 << 11)
	43	#define MMCST0_TRNDNE (1 << 12)
	44
	45	#define MMCST0_ERR_MASK (0x00F8)
	46
	47	/* MMC Status Reg1 fields */
	48	#define MMCST1_BUSY (1 << 0)
	49	#define MMCST1_CLKSTP (1 << 1)
	50	#define MMCST1_DXEMP (1 << 2)
	51	#define MMCST1_DRFUL (1 << 3)
	52	#define MMCST1_DAT3ST (1 << 4)
	53	#define MMCST1_FIFOEMP (1 << 5)
	54	#define MMCST1_FIFOFUL (1 << 6)
	55
	56	/* MMC INT Mask Reg fields */
	57	#define MMCIM_EDATDNE (1 << 0)
	58	#define MMCIM_EBSYDNE (1 << 1)
	59	#define MMCIM_ERSPDNE (1 << 2)
	60	#define MMCIM_ETOUTRD (1 << 3)
	61	#define MMCIM_ETOUTRS (1 << 4)
	62	#define MMCIM_ECRCWR (1 << 5)
	63	#define MMCIM_ECRCRD (1 << 6)
	64	#define MMCIM_ECRCRS (1 << 7)
	65	#define MMCIM_EDXRDY (1 << 9)
	66	#define MMCIM_EDRRDY (1 << 10)
	67	#define MMCIM_EDATED (1 << 11)
	68	#define MMCIM_ETRNDNE (1 << 12)
	69
	70	#define MMCIM_MASKALL (0xFFFFFFFF)
71
72	/* MMC Resp Tout Reg fields */
73	#define MMCTOR_TOR_MASK (0xFF) /* dont write to reg, \| it */
74	#define MMCTOR_TOD_20_16_SHIFT (8)
75
76	/* MMC Data Read Tout Reg fields */
77	#define MMCTOD_TOD_0_15_MASK (0xFFFF)
78
79	/* MMC Block len Reg fields */
80	#define MMCBLEN_BLEN_MASK (0xFFF)
81
82	/* MMC Num Blocks Reg fields */
83	#define MMCNBLK_NBLK_MASK (0xFFFF)
84	#define MMCNBLK_NBLK_MAX (0xFFFF)
85
86	/* MMC Num Blocks Counter Reg fields */
87	#define MMCNBLC_NBLC_MASK (0xFFFF)
88
89	/* MMC Cmd Reg fields */
90	#define MMCCMD_CMD_MASK (0x3F)
91	#define MMCCMD_PPLEN (1 << 7)
92	#define MMCCMD_BSYEXP (1 << 8)
93	#define MMCCMD_RSPFMT_NONE (0 << 9)
94	#define MMCCMD_RSPFMT_R1567 (1 << 9)
95	#define MMCCMD_RSPFMT_R2 (2 << 9)
96	#define MMCCMD_RSPFMT_R3 (3 << 9)
97	#define MMCCMD_DTRW (1 << 11)
98	#define MMCCMD_STRMTP (1 << 12)
99	#define MMCCMD_WDATX (1 << 13)
100	#define MMCCMD_INITCK (1 << 14)
101	#define MMCCMD_DCLR (1 << 15)
102	#define MMCCMD_DMATRIG (1 << 16)
103
104	/* FIFO control Reg fields */
105	#define MMCFIFOCTL_FIFORST (1 << 0)
106	#define MMCFIFOCTL_FIFODIR (1 << 1)
107	#define MMCFIFOCTL_FIFOLEV (1 << 2)
108	#define MMCFIFOCTL_ACCWD_4 (0 << 3) /* access width of 4 bytes */
109	#define MMCFIFOCTL_ACCWD_3 (1 << 3) /* access width of 3 bytes */
110	#define MMCFIFOCTL_ACCWD_2 (2 << 3) /* access width of 2 bytes */
111	#define MMCFIFOCTL_ACCWD_1 (3 << 3) /* access width of 1 byte */
112
113	/* Davinci MMC Register definitions */
114	struct davinci_mmc_regs {
115	dv_reg mmcctl;
116	dv_reg mmcclk;
117	dv_reg mmcst0;
118	dv_reg mmcst1;
119	dv_reg mmcim;
120	dv_reg mmctor;
121	dv_reg mmctod;
122	dv_reg mmcblen;
123	dv_reg mmcnblk;
124	dv_reg mmcnblc;
125	dv_reg mmcdrr;
126	dv_reg mmcdxr;
127	dv_reg mmccmd;
128	dv_reg mmcarghl;
129	dv_reg mmcrsp01;
130	dv_reg mmcrsp23;
131	dv_reg mmcrsp45;
132	dv_reg mmcrsp67;
133	dv_reg mmcdrsp;
134	dv_reg mmcetok;
135	dv_reg mmccidx;
136	dv_reg mmcckc;
137	dv_reg mmctorc;
138	dv_reg mmctodc;
139	dv_reg mmcblnc;
140	dv_reg sdioctl;
141	dv_reg sdiost0;
142	dv_reg sdioien;
143	dv_reg sdioist;
144	dv_reg mmcfifoctl;
145	};
146
147	/* Davinci MMC board definitions */
148	struct davinci_mmc {
149	struct davinci_mmc_regs reg_base; / Register base address */
150	uint input_clk; /* Input clock to MMC controller */
151	uint host_caps; /* Host capabilities */
152	uint voltages; /* Host supported voltages */
153	uint version; /* MMC Controller version */
93bfd616	154	struct mmc_config cfg;
57418d21 SP	155	};
	156
	157	enum {
	158	MMC_CTLR_VERSION_1 = 0, /* DM644x and DM355 */
	159	MMC_CTLR_VERSION_2, /* DA830 */
	160	};
	161
	162	int davinci_mmc_init(bd_t bis, struct davinci_mmc host);
	163
	164	#endif /* _SDMMC_DEFS_H */