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Commit | Line | Data |
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008a351a MK |
1 | /* |
2 | * (C) Copyright 2010 Samsung Electronics | |
3 | * Minkyu Kang <mk7.kang@samsung.com> | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
008a351a MK |
6 | */ |
7 | ||
393cb361 CK |
8 | #ifndef _EXYNOS4_CPU_H |
9 | #define _EXYNOS4_CPU_H | |
008a351a | 10 | |
37bb6d89 CK |
11 | #define DEVICE_NOT_AVAILABLE 0 |
12 | ||
7775831d | 13 | #define EXYNOS_CPU_NAME "Exynos" |
393cb361 | 14 | #define EXYNOS4_ADDR_BASE 0x10000000 |
008a351a | 15 | |
b189a83a | 16 | /* EXYNOS4 Common*/ |
847ab8f6 PW |
17 | #define EXYNOS4_I2C_SPACING 0x10000 |
18 | ||
393cb361 CK |
19 | #define EXYNOS4_GPIO_PART3_BASE 0x03860000 |
20 | #define EXYNOS4_PRO_ID 0x10000000 | |
283591f1 | 21 | #define EXYNOS4_SYSREG_BASE 0x10010000 |
393cb361 CK |
22 | #define EXYNOS4_POWER_BASE 0x10020000 |
23 | #define EXYNOS4_SWRESET 0x10020400 | |
24 | #define EXYNOS4_CLOCK_BASE 0x10030000 | |
25 | #define EXYNOS4_SYSTIMER_BASE 0x10050000 | |
26 | #define EXYNOS4_WATCHDOG_BASE 0x10060000 | |
b5f9756f | 27 | #define EXYNOS4_TZPC_BASE 0x10110000 |
393cb361 | 28 | #define EXYNOS4_MIU_BASE 0x10600000 |
643be9c0 | 29 | #define EXYNOS4_DMC_CTRL_BASE 0x10400000 |
393cb361 CK |
30 | #define EXYNOS4_GPIO_PART2_BASE 0x11000000 |
31 | #define EXYNOS4_GPIO_PART1_BASE 0x11400000 | |
32 | #define EXYNOS4_FIMD_BASE 0x11C00000 | |
283591f1 | 33 | #define EXYNOS4_MIPI_DSIM_BASE 0x11C80000 |
393cb361 CK |
34 | #define EXYNOS4_USBOTG_BASE 0x12480000 |
35 | #define EXYNOS4_MMC_BASE 0x12510000 | |
36 | #define EXYNOS4_SROMC_BASE 0x12570000 | |
7590d3ce | 37 | #define EXYNOS4_USB_HOST_EHCI_BASE 0x12580000 |
393cb361 CK |
38 | #define EXYNOS4_USBPHY_BASE 0x125B0000 |
39 | #define EXYNOS4_UART_BASE 0x13800000 | |
1a758aec | 40 | #define EXYNOS4_I2C_BASE 0x13860000 |
393cb361 | 41 | #define EXYNOS4_ADC_BASE 0x13910000 |
383b5cc5 | 42 | #define EXYNOS4_SPI_BASE 0x13920000 |
393cb361 CK |
43 | #define EXYNOS4_PWMTIMER_BASE 0x139D0000 |
44 | #define EXYNOS4_MODEM_BASE 0x13A00000 | |
37bb6d89 | 45 | #define EXYNOS4_USBPHY_CONTROL 0x10020704 |
87fa491a | 46 | #define EXYNOS4_I2S_BASE 0xE2100000 |
37bb6d89 CK |
47 | |
48 | #define EXYNOS4_GPIO_PART4_BASE DEVICE_NOT_AVAILABLE | |
c4015050 | 49 | #define EXYNOS4_DP_BASE DEVICE_NOT_AVAILABLE |
383b5cc5 | 50 | #define EXYNOS4_SPI_ISP_BASE DEVICE_NOT_AVAILABLE |
acbb1eb7 | 51 | #define EXYNOS4_ACE_SFR_BASE DEVICE_NOT_AVAILABLE |
643be9c0 | 52 | #define EXYNOS4_DMC_PHY_BASE DEVICE_NOT_AVAILABLE |
37bb6d89 | 53 | |
b189a83a CK |
54 | /* EXYNOS4X12 */ |
55 | #define EXYNOS4X12_GPIO_PART3_BASE 0x03860000 | |
56 | #define EXYNOS4X12_PRO_ID 0x10000000 | |
57 | #define EXYNOS4X12_SYSREG_BASE 0x10010000 | |
58 | #define EXYNOS4X12_POWER_BASE 0x10020000 | |
59 | #define EXYNOS4X12_SWRESET 0x10020400 | |
60 | #define EXYNOS4X12_USBPHY_CONTROL 0x10020704 | |
61 | #define EXYNOS4X12_CLOCK_BASE 0x10030000 | |
62 | #define EXYNOS4X12_SYSTIMER_BASE 0x10050000 | |
63 | #define EXYNOS4X12_WATCHDOG_BASE 0x10060000 | |
b5f9756f | 64 | #define EXYNOS4X12_TZPC_BASE 0x10110000 |
643be9c0 | 65 | #define EXYNOS4X12_DMC_CTRL_BASE 0x10600000 |
b189a83a CK |
66 | #define EXYNOS4X12_GPIO_PART4_BASE 0x106E0000 |
67 | #define EXYNOS4X12_GPIO_PART2_BASE 0x11000000 | |
68 | #define EXYNOS4X12_GPIO_PART1_BASE 0x11400000 | |
69 | #define EXYNOS4X12_FIMD_BASE 0x11C00000 | |
70 | #define EXYNOS4X12_MIPI_DSIM_BASE 0x11C80000 | |
71 | #define EXYNOS4X12_USBOTG_BASE 0x12480000 | |
72 | #define EXYNOS4X12_MMC_BASE 0x12510000 | |
73 | #define EXYNOS4X12_SROMC_BASE 0x12570000 | |
74 | #define EXYNOS4X12_USB_HOST_EHCI_BASE 0x12580000 | |
75 | #define EXYNOS4X12_USBPHY_BASE 0x125B0000 | |
76 | #define EXYNOS4X12_UART_BASE 0x13800000 | |
77 | #define EXYNOS4X12_I2C_BASE 0x13860000 | |
78 | #define EXYNOS4X12_PWMTIMER_BASE 0x139D0000 | |
79 | ||
80 | #define EXYNOS4X12_ADC_BASE DEVICE_NOT_AVAILABLE | |
81 | #define EXYNOS4X12_DP_BASE DEVICE_NOT_AVAILABLE | |
82 | #define EXYNOS4X12_MODEM_BASE DEVICE_NOT_AVAILABLE | |
4fdebefa MK |
83 | #define EXYNOS4X12_I2S_BASE DEVICE_NOT_AVAILABLE |
84 | #define EXYNOS4X12_SPI_BASE DEVICE_NOT_AVAILABLE | |
85 | #define EXYNOS4X12_SPI_ISP_BASE DEVICE_NOT_AVAILABLE | |
acbb1eb7 | 86 | #define EXYNOS4X12_ACE_SFR_BASE DEVICE_NOT_AVAILABLE |
643be9c0 | 87 | #define EXYNOS4X12_DMC_PHY_BASE DEVICE_NOT_AVAILABLE |
b189a83a CK |
88 | |
89 | /* EXYNOS5 Common*/ | |
8da3eb1b RS |
90 | #define EXYNOS5_I2C_SPACING 0x10000 |
91 | ||
37bb6d89 CK |
92 | #define EXYNOS5_GPIO_PART4_BASE 0x03860000 |
93 | #define EXYNOS5_PRO_ID 0x10000000 | |
94 | #define EXYNOS5_CLOCK_BASE 0x10010000 | |
95 | #define EXYNOS5_POWER_BASE 0x10040000 | |
96 | #define EXYNOS5_SWRESET 0x10040400 | |
97 | #define EXYNOS5_SYSREG_BASE 0x10050000 | |
b5f9756f | 98 | #define EXYNOS5_TZPC_BASE 0x10100000 |
37bb6d89 | 99 | #define EXYNOS5_WATCHDOG_BASE 0x101D0000 |
acbb1eb7 | 100 | #define EXYNOS5_ACE_SFR_BASE 0x10830000 |
643be9c0 | 101 | #define EXYNOS5_DMC_PHY_BASE 0x10C00000 |
37bb6d89 CK |
102 | #define EXYNOS5_GPIO_PART3_BASE 0x10D10000 |
103 | #define EXYNOS5_DMC_CTRL_BASE 0x10DD0000 | |
104 | #define EXYNOS5_GPIO_PART1_BASE 0x11400000 | |
283591f1 | 105 | #define EXYNOS5_MIPI_DSIM_BASE 0x11D00000 |
7590d3ce | 106 | #define EXYNOS5_USB_HOST_EHCI_BASE 0x12110000 |
86d74d03 RS |
107 | #define EXYNOS5_USBPHY_BASE 0x12130000 |
108 | #define EXYNOS5_USBOTG_BASE 0x12140000 | |
37bb6d89 CK |
109 | #define EXYNOS5_MMC_BASE 0x12200000 |
110 | #define EXYNOS5_SROMC_BASE 0x12250000 | |
37bb6d89 | 111 | #define EXYNOS5_UART_BASE 0x12C00000 |
1a758aec | 112 | #define EXYNOS5_I2C_BASE 0x12C60000 |
383b5cc5 | 113 | #define EXYNOS5_SPI_BASE 0x12D20000 |
87fa491a | 114 | #define EXYNOS5_I2S_BASE 0x12D60000 |
37bb6d89 | 115 | #define EXYNOS5_PWMTIMER_BASE 0x12DD0000 |
383b5cc5 | 116 | #define EXYNOS5_SPI_ISP_BASE 0x131A0000 |
37bb6d89 CK |
117 | #define EXYNOS5_GPIO_PART2_BASE 0x13400000 |
118 | #define EXYNOS5_FIMD_BASE 0x14400000 | |
c4015050 | 119 | #define EXYNOS5_DP_BASE 0x145B0000 |
37bb6d89 CK |
120 | |
121 | #define EXYNOS5_ADC_BASE DEVICE_NOT_AVAILABLE | |
122 | #define EXYNOS5_MODEM_BASE DEVICE_NOT_AVAILABLE | |
008a351a MK |
123 | |
124 | #ifndef __ASSEMBLY__ | |
125 | #include <asm/io.h> | |
126 | /* CPU detection macros */ | |
127 | extern unsigned int s5p_cpu_id; | |
5d845f27 MK |
128 | extern unsigned int s5p_cpu_rev; |
129 | ||
130 | static inline int s5p_get_cpu_rev(void) | |
131 | { | |
132 | return s5p_cpu_rev; | |
133 | } | |
008a351a MK |
134 | |
135 | static inline void s5p_set_cpu_id(void) | |
136 | { | |
7775831d MK |
137 | unsigned int pro_id = (readl(EXYNOS4_PRO_ID) & 0x00FFF000) >> 12; |
138 | ||
139 | switch (pro_id) { | |
140 | case 0x200: | |
141 | /* Exynos4210 EVT0 */ | |
142 | s5p_cpu_id = 0x4210; | |
5d845f27 | 143 | s5p_cpu_rev = 0; |
7775831d MK |
144 | break; |
145 | case 0x210: | |
146 | /* Exynos4210 EVT1 */ | |
147 | s5p_cpu_id = 0x4210; | |
148 | break; | |
149 | case 0x412: | |
150 | /* Exynos4412 */ | |
151 | s5p_cpu_id = 0x4412; | |
152 | break; | |
153 | case 0x520: | |
154 | /* Exynos5250 */ | |
155 | s5p_cpu_id = 0x5250; | |
156 | break; | |
5d845f27 | 157 | } |
008a351a MK |
158 | } |
159 | ||
7775831d MK |
160 | static inline char *s5p_get_cpu_name(void) |
161 | { | |
162 | return EXYNOS_CPU_NAME; | |
163 | } | |
164 | ||
008a351a | 165 | #define IS_SAMSUNG_TYPE(type, id) \ |
ca35a0cd | 166 | static inline int __attribute__((no_instrument_function)) cpu_is_##type(void) \ |
008a351a | 167 | { \ |
7775831d | 168 | return (s5p_cpu_id >> 12) == id; \ |
008a351a MK |
169 | } |
170 | ||
7775831d MK |
171 | IS_SAMSUNG_TYPE(exynos4, 0x4) |
172 | IS_SAMSUNG_TYPE(exynos5, 0x5) | |
008a351a | 173 | |
6fcc059f | 174 | #define IS_EXYNOS_TYPE(type, id) \ |
ca35a0cd SG |
175 | static inline int __attribute__((no_instrument_function)) \ |
176 | proid_is_##type(void) \ | |
6fcc059f MK |
177 | { \ |
178 | return s5p_cpu_id == id; \ | |
179 | } | |
180 | ||
181 | IS_EXYNOS_TYPE(exynos4210, 0x4210) | |
b189a83a | 182 | IS_EXYNOS_TYPE(exynos4412, 0x4412) |
6fcc059f MK |
183 | IS_EXYNOS_TYPE(exynos5250, 0x5250) |
184 | ||
008a351a | 185 | #define SAMSUNG_BASE(device, base) \ |
ca35a0cd SG |
186 | static inline unsigned int __attribute__((no_instrument_function)) \ |
187 | samsung_get_base_##device(void) \ | |
008a351a | 188 | { \ |
ca35a0cd | 189 | if (cpu_is_exynos4()) { \ |
b189a83a CK |
190 | if (proid_is_exynos4412()) \ |
191 | return EXYNOS4X12_##base; \ | |
393cb361 | 192 | return EXYNOS4_##base; \ |
b189a83a | 193 | } else if (cpu_is_exynos5()) { \ |
37bb6d89 | 194 | return EXYNOS5_##base; \ |
b189a83a CK |
195 | } \ |
196 | return 0; \ | |
008a351a MK |
197 | } |
198 | ||
199 | SAMSUNG_BASE(adc, ADC_BASE) | |
200 | SAMSUNG_BASE(clock, CLOCK_BASE) | |
acbb1eb7 | 201 | SAMSUNG_BASE(ace_sfr, ACE_SFR_BASE) |
c4015050 | 202 | SAMSUNG_BASE(dp, DP_BASE) |
283591f1 | 203 | SAMSUNG_BASE(sysreg, SYSREG_BASE) |
008a351a | 204 | SAMSUNG_BASE(fimd, FIMD_BASE) |
1a758aec | 205 | SAMSUNG_BASE(i2c, I2C_BASE) |
87fa491a | 206 | SAMSUNG_BASE(i2s, I2S_BASE) |
283591f1 | 207 | SAMSUNG_BASE(mipi_dsim, MIPI_DSIM_BASE) |
008a351a MK |
208 | SAMSUNG_BASE(gpio_part1, GPIO_PART1_BASE) |
209 | SAMSUNG_BASE(gpio_part2, GPIO_PART2_BASE) | |
210 | SAMSUNG_BASE(gpio_part3, GPIO_PART3_BASE) | |
37bb6d89 | 211 | SAMSUNG_BASE(gpio_part4, GPIO_PART4_BASE) |
008a351a MK |
212 | SAMSUNG_BASE(pro_id, PRO_ID) |
213 | SAMSUNG_BASE(mmc, MMC_BASE) | |
214 | SAMSUNG_BASE(modem, MODEM_BASE) | |
215 | SAMSUNG_BASE(sromc, SROMC_BASE) | |
216 | SAMSUNG_BASE(swreset, SWRESET) | |
217 | SAMSUNG_BASE(timer, PWMTIMER_BASE) | |
218 | SAMSUNG_BASE(uart, UART_BASE) | |
219 | SAMSUNG_BASE(usb_phy, USBPHY_BASE) | |
7590d3ce | 220 | SAMSUNG_BASE(usb_ehci, USB_HOST_EHCI_BASE) |
008a351a MK |
221 | SAMSUNG_BASE(usb_otg, USBOTG_BASE) |
222 | SAMSUNG_BASE(watchdog, WATCHDOG_BASE) | |
77e490e2 | 223 | SAMSUNG_BASE(power, POWER_BASE) |
383b5cc5 HR |
224 | SAMSUNG_BASE(spi, SPI_BASE) |
225 | SAMSUNG_BASE(spi_isp, SPI_ISP_BASE) | |
b5f9756f | 226 | SAMSUNG_BASE(tzpc, TZPC_BASE) |
643be9c0 RS |
227 | SAMSUNG_BASE(dmc_ctrl, DMC_CTRL_BASE) |
228 | SAMSUNG_BASE(dmc_phy, DMC_PHY_BASE) | |
008a351a MK |
229 | #endif |
230 | ||
393cb361 | 231 | #endif /* _EXYNOS4_CPU_H */ |