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1 | /* |
2 | * Copyright (C) 2012 Samsung Electronics | |
3 | * Rajeshwari Shinde <rajeshwari.s@samsung.com> | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
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6 | */ |
7 | ||
8 | #ifndef __ASM_ARM_ARCH_PERIPH_H | |
9 | #define __ASM_ARM_ARCH_PERIPH_H | |
10 | ||
11 | /* | |
d0559118 | 12 | * Peripherals required for pinmux configuration. List will |
c5e3710a | 13 | * grow with support for more devices getting added. |
d0559118 | 14 | * Numbering based on interrupt table. |
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15 | * |
16 | */ | |
17 | enum periph_id { | |
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18 | PERIPH_ID_UART0 = 51, |
19 | PERIPH_ID_UART1, | |
20 | PERIPH_ID_UART2, | |
21 | PERIPH_ID_UART3, | |
22 | PERIPH_ID_I2C0 = 56, | |
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23 | PERIPH_ID_I2C1, |
24 | PERIPH_ID_I2C2, | |
25 | PERIPH_ID_I2C3, | |
26 | PERIPH_ID_I2C4, | |
27 | PERIPH_ID_I2C5, | |
28 | PERIPH_ID_I2C6, | |
29 | PERIPH_ID_I2C7, | |
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30 | PERIPH_ID_SPI0 = 68, |
31 | PERIPH_ID_SPI1, | |
32 | PERIPH_ID_SPI2, | |
33 | PERIPH_ID_SDMMC0 = 75, | |
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34 | PERIPH_ID_SDMMC1, |
35 | PERIPH_ID_SDMMC2, | |
36 | PERIPH_ID_SDMMC3, | |
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37 | PERIPH_ID_I2S1 = 99, |
38 | ||
39 | /* Since following peripherals do | |
40 | * not have shared peripheral interrupts (SPIs) | |
41 | * they are numbered arbitiraly after the maximum | |
42 | * SPIs Exynos has (128) | |
43 | */ | |
44 | PERIPH_ID_SROMC = 128, | |
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45 | PERIPH_ID_SPI3, |
46 | PERIPH_ID_SPI4, | |
d0559118 | 47 | PERIPH_ID_SDMMC4, |
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48 | PERIPH_ID_PWM0, |
49 | PERIPH_ID_PWM1, | |
50 | PERIPH_ID_PWM2, | |
51 | PERIPH_ID_PWM3, | |
52 | PERIPH_ID_PWM4, | |
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53 | |
54 | PERIPH_ID_COUNT, | |
55 | PERIPH_ID_NONE = -1, | |
56 | }; | |
57 | ||
58 | #endif /* __ASM_ARM_ARCH_PERIPH_H */ |