[thirdparty/u-boot.git] / arch / arm / include / asm / arch-fsl-layerscape / fsl_serdes.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2015 Freescale Semiconductor, Inc.
 */

#ifndef __FSL_SERDES_H__
#define __FSL_SERDES_H__

#include <config.h>

#ifdef CONFIG_FSL_LSCH3
enum srds_prtcl {
	/*
	 * Nobody will check whether the device 'NONE' has been configured,
	 * So use it to indicate if the serdes_prtcl_map has been initialized.
	 */
	NONE = 0,
	PCIE1,
	PCIE2,
	PCIE3,
	PCIE4,
	SATA1,
	SATA2,
	XAUI1,
	XAUI2,
	XFI1,
	XFI2,
	XFI3,
	XFI4,
	XFI5,
	XFI6,
	XFI7,
	XFI8,
	SGMII1,
	SGMII2,
	SGMII3,
	SGMII4,
	SGMII5,
	SGMII6,
	SGMII7,
	SGMII8,
	SGMII9,
	SGMII10,
	SGMII11,
	SGMII12,
	SGMII13,
	SGMII14,
	SGMII15,
	SGMII16,
	QSGMII_A,
	QSGMII_B,
	QSGMII_C,
	QSGMII_D,
	SERDES_PRCTL_COUNT
};

enum srds {
	FSL_SRDS_1  = 0,
	FSL_SRDS_2  = 1,
};
#elif defined(CONFIG_FSL_LSCH2)
enum srds_prtcl {
	/*
	 * Nobody will check whether the device 'NONE' has been configured,
	 * So use it to indicate if the serdes_prtcl_map has been initialized.
	 */
	NONE = 0,
	PCIE1,
	PCIE2,
	PCIE3,
	PCIE4,
	SATA1,
	SATA2,
	SRIO1,
	SRIO2,
	SGMII_FM1_DTSEC1,
	SGMII_FM1_DTSEC2,
	SGMII_FM1_DTSEC3,
	SGMII_FM1_DTSEC4,
	SGMII_FM1_DTSEC5,
	SGMII_FM1_DTSEC6,
	SGMII_FM1_DTSEC9,
	SGMII_FM1_DTSEC10,
	SGMII_FM2_DTSEC1,
	SGMII_FM2_DTSEC2,
	SGMII_FM2_DTSEC3,
	SGMII_FM2_DTSEC4,
	SGMII_FM2_DTSEC5,
	SGMII_FM2_DTSEC6,
	SGMII_FM2_DTSEC9,
	SGMII_FM2_DTSEC10,
	SGMII_TSEC1,
	SGMII_TSEC2,
	SGMII_TSEC3,
	SGMII_TSEC4,
	XAUI_FM1,
	XAUI_FM2,
	AURORA,
	CPRI1,
	CPRI2,
	CPRI3,
	CPRI4,
	CPRI5,
	CPRI6,
	CPRI7,
	CPRI8,
	XAUI_FM1_MAC9,
	XAUI_FM1_MAC10,
	XAUI_FM2_MAC9,
	XAUI_FM2_MAC10,
	HIGIG_FM1_MAC9,
	HIGIG_FM1_MAC10,
	HIGIG_FM2_MAC9,
	HIGIG_FM2_MAC10,
	QSGMII_FM1_A,		/* A indicates MACs 1,2,5,6 */
	QSGMII_FM1_B,		/* B indicates MACs 5,6,9,10 */
	QSGMII_FM2_A,
	QSGMII_FM2_B,
	XFI_FM1_MAC1,
	XFI_FM1_MAC2,
	XFI_FM1_MAC9,
	XFI_FM1_MAC10,
	XFI_FM2_MAC9,
	XFI_FM2_MAC10,
	INTERLAKEN,
	QSGMII_SW1_A,		/* Indicates ports on L2 Switch */
	QSGMII_SW1_B,
	SGMII_2500_FM1_DTSEC1,
	SGMII_2500_FM1_DTSEC2,
	SGMII_2500_FM1_DTSEC3,
	SGMII_2500_FM1_DTSEC4,
	SGMII_2500_FM1_DTSEC5,
	SGMII_2500_FM1_DTSEC6,
	SGMII_2500_FM1_DTSEC9,
	SGMII_2500_FM1_DTSEC10,
	SGMII_2500_FM2_DTSEC1,
	SGMII_2500_FM2_DTSEC2,
	SGMII_2500_FM2_DTSEC3,
	SGMII_2500_FM2_DTSEC4,
	SGMII_2500_FM2_DTSEC5,
	SGMII_2500_FM2_DTSEC6,
	SGMII_2500_FM2_DTSEC9,
	SGMII_2500_FM2_DTSEC10,
	TX_CLK,
	SERDES_PRCTL_COUNT
};

enum srds {
	FSL_SRDS_1  = 0,
	FSL_SRDS_2  = 1,
};

#endif

int is_serdes_configured(enum srds_prtcl device);
void fsl_serdes_init(void);
int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
int is_serdes_prtcl_valid(int serdes, u32 prtcl);
int serdes_get_number(int serdes, int cfg);
void fsl_rgmii_init(void);

#ifdef CONFIG_FSL_LSCH2
const char *serdes_clock_to_string(u32 clock);
int get_serdes_protocol(void);
#endif
#ifdef CONFIG_SYS_HAS_SERDES
/* Get the volt of SVDD in unit mV */
int get_serdes_volt(void);
/* Set the volt of SVDD in unit mV */
int set_serdes_volt(int svdd);
/* The target volt of SVDD in unit mV */
int setup_serdes_volt(u32 svdd);
#endif

#endif /* __FSL_SERDES_H__ */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
31d34c6c ML	2	/*
31d34c6c ML	3	* Copyright 2015 Freescale Semiconductor, Inc.
31d34c6c ML	4	*/
31d34c6c ML	5
9f3183d2 MH	6	#ifndef __FSL_SERDES_H__
9f3183d2 MH	7	#define __FSL_SERDES_H__
31d34c6c ML	8
	9	#include <config.h>
	10
6d9b82d0	11	#ifdef CONFIG_FSL_LSCH3
31d34c6c	12	enum srds_prtcl {
71fe2225 HZ	13	/*
	14	* Nobody will check whether the device 'NONE' has been configured,
	15	* So use it to indicate if the serdes_prtcl_map has been initialized.
	16	*/
31d34c6c ML	17	NONE = 0,
	18	PCIE1,
	19	PCIE2,
	20	PCIE3,
	21	PCIE4,
	22	SATA1,
	23	SATA2,
	24	XAUI1,
	25	XAUI2,
	26	XFI1,
	27	XFI2,
	28	XFI3,
	29	XFI4,
	30	XFI5,
	31	XFI6,
	32	XFI7,
	33	XFI8,
	34	SGMII1,
	35	SGMII2,
	36	SGMII3,
	37	SGMII4,
	38	SGMII5,
	39	SGMII6,
	40	SGMII7,
	41	SGMII8,
	42	SGMII9,
	43	SGMII10,
	44	SGMII11,
	45	SGMII12,
	46	SGMII13,
	47	SGMII14,
	48	SGMII15,
	49	SGMII16,
1b7dba99 PK	50	QSGMII_A,
	51	QSGMII_B,
	52	QSGMII_C,
	53	QSGMII_D,
31d34c6c ML	54	SERDES_PRCTL_COUNT
	55	};
	56
	57	enum srds {
	58	FSL_SRDS_1 = 0,
	59	FSL_SRDS_2 = 1,
	60	};
22a44d08	61	#elif defined(CONFIG_FSL_LSCH2)
8281c58f	62	enum srds_prtcl {
71fe2225 HZ	63	/*
	64	* Nobody will check whether the device 'NONE' has been configured,
	65	* So use it to indicate if the serdes_prtcl_map has been initialized.
	66	*/
8281c58f MH	67	NONE = 0,
	68	PCIE1,
	69	PCIE2,
	70	PCIE3,
	71	PCIE4,
	72	SATA1,
	73	SATA2,
	74	SRIO1,
	75	SRIO2,
	76	SGMII_FM1_DTSEC1,
	77	SGMII_FM1_DTSEC2,
	78	SGMII_FM1_DTSEC3,
	79	SGMII_FM1_DTSEC4,
	80	SGMII_FM1_DTSEC5,
	81	SGMII_FM1_DTSEC6,
	82	SGMII_FM1_DTSEC9,
	83	SGMII_FM1_DTSEC10,
	84	SGMII_FM2_DTSEC1,
	85	SGMII_FM2_DTSEC2,
	86	SGMII_FM2_DTSEC3,
	87	SGMII_FM2_DTSEC4,
	88	SGMII_FM2_DTSEC5,
	89	SGMII_FM2_DTSEC6,
	90	SGMII_FM2_DTSEC9,
	91	SGMII_FM2_DTSEC10,
	92	SGMII_TSEC1,
	93	SGMII_TSEC2,
	94	SGMII_TSEC3,
	95	SGMII_TSEC4,
	96	XAUI_FM1,
	97	XAUI_FM2,
	98	AURORA,
	99	CPRI1,
	100	CPRI2,
	101	CPRI3,
	102	CPRI4,
	103	CPRI5,
	104	CPRI6,
	105	CPRI7,
	106	CPRI8,
	107	XAUI_FM1_MAC9,
	108	XAUI_FM1_MAC10,
	109	XAUI_FM2_MAC9,
	110	XAUI_FM2_MAC10,
	111	HIGIG_FM1_MAC9,
	112	HIGIG_FM1_MAC10,
	113	HIGIG_FM2_MAC9,
	114	HIGIG_FM2_MAC10,
	115	QSGMII_FM1_A, /* A indicates MACs 1,2,5,6 */
	116	QSGMII_FM1_B, /* B indicates MACs 5,6,9,10 */
	117	QSGMII_FM2_A,
	118	QSGMII_FM2_B,
	119	XFI_FM1_MAC1,
	120	XFI_FM1_MAC2,
	121	XFI_FM1_MAC9,
	122	XFI_FM1_MAC10,
	123	XFI_FM2_MAC9,
	124	XFI_FM2_MAC10,
	125	INTERLAKEN,
	126	QSGMII_SW1_A, /* Indicates ports on L2 Switch */
	127	QSGMII_SW1_B,
	128	SGMII_2500_FM1_DTSEC1,
	129	SGMII_2500_FM1_DTSEC2,
	130	SGMII_2500_FM1_DTSEC3,
131	SGMII_2500_FM1_DTSEC4,
132	SGMII_2500_FM1_DTSEC5,
133	SGMII_2500_FM1_DTSEC6,
134	SGMII_2500_FM1_DTSEC9,
135	SGMII_2500_FM1_DTSEC10,
136	SGMII_2500_FM2_DTSEC1,
137	SGMII_2500_FM2_DTSEC2,
138	SGMII_2500_FM2_DTSEC3,
139	SGMII_2500_FM2_DTSEC4,
140	SGMII_2500_FM2_DTSEC5,
141	SGMII_2500_FM2_DTSEC6,
142	SGMII_2500_FM2_DTSEC9,
143	SGMII_2500_FM2_DTSEC10,
b7f2bbff	144	TX_CLK,
8281c58f MH	145	SERDES_PRCTL_COUNT
	146	};
	147
	148	enum srds {
	149	FSL_SRDS_1 = 0,
da4d620c	150	FSL_SRDS_2 = 1,
8281c58f MH	151	};
8281c58f MH	152
9f3183d2	153	#endif
31d34c6c ML	154
	155	int is_serdes_configured(enum srds_prtcl device);
	156	void fsl_serdes_init(void);
31d34c6c ML	157	int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
	158	enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
	159	int is_serdes_prtcl_valid(int serdes, u32 prtcl);
6d9b82d0	160	int serdes_get_number(int serdes, int cfg);
17d066fc	161	void fsl_rgmii_init(void);
31d34c6c	162
b528b937	163	#ifdef CONFIG_FSL_LSCH2
8281c58f MH	164	const char *serdes_clock_to_string(u32 clock);
8281c58f MH	165	int get_serdes_protocol(void);
a1f95ff7	166	#endif
031acdba HZ	167	#ifdef CONFIG_SYS_HAS_SERDES
	168	/* Get the volt of SVDD in unit mV */
	169	int get_serdes_volt(void);
	170	/* Set the volt of SVDD in unit mV */
	171	int set_serdes_volt(int svdd);
	172	/* The target volt of SVDD in unit mV */
	173	int setup_serdes_volt(u32 svdd);
	174	#endif
8281c58f	175
9f3183d2	176	#endif /* __FSL_SERDES_H__ */