[people/ms/u-boot.git] / arch / arm / include / asm / arch-fsl-layerscape / mp.h

/*
 * Copyright 2014-2015, Freescale Semiconductor
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _FSL_LAYERSCAPE_MP_H
#define _FSL_LAYERSCAPE_MP_H

/*
* Each spin table element is defined as
* struct {
*      uint64_t entry_addr;
*      uint64_t status;
*      uint64_t lpid;
* };
* we pad this struct to 64 bytes so each entry is in its own cacheline
* the actual spin table is an array of these structures
*/
#define SPIN_TABLE_ELEM_ENTRY_ADDR_IDX	0
#define SPIN_TABLE_ELEM_STATUS_IDX	1
#define SPIN_TABLE_ELEM_LPID_IDX	2
#define WORDS_PER_SPIN_TABLE_ENTRY	8	/* pad to 64 bytes */
#define SPIN_TABLE_ELEM_SIZE		64

#define id_to_core(x)	((x & 3) | (x >> 6))
#ifndef __ASSEMBLY__
extern u64 __spin_table[];
extern u64 __real_cntfrq;
extern u64 *secondary_boot_code;
extern size_t __secondary_boot_code_size;
int fsl_layerscape_wake_seconday_cores(void);
void *get_spin_tbl_addr(void);
phys_addr_t determine_mp_bootpg(void);
void secondary_boot_func(void);
int is_core_online(u64 cpu_id);
#endif
#endif /* _FSL_LAYERSCAPE_MP_H */
Commit	Line	Data
40f8dec5	1	/*
9f3183d2	2	* Copyright 2014-2015, Freescale Semiconductor
40f8dec5 YS	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
9f3183d2 MH	7	#ifndef _FSL_LAYERSCAPE_MP_H
9f3183d2 MH	8	#define _FSL_LAYERSCAPE_MP_H
40f8dec5 YS	9
	10	/*
	11	* Each spin table element is defined as
	12	* struct {
	13	* uint64_t entry_addr;
	14	* uint64_t status;
	15	* uint64_t lpid;
	16	* };
	17	* we pad this struct to 64 bytes so each entry is in its own cacheline
	18	* the actual spin table is an array of these structures
	19	*/
	20	#define SPIN_TABLE_ELEM_ENTRY_ADDR_IDX 0
	21	#define SPIN_TABLE_ELEM_STATUS_IDX 1
	22	#define SPIN_TABLE_ELEM_LPID_IDX 2
	23	#define WORDS_PER_SPIN_TABLE_ENTRY 8 /* pad to 64 bytes */
	24	#define SPIN_TABLE_ELEM_SIZE 64
	25
	26	#define id_to_core(x) ((x & 3) \| (x >> 6))
	27	#ifndef __ASSEMBLY__
	28	extern u64 __spin_table[];
207774b2	29	extern u64 __real_cntfrq;
40f8dec5 YS	30	extern u64 *secondary_boot_code;
40f8dec5 YS	31	extern size_t __secondary_boot_code_size;
9f3183d2	32	int fsl_layerscape_wake_seconday_cores(void);
40f8dec5 YS	33	void *get_spin_tbl_addr(void);
	34	phys_addr_t determine_mp_bootpg(void);
	35	void secondary_boot_func(void);
60385d94	36	int is_core_online(u64 cpu_id);
40f8dec5	37	#endif
9f3183d2	38	#endif /* _FSL_LAYERSCAPE_MP_H */