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| Commit | Line | Data |
|---|---|---|
| 2f78eae5 YS |
1 | /* |
| 2 | * Copyright 2014, Freescale Semiconductor | |
| 3 | * | |
| 4 | * SPDX-License-Identifier: GPL-2.0+ | |
| 5 | */ | |
| 6 | ||
| 7 | #ifndef _ASM_ARMV8_FSL_LSCH3_CONFIG_ | |
| 8 | #define _ASM_ARMV8_FSL_LSCH3_CONFIG_ | |
| 9 | ||
| 10 | #include <fsl_ddrc_version.h> | |
| 40f8dec5 | 11 | #define CONFIG_MP |
| 2f78eae5 YS |
12 | #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ |
| 13 | /* Link Definitions */ | |
| 14 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) | |
| 15 | ||
| 16 | #define CONFIG_SYS_IMMR 0x01000000 | |
| 17 | #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) | |
| 18 | #define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000) | |
| d9c68b14 | 19 | #define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000 |
| 2f78eae5 YS |
20 | #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000) |
| 21 | #define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000) | |
| 40f8dec5 | 22 | #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000) |
| 2f78eae5 YS |
23 | #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000) |
| 24 | #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000) | |
| 25 | #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000) | |
| 26 | #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000) | |
| 27 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500) | |
| 28 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600) | |
| 29 | #define CONFIG_SYS_FSL_TIMER_ADDR 0x023d0000 | |
| 30 | #define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \ | |
| 31 | 0x18A0) | |
| 32 | ||
| 33 | #define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000) | |
| 34 | #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000) | |
| 35 | #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000) | |
| 36 | #define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000) | |
| 37 | ||
| 9c66ce66 BS |
38 | /* TZ Protection Controller Definitions */ |
| 39 | #define TZPC_BASE 0x02200000 | |
| 40 | #define TZPCR0SIZE_BASE (TZPC_BASE) | |
| 41 | #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800) | |
| 42 | #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) | |
| 43 | #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808) | |
| 44 | #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C) | |
| 45 | #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810) | |
| 46 | #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814) | |
| 47 | #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818) | |
| 48 | #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) | |
| 49 | #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) | |
| 50 | ||
| 51 | /* TZ Address Space Controller Definitions */ | |
| 52 | #define TZASC1_BASE 0x01100000 /* as per CCSR map. */ | |
| 53 | #define TZASC2_BASE 0x01110000 /* as per CCSR map. */ | |
| 54 | #define TZASC3_BASE 0x01120000 /* as per CCSR map. */ | |
| 55 | #define TZASC4_BASE 0x01130000 /* as per CCSR map. */ | |
| 56 | #define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000))) | |
| 57 | #define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004) | |
| 58 | #define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008) | |
| 59 | #define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100) | |
| 60 | #define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104) | |
| 61 | #define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108) | |
| 62 | #define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C) | |
| 63 | #define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110) | |
| 64 | #define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114) | |
| 65 | ||
| 2f78eae5 YS |
66 | /* Generic Interrupt Controller Definitions */ |
| 67 | #define GICD_BASE 0x06000000 | |
| 68 | #define GICR_BASE 0x06100000 | |
| 69 | ||
| 70 | /* SMMU Defintions */ | |
| 71 | #define SMMU_BASE 0x05000000 /* GR0 Base */ | |
| 72 | ||
| 73 | /* DDR */ | |
| 74 | #define CONFIG_SYS_FSL_DDR_LE | |
| 75 | #define CONFIG_VERY_BIG_RAM | |
| 8340e7ac YS |
76 | #ifdef CONFIG_SYS_FSL_DDR4 |
| 77 | #define CONFIG_SYS_FSL_DDRC_GEN4 | |
| 78 | #else | |
| 2f78eae5 | 79 | #define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */ |
| 8340e7ac | 80 | #endif |
| 2f78eae5 YS |
81 | #define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */ |
| 82 | #define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) | |
| 83 | #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE | |
| 84 | #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 | |
| 85 | ||
| 86 | ||
| 87 | /* IFC */ | |
| 88 | #define CONFIG_SYS_FSL_IFC_LE | |
| 89 | ||
| f749db3a | 90 | #ifdef CONFIG_LS2085A |
| 2f78eae5 YS |
91 | #define CONFIG_MAX_CPUS 16 |
| 92 | #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 | |
| d9c68b14 | 93 | #define CONFIG_NUM_DDR_CONTROLLERS 3 |
| 2f78eae5 YS |
94 | #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } |
| 95 | #else | |
| 96 | #error SoC not defined | |
| 97 | #endif | |
| 98 | ||
| 99 | #endif /* _ASM_ARMV8_FSL_LSCH3_CONFIG_ */ |