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4efb77d4 PW |
1 | /* |
2 | * (C) Copyright 2009 | |
3 | * Marvell Semiconductor <www.marvell.com> | |
4 | * Written-by: Prafulla Wadaskar <prafulla@marvell.com> | |
5 | * | |
6 | * Header file for the Marvell's Feroceon CPU core. | |
7 | * | |
8 | * See file CREDITS for list of people who contributed to this | |
9 | * project. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | |
24 | * MA 02110-1301 USA | |
25 | */ | |
26 | ||
27 | #ifndef _ASM_ARCH_KIRKWOOD_H | |
28 | #define _ASM_ARCH_KIRKWOOD_H | |
29 | ||
4efb77d4 | 30 | #if defined (CONFIG_FEROCEON_88FR131) || defined (CONFIG_SHEEVA_88SV131) |
4efb77d4 PW |
31 | |
32 | /* SOC specific definations */ | |
33 | #define INTREG_BASE 0xd0000000 | |
34 | #define KW_REGISTER(x) (KW_REGS_PHY_BASE + x) | |
35 | #define KW_OFFSET_REG (INTREG_BASE + 0x20080) | |
36 | ||
37 | /* undocumented registers */ | |
38 | #define KW_REG_UNDOC_0x1470 (KW_REGISTER(0x1470)) | |
39 | #define KW_REG_UNDOC_0x1478 (KW_REGISTER(0x1478)) | |
40 | ||
688b6a0f | 41 | #define KW_TWSI_BASE (KW_REGISTER(0x11000)) |
4efb77d4 | 42 | #define KW_UART0_BASE (KW_REGISTER(0x12000)) |
b996165f | 43 | #define KW_UART1_BASE (KW_REGISTER(0x12100)) |
4efb77d4 PW |
44 | #define KW_MPP_BASE (KW_REGISTER(0x10000)) |
45 | #define KW_GPIO0_BASE (KW_REGISTER(0x10100)) | |
46 | #define KW_GPIO1_BASE (KW_REGISTER(0x10140)) | |
b608b957 | 47 | #define KW_RTC_BASE (KW_REGISTER(0x10300)) |
4efb77d4 PW |
48 | #define KW_NANDF_BASE (KW_REGISTER(0x10418)) |
49 | #define KW_SPI_BASE (KW_REGISTER(0x10600)) | |
50 | #define KW_CPU_WIN_BASE (KW_REGISTER(0x20000)) | |
51 | #define KW_CPU_REG_BASE (KW_REGISTER(0x20100)) | |
52 | #define KW_TIMER_BASE (KW_REGISTER(0x20300)) | |
53 | #define KW_REG_PCIE_BASE (KW_REGISTER(0x40000)) | |
78eabb90 | 54 | #define KW_USB20_BASE (KW_REGISTER(0x50000)) |
4efb77d4 PW |
55 | #define KW_EGIGA0_BASE (KW_REGISTER(0x72000)) |
56 | #define KW_EGIGA1_BASE (KW_REGISTER(0x76000)) | |
5f305003 PW |
57 | #define KW_SATA_BASE (KW_REGISTER(0x80000)) |
58 | ||
59 | /* Kirkwood Sata controller has two ports */ | |
60 | #define KW_SATA_PORT0_OFFSET 0x2000 | |
61 | #define KW_SATA_PORT1_OFFSET 0x4000 | |
4efb77d4 | 62 | |
d3c9ffd0 AA |
63 | /* Kirkwood GbE controller has two ports */ |
64 | #define MAX_MVGBE_DEVS 2 | |
65 | #define MVGBE0_BASE KW_EGIGA0_BASE | |
66 | #define MVGBE1_BASE KW_EGIGA1_BASE | |
d44265ad | 67 | |
74d34421 AA |
68 | /* Kirkwood USB Host controller */ |
69 | #define MVUSB0_BASE KW_USB20_BASE | |
70 | #define MVUSB0_CPU_ATTR_DRAM_CS0 KWCPU_ATTR_DRAM_CS0 | |
71 | #define MVUSB0_CPU_ATTR_DRAM_CS1 KWCPU_ATTR_DRAM_CS1 | |
72 | #define MVUSB0_CPU_ATTR_DRAM_CS2 KWCPU_ATTR_DRAM_CS2 | |
73 | #define MVUSB0_CPU_ATTR_DRAM_CS3 KWCPU_ATTR_DRAM_CS3 | |
74 | ||
75 | /* Kirkwood CPU memory windows */ | |
76 | #define MVCPU_WIN_CTRL_DATA KWCPU_WIN_CTRL_DATA | |
77 | #define MVCPU_WIN_ENABLE KWCPU_WIN_ENABLE | |
78 | #define MVCPU_WIN_DISABLE KWCPU_WIN_DISABLE | |
79 | ||
4efb77d4 PW |
80 | #if defined (CONFIG_KW88F6281) |
81 | #include <asm/arch/kw88f6281.h> | |
82 | #elif defined (CONFIG_KW88F6192) | |
83 | #include <asm/arch/kw88f6192.h> | |
84 | #else | |
85 | #error "SOC Name not defined" | |
86 | #endif /* CONFIG_KW88F6281 */ | |
87 | #endif /* CONFIG_FEROCEON_88FR131 */ | |
88 | #endif /* _ASM_ARCH_KIRKWOOD_H */ |