[people/ms/u-boot.git] / arch / arm / include / asm / arch-ls102xa / immap_ls102xa.h

/*
 * Copyright 2014 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __ASM_ARCH_LS102XA_IMMAP_H_
#define __ASM_ARCH_LS102XA_IMMAP_H_
#include <fsl_immap.h>

#define SVR_MAJ(svr)		(((svr) >>  4) & 0xf)
#define SVR_MIN(svr)		(((svr) >>  0) & 0xf)
#define SVR_SOC_VER(svr)	(((svr) >> 8) & 0x7ff)
#define IS_E_PROCESSOR(svr)	(svr & 0x80000)
#define IS_SVR_REV(svr, maj, min) \
		((SVR_MAJ(svr) == maj) && (SVR_MIN(svr) == min))

#define SOC_VER_SLS1020		0x00
#define SOC_VER_LS1020		0x10
#define SOC_VER_LS1021		0x11
#define SOC_VER_LS1022		0x12

#define SOC_MAJOR_VER_1_0	0x1
#define SOC_MAJOR_VER_2_0	0x2

#define CCSR_BRR_OFFSET		0xe4
#define CCSR_SCRATCHRW1_OFFSET	0x200

#define RCWSR0_SYS_PLL_RAT_SHIFT	25
#define RCWSR0_SYS_PLL_RAT_MASK		0x1f
#define RCWSR0_MEM_PLL_RAT_SHIFT	16
#define RCWSR0_MEM_PLL_RAT_MASK		0x3f

#define RCWSR4_SRDS1_PRTCL_SHIFT	24
#define RCWSR4_SRDS1_PRTCL_MASK		0xff000000

#define TIMER_COMP_VAL			0xffffffffffffffffull
#define ARCH_TIMER_CTRL_ENABLE		(1 << 0)
#define SYS_COUNTER_CTRL_ENABLE		(1 << 24)

#define DCFG_CCSR_PORSR1_RCW_MASK	0xff800000
#define DCFG_CCSR_PORSR1_RCW_SRC_I2C	0x24800000

#define DCFG_DCSR_PORCR1		0

/*
 * Define default values for some CCSR macros to make header files cleaner
 *
 * To completely disable CCSR relocation in a board header file, define
 * CONFIG_SYS_CCSR_DO_NOT_RELOCATE.  This will force CONFIG_SYS_CCSRBAR_PHYS
 * to a value that is the same as CONFIG_SYS_CCSRBAR.
 */

#ifdef CONFIG_SYS_CCSRBAR_PHYS
#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly."
#endif

#ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE
#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH
#undef CONFIG_SYS_CCSRBAR_PHYS_LOW
#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0
#endif

#ifndef CONFIG_SYS_CCSRBAR
#define CONFIG_SYS_CCSRBAR		CONFIG_SYS_IMMR
#endif

#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0xf
#else
#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0
#endif
#endif

#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_IMMR
#endif

#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
				 CONFIG_SYS_CCSRBAR_PHYS_LOW)

struct sys_info {
	unsigned long freq_processor[CONFIG_MAX_CPUS];
	unsigned long freq_systembus;
	unsigned long freq_ddrbus;
	unsigned long freq_localbus;
};

/* Device Configuration and Pin Control */
struct ccsr_gur {
	u32     porsr1;         /* POR status 1 */
	u32     porsr2;         /* POR status 2 */
	u8      res_008[0x20-0x8];
	u32     gpporcr1;       /* General-purpose POR configuration */
	u32	gpporcr2;
	u32     dcfg_fusesr;    /* Fuse status register */
	u8      res_02c[0x70-0x2c];
	u32     devdisr;        /* Device disable control */
	u32     devdisr2;       /* Device disable control 2 */
	u32     devdisr3;       /* Device disable control 3 */
	u32     devdisr4;       /* Device disable control 4 */
	u32     devdisr5;       /* Device disable control 5 */
	u8      res_084[0x94-0x84];
	u32     coredisru;      /* uppper portion for support of 64 cores */
	u32     coredisrl;      /* lower portion for support of 64 cores */
	u8      res_09c[0xa4-0x9c];
	u32     svr;            /* System version */
	u8	res_0a8[0xb0-0xa8];
	u32	rstcr;		/* Reset control */
	u32	rstrqpblsr;	/* Reset request preboot loader status */
	u8	res_0b8[0xc0-0xb8];
	u32	rstrqmr1;	/* Reset request mask */
	u8	res_0c4[0xc8-0xc4];
	u32	rstrqsr1;	/* Reset request status */
	u8	res_0cc[0xd4-0xcc];
	u32	rstrqwdtmrl;	/* Reset request WDT mask */
	u8	res_0d8[0xdc-0xd8];
	u32	rstrqwdtsrl;	/* Reset request WDT status */
	u8	res_0e0[0xe4-0xe0];
	u32	brrl;		/* Boot release */
	u8      res_0e8[0x100-0xe8];
	u32     rcwsr[16];      /* Reset control word status */
#define RCW_SB_EN_REG_INDEX	7
#define RCW_SB_EN_MASK		0x00200000
	u8      res_140[0x200-0x140];
	u32     scratchrw[4];  /* Scratch Read/Write */
	u8      res_210[0x300-0x210];
	u32     scratchw1r[4];  /* Scratch Read (Write once) */
	u8      res_310[0x400-0x310];
	u32	crstsr;
	u8      res_404[0x550-0x404];
	u32	sataliodnr;
	u8	res_554[0x604-0x554];
	u32	pamubypenr;
	u32	dmacr1;
	u8      res_60c[0x740-0x60c];   /* add more registers when needed */
	u32     tp_ityp[64];    /* Topology Initiator Type Register */
	struct {
		u32     upper;
		u32     lower;
	} tp_cluster[1];        /* Core Cluster n Topology Register */
	u8	res_848[0xe60-0x848];
	u32	ddrclkdr;
	u8	res_e60[0xe68-0xe64];
	u32	ifcclkdr;
	u8	res_e68[0xe80-0xe6c];
	u32	sdhcpcr;
};

#define SCFG_ETSECDMAMCR_LE_BD_FR	0x00000c00
#define SCFG_SNPCNFGCR_SEC_RD_WR	0xc0000000
#define SCFG_ETSECCMCR_GE2_CLK125	0x04000000
#define SCFG_ETSECCMCR_GE0_CLK125	0x00000000
#define SCFG_ETSECCMCR_GE1_CLK125	0x08000000
#define SCFG_PIXCLKCR_PXCKEN		0x80000000
#define SCFG_QSPI_CLKSEL		0xc0100000
#define SCFG_SNPCNFGCR_SEC_RD_WR	0xc0000000
#define SCFG_SNPCNFGCR_DCU_RD_WR	0x03000000
#define SCFG_SNPCNFGCR_SATA_RD_WR	0x00c00000
#define SCFG_SNPCNFGCR_USB3_RD_WR	0x00300000
#define SCFG_SNPCNFGCR_DBG_RD_WR	0x000c0000
#define SCFG_SNPCNFGCR_EDMA_SNP		0x00020000
#define SCFG_ENDIANCR_LE		0x80000000
#define SCFG_DPSLPCR_WDRR_EN		0x00000001
#define SCFG_PMCINTECR_LPUART		0x40000000
#define SCFG_PMCINTECR_FTM		0x20000000
#define SCFG_PMCINTECR_GPIO		0x10000000
#define SCFG_PMCINTECR_IRQ0		0x08000000
#define SCFG_PMCINTECR_IRQ1		0x04000000
#define SCFG_PMCINTECR_ETSECRXG0	0x00800000
#define SCFG_PMCINTECR_ETSECRXG1	0x00400000
#define SCFG_PMCINTECR_ETSECERRG0	0x00080000
#define SCFG_PMCINTECR_ETSECERRG1	0x00040000
#define SCFG_CLUSTERPMCR_WFIL2EN	0x80000000

#define SCFG_BASE			0x01570000
#define SCFG_USB3PRM1CR			0x070
#define SCFG_USB_TXVREFTUNE		0x9

/* Supplemental Configuration Unit */
struct ccsr_scfg {
	u32 dpslpcr;
	u32 resv0[2];
	u32 etsecclkdpslpcr;
	u32 resv1[5];
	u32 fuseovrdcr;
	u32 pixclkcr;
	u32 resv2[5];
	u32 spimsicr;
	u32 resv3[6];
	u32 pex1pmwrcr;
	u32 pex1pmrdsr;
	u32 resv4[3];
	u32 usb3prm1cr;
	u32 usb4prm2cr;
	u32 pex1rdmsgpldlsbsr;
	u32 pex1rdmsgpldmsbsr;
	u32 pex2rdmsgpldlsbsr;
	u32 pex2rdmsgpldmsbsr;
	u32 pex1rdmmsgrqsr;
	u32 pex2rdmmsgrqsr;
	u32 spimsiclrcr;
	u32 pexmscportsr[2];
	u32 pex2pmwrcr;
	u32 resv5[24];
	u32 mac1_streamid;
	u32 mac2_streamid;
	u32 mac3_streamid;
	u32 pex1_streamid;
	u32 pex2_streamid;
	u32 dma_streamid;
	u32 sata_streamid;
	u32 usb3_streamid;
	u32 qe_streamid;
	u32 sdhc_streamid;
	u32 adma_streamid;
	u32 letechsftrstcr;
	u32 core0_sft_rst;
	u32 core1_sft_rst;
	u32 resv6[1];
	u32 usb_hi_addr;
	u32 etsecclkadjcr;
	u32 sai_clk;
	u32 resv7[1];
	u32 dcu_streamid;
	u32 usb2_streamid;
	u32 ftm_reset;
	u32 altcbar;
	u32 qspi_cfg;
	u32 pmcintecr;
	u32 pmcintlecr;
	u32 pmcintsr;
	u32 qos1;
	u32 qos2;
	u32 qos3;
	u32 cci_cfg;
	u32 endiancr;
	u32 etsecdmamcr;
	u32 usb3prm3cr;
	u32 resv9[1];
	u32 debug_streamid;
	u32 resv10[5];
	u32 snpcnfgcr;
	u32 hrstcr;
	u32 intpcr;
	u32 resv12[20];
	u32 scfgrevcr;
	u32 coresrencr;
	u32 pex2pmrdsr;
	u32 eddrtqcfg;
	u32 ddrc2cr;
	u32 ddrc3cr;
	u32 ddrc4cr;
	u32 ddrgcr;
	u32 resv13[120];
	u32 qeioclkcr;
	u32 etsecmcr;
	u32 sdhciovserlcr;
	u32 resv14[61];
	u32 sparecr[8];
	u32 resv15[248];
	u32 core0sftrstsr;
	u32 clusterpmcr;
};

/* Clocking */
struct ccsr_clk {
	struct {
		u32 clkcncsr;	/* core cluster n clock control status */
		u8  res_004[0x1c];
	} clkcsr[2];
	u8	res_040[0x7c0]; /* 0x100 */
	struct {
		u32 pllcngsr;
		u8 res_804[0x1c];
	} pllcgsr[2];
	u8	res_840[0x1c0];
	u32	clkpcsr;	/* 0xa00 Platform clock domain control/status */
	u8	res_a04[0x1fc];
	u32	pllpgsr;	/* 0xc00 Platform PLL General Status */
	u8	res_c04[0x1c];
	u32	plldgsr;	/* 0xc20 DDR PLL General Status */
	u8	res_c24[0x3dc];
};

/* System Counter */
struct sctr_regs {
	u32 cntcr;
	u32 cntsr;
	u32 cntcv1;
	u32 cntcv2;
	u32 resv1[4];
	u32 cntfid0;
	u32 cntfid1;
	u32 resv2[1002];
	u32 counterid[12];
};

#define MAX_SERDES			1
#define SRDS_MAX_LANES			4
#define SRDS_MAX_BANK			2

#define SRDS_RSTCTL_RST			0x80000000
#define SRDS_RSTCTL_RSTDONE		0x40000000
#define SRDS_RSTCTL_RSTERR		0x20000000
#define SRDS_RSTCTL_SWRST		0x10000000
#define SRDS_RSTCTL_SDEN		0x00000020
#define SRDS_RSTCTL_SDRST_B		0x00000040
#define SRDS_RSTCTL_PLLRST_B		0x00000080
#define SRDS_PLLCR0_POFF		0x80000000
#define SRDS_PLLCR0_RFCK_SEL_MASK	0x70000000
#define SRDS_PLLCR0_RFCK_SEL_100	0x00000000
#define SRDS_PLLCR0_RFCK_SEL_125	0x10000000
#define SRDS_PLLCR0_RFCK_SEL_156_25	0x20000000
#define SRDS_PLLCR0_RFCK_SEL_150	0x30000000
#define SRDS_PLLCR0_RFCK_SEL_161_13	0x40000000
#define SRDS_PLLCR0_RFCK_SEL_122_88	0x50000000
#define SRDS_PLLCR0_PLL_LCK		0x00800000
#define SRDS_PLLCR0_FRATE_SEL_MASK	0x000f0000
#define SRDS_PLLCR0_FRATE_SEL_5		0x00000000
#define SRDS_PLLCR0_FRATE_SEL_3_75	0x00050000
#define SRDS_PLLCR0_FRATE_SEL_5_15	0x00060000
#define SRDS_PLLCR0_FRATE_SEL_4		0x00070000
#define SRDS_PLLCR0_FRATE_SEL_3_12	0x00090000
#define SRDS_PLLCR0_FRATE_SEL_3		0x000a0000
#define SRDS_PLLCR1_PLL_BWSEL		0x08000000

struct ccsr_serdes {
	struct {
		u32	rstctl;	/* Reset Control Register */

		u32	pllcr0; /* PLL Control Register 0 */

		u32	pllcr1; /* PLL Control Register 1 */
		u32	res_0c;	/* 0x00c */
		u32	pllcr3;
		u32	pllcr4;
		u8	res_18[0x20-0x18];
	} bank[2];
	u8	res_40[0x90-0x40];
	u32	srdstcalcr;	/* 0x90 TX Calibration Control */
	u8	res_94[0xa0-0x94];
	u32	srdsrcalcr;	/* 0xa0 RX Calibration Control */
	u8	res_a4[0xb0-0xa4];
	u32	srdsgr0;	/* 0xb0 General Register 0 */
	u8	res_b4[0xe0-0xb4];
	u32	srdspccr0;	/* 0xe0 Protocol Converter Config 0 */
	u32	srdspccr1;	/* 0xe4 Protocol Converter Config 1 */
	u32	srdspccr2;	/* 0xe8 Protocol Converter Config 2 */
	u32	srdspccr3;	/* 0xec Protocol Converter Config 3 */
	u32	srdspccr4;	/* 0xf0 Protocol Converter Config 4 */
	u8	res_f4[0x100-0xf4];
	struct {
		u32	lnpssr;	/* 0x100, 0x120, ..., 0x1e0 */
		u8	res_104[0x120-0x104];
	} srdslnpssr[4];
	u8	res_180[0x300-0x180];
	u32	srdspexeqcr;
	u32	srdspexeqpcr[11];
	u8	res_330[0x400-0x330];
	u32	srdspexapcr;
	u8	res_404[0x440-0x404];
	u32	srdspexbpcr;
	u8	res_444[0x800-0x444];
	struct {
		u32	gcr0;	/* 0x800 General Control Register 0 */
		u32	gcr1;	/* 0x804 General Control Register 1 */
		u32	gcr2;	/* 0x808 General Control Register 2 */
		u32	sscr0;
		u32	recr0;	/* 0x810 Receive Equalization Control */
		u32	recr1;
		u32	tecr0;	/* 0x818 Transmit Equalization Control */
		u32	sscr1;
		u32	ttlcr0;	/* 0x820 Transition Tracking Loop Ctrl 0 */
		u8	res_824[0x83c-0x824];
		u32	tcsr3;
	} lane[4];	/* Lane A, B, C, D, E, F, G, H */
	u8	res_a00[0x1000-0xa00];	/* from 0xa00 to 0xfff */
};


/* AHCI (sata) register map */
struct ccsr_ahci {
	u32 res1[0xa4/4];	/* 0x0 - 0xa4 */
	u32 pcfg;	/* port config */
	u32 ppcfg;	/* port phy1 config */
	u32 pp2c;	/* port phy2 config */
	u32 pp3c;	/* port phy3 config */
	u32 pp4c;	/* port phy4 config */
	u32 pp5c;	/* port phy5 config */
	u32 paxic;	/* port AXI config */
	u32 axicc;	/* AXI cache control */
	u32 axipc;	/* AXI PROT control */
	u32 ptc;	/* port Trans Config */
	u32 pts;	/* port Trans Status */
	u32 plc;	/* port link config */
	u32 plc1;	/* port link config1 */
	u32 plc2;	/* port link config2 */
	u32 pls;	/* port link status */
	u32 pls1;	/* port link status1 */
	u32 pcmdc;	/* port CMD config */
	u32 ppcs;	/* port phy control status */
	u32 pberr;	/* port 0/1 BIST error */
	u32 cmds;	/* port 0/1 CMD status error */
};

#define RCPM_POWMGTCSR			0x130
#define RCPM_POWMGTCSR_SERDES_PW	0x80000000
#define RCPM_POWMGTCSR_LPM20_REQ	0x00100000
#define RCPM_POWMGTCSR_LPM20_ST		0x00000200
#define RCPM_POWMGTCSR_P_LPM20_ST	0x00000100
#define RCPM_IPPDEXPCR0			0x140
#define RCPM_IPPDEXPCR0_ETSEC		0x80000000
#define RCPM_IPPDEXPCR0_GPIO		0x00000040
#define RCPM_IPPDEXPCR1			0x144
#define RCPM_IPPDEXPCR1_LPUART		0x40000000
#define RCPM_IPPDEXPCR1_FLEXTIMER	0x20000000
#define RCPM_IPPDEXPCR1_OCRAM1		0x10000000
#define RCPM_NFIQOUTR			0x15c
#define RCPM_NIRQOUTR			0x16c
#define RCPM_DSIMSKR			0x18c
#define RCPM_CLPCL10SETR		0x1c4
#define RCPM_CLPCL10SETR_C0		0x00000001

struct ccsr_rcpm {
	u8 rev1[0x4c];
	u32 twaitsr;
	u8 rev2[0xe0];
	u32 powmgtcsr;
	u8 rev3[0xc];
	u32 ippdexpcr0;
	u32 ippdexpcr1;
	u8 rev4[0x14];
	u32 nfiqoutr;
	u8 rev5[0xc];
	u32 nirqoutr;
	u8 rev6[0x1c];
	u32 dsimskr;
	u8 rev7[0x34];
	u32 clpcl10setr;
};

uint get_svr(void);

#endif	/* __ASM_ARCH_LS102XA_IMMAP_H_ */
Commit	Line	Data
d60a2099 WH	1	/*
	2	* Copyright 2014 Freescale Semiconductor, Inc.
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef __ASM_ARCH_LS102XA_IMMAP_H_
	8	#define __ASM_ARCH_LS102XA_IMMAP_H_
63b2316c	9	#include <fsl_immap.h>
d60a2099 WH	10
	11	#define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
	12	#define SVR_MIN(svr) (((svr) >> 0) & 0xf)
	13	#define SVR_SOC_VER(svr) (((svr) >> 8) & 0x7ff)
	14	#define IS_E_PROCESSOR(svr) (svr & 0x80000)
0c028a03 SL	15	#define IS_SVR_REV(svr, maj, min) \
0c028a03 SL	16	((SVR_MAJ(svr) == maj) && (SVR_MIN(svr) == min))
d60a2099 WH	17
	18	#define SOC_VER_SLS1020 0x00
	19	#define SOC_VER_LS1020 0x10
	20	#define SOC_VER_LS1021 0x11
	21	#define SOC_VER_LS1022 0x12
	22
036f3f33 AW	23	#define SOC_MAJOR_VER_1_0 0x1
	24	#define SOC_MAJOR_VER_2_0 0x2
	25
1a2826f6 XL	26	#define CCSR_BRR_OFFSET 0xe4
	27	#define CCSR_SCRATCHRW1_OFFSET 0x200
	28
d60a2099 WH	29	#define RCWSR0_SYS_PLL_RAT_SHIFT 25
	30	#define RCWSR0_SYS_PLL_RAT_MASK 0x1f
	31	#define RCWSR0_MEM_PLL_RAT_SHIFT 16
	32	#define RCWSR0_MEM_PLL_RAT_MASK 0x3f
	33
	34	#define RCWSR4_SRDS1_PRTCL_SHIFT 24
	35	#define RCWSR4_SRDS1_PRTCL_MASK 0xff000000
	36
2b714cfa	37	#define TIMER_COMP_VAL 0xffffffffffffffffull
d60a2099 WH	38	#define ARCH_TIMER_CTRL_ENABLE (1 << 0)
	39	#define SYS_COUNTER_CTRL_ENABLE (1 << 24)
	40
8ab967b6 AW	41	#define DCFG_CCSR_PORSR1_RCW_MASK 0xff800000
	42	#define DCFG_CCSR_PORSR1_RCW_SRC_I2C 0x24800000
	43
	44	#define DCFG_DCSR_PORCR1 0
	45
60d51736 AW	46	/*
	47	* Define default values for some CCSR macros to make header files cleaner
	48	*
	49	* To completely disable CCSR relocation in a board header file, define
	50	* CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS
	51	* to a value that is the same as CONFIG_SYS_CCSRBAR.
	52	*/
	53
	54	#ifdef CONFIG_SYS_CCSRBAR_PHYS
	55	#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly."
	56	#endif
	57
	58	#ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE
	59	#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH
	60	#undef CONFIG_SYS_CCSRBAR_PHYS_LOW
	61	#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
	62	#endif
	63
	64	#ifndef CONFIG_SYS_CCSRBAR
	65	#define CONFIG_SYS_CCSRBAR CONFIG_SYS_IMMR
	66	#endif
	67
	68	#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
	69	#ifdef CONFIG_PHYS_64BIT
	70	#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf
	71	#else
	72	#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
	73	#endif
	74	#endif
	75
	76	#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
	77	#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_IMMR
	78	#endif
	79
	80	#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 \| \
	81	CONFIG_SYS_CCSRBAR_PHYS_LOW)
	82
d60a2099 WH	83	struct sys_info {
	84	unsigned long freq_processor[CONFIG_MAX_CPUS];
	85	unsigned long freq_systembus;
	86	unsigned long freq_ddrbus;
	87	unsigned long freq_localbus;
	88	};
	89
	90	/* Device Configuration and Pin Control */
	91	struct ccsr_gur {
	92	u32 porsr1; /* POR status 1 */
	93	u32 porsr2; /* POR status 2 */
	94	u8 res_008[0x20-0x8];
	95	u32 gpporcr1; /* General-purpose POR configuration */
	96	u32 gpporcr2;
	97	u32 dcfg_fusesr; /* Fuse status register */
	98	u8 res_02c[0x70-0x2c];
	99	u32 devdisr; /* Device disable control */
	100	u32 devdisr2; /* Device disable control 2 */
	101	u32 devdisr3; /* Device disable control 3 */
	102	u32 devdisr4; /* Device disable control 4 */
	103	u32 devdisr5; /* Device disable control 5 */
	104	u8 res_084[0x94-0x84];
	105	u32 coredisru; /* uppper portion for support of 64 cores */
	106	u32 coredisrl; /* lower portion for support of 64 cores */
	107	u8 res_09c[0xa4-0x9c];
	108	u32 svr; /* System version */
	109	u8 res_0a8[0xb0-0xa8];
	110	u32 rstcr; /* Reset control */
	111	u32 rstrqpblsr; /* Reset request preboot loader status */
	112	u8 res_0b8[0xc0-0xb8];
	113	u32 rstrqmr1; /* Reset request mask */
	114	u8 res_0c4[0xc8-0xc4];
	115	u32 rstrqsr1; /* Reset request status */
	116	u8 res_0cc[0xd4-0xcc];
	117	u32 rstrqwdtmrl; /* Reset request WDT mask */
	118	u8 res_0d8[0xdc-0xd8];
	119	u32 rstrqwdtsrl; /* Reset request WDT status */
	120	u8 res_0e0[0xe4-0xe0];
	121	u32 brrl; /* Boot release */
	122	u8 res_0e8[0x100-0xe8];
	123	u32 rcwsr[16]; /* Reset control word status */
0a6b2714 AB	124	#define RCW_SB_EN_REG_INDEX 7
0a6b2714 AB	125	#define RCW_SB_EN_MASK 0x00200000
d60a2099 WH	126	u8 res_140[0x200-0x140];
	127	u32 scratchrw[4]; /* Scratch Read/Write */
	128	u8 res_210[0x300-0x210];
	129	u32 scratchw1r[4]; /* Scratch Read (Write once) */
	130	u8 res_310[0x400-0x310];
	131	u32 crstsr;
	132	u8 res_404[0x550-0x404];
	133	u32 sataliodnr;
	134	u8 res_554[0x604-0x554];
	135	u32 pamubypenr;
	136	u32 dmacr1;
	137	u8 res_60c[0x740-0x60c]; /* add more registers when needed */
	138	u32 tp_ityp[64]; /* Topology Initiator Type Register */
	139	struct {
	140	u32 upper;
	141	u32 lower;
	142	} tp_cluster[1]; /* Core Cluster n Topology Register */
	143	u8 res_848[0xe60-0x848];
	144	u32 ddrclkdr;
	145	u8 res_e60[0xe68-0xe64];
	146	u32 ifcclkdr;
	147	u8 res_e68[0xe80-0xe6c];
	148	u32 sdhcpcr;
	149	};
	150
ebe4c1e6	151	#define SCFG_ETSECDMAMCR_LE_BD_FR 0x00000c00
5757e06c	152	#define SCFG_SNPCNFGCR_SEC_RD_WR 0xc0000000
d60a2099	153	#define SCFG_ETSECCMCR_GE2_CLK125 0x04000000
0f5e5579 AW	154	#define SCFG_ETSECCMCR_GE0_CLK125 0x00000000
0f5e5579 AW	155	#define SCFG_ETSECCMCR_GE1_CLK125 0x08000000
d60a2099	156	#define SCFG_PIXCLKCR_PXCKEN 0x80000000
d612f0ab	157	#define SCFG_QSPI_CLKSEL 0xc0100000
762b3535 YY	158	#define SCFG_SNPCNFGCR_SEC_RD_WR 0xc0000000
	159	#define SCFG_SNPCNFGCR_DCU_RD_WR 0x03000000
	160	#define SCFG_SNPCNFGCR_SATA_RD_WR 0x00c00000
	161	#define SCFG_SNPCNFGCR_USB3_RD_WR 0x00300000
	162	#define SCFG_SNPCNFGCR_DBG_RD_WR 0x000c0000
	163	#define SCFG_SNPCNFGCR_EDMA_SNP 0x00020000
88c857df	164	#define SCFG_ENDIANCR_LE 0x80000000
349cfc97 HZ	165	#define SCFG_DPSLPCR_WDRR_EN 0x00000001
	166	#define SCFG_PMCINTECR_LPUART 0x40000000
	167	#define SCFG_PMCINTECR_FTM 0x20000000
	168	#define SCFG_PMCINTECR_GPIO 0x10000000
	169	#define SCFG_PMCINTECR_IRQ0 0x08000000
	170	#define SCFG_PMCINTECR_IRQ1 0x04000000
	171	#define SCFG_PMCINTECR_ETSECRXG0 0x00800000
	172	#define SCFG_PMCINTECR_ETSECRXG1 0x00400000
	173	#define SCFG_PMCINTECR_ETSECERRG0 0x00080000
	174	#define SCFG_PMCINTECR_ETSECERRG1 0x00040000
	175	#define SCFG_CLUSTERPMCR_WFIL2EN 0x80000000
d60a2099	176
83fa7118 RW	177	#define SCFG_BASE 0x01570000
	178	#define SCFG_USB3PRM1CR 0x070
	179	#define SCFG_USB_TXVREFTUNE 0x9
	180
d60a2099 WH	181	/* Supplemental Configuration Unit */
	182	struct ccsr_scfg {
	183	u32 dpslpcr;
	184	u32 resv0[2];
	185	u32 etsecclkdpslpcr;
	186	u32 resv1[5];
	187	u32 fuseovrdcr;
	188	u32 pixclkcr;
	189	u32 resv2[5];
	190	u32 spimsicr;
	191	u32 resv3[6];
	192	u32 pex1pmwrcr;
	193	u32 pex1pmrdsr;
	194	u32 resv4[3];
	195	u32 usb3prm1cr;
	196	u32 usb4prm2cr;
	197	u32 pex1rdmsgpldlsbsr;
	198	u32 pex1rdmsgpldmsbsr;
	199	u32 pex2rdmsgpldlsbsr;
	200	u32 pex2rdmsgpldmsbsr;
	201	u32 pex1rdmmsgrqsr;
	202	u32 pex2rdmmsgrqsr;
	203	u32 spimsiclrcr;
ec245fd7	204	u32 pexmscportsr[2];
d60a2099 WH	205	u32 pex2pmwrcr;
	206	u32 resv5[24];
	207	u32 mac1_streamid;
	208	u32 mac2_streamid;
	209	u32 mac3_streamid;
	210	u32 pex1_streamid;
	211	u32 pex2_streamid;
	212	u32 dma_streamid;
	213	u32 sata_streamid;
	214	u32 usb3_streamid;
	215	u32 qe_streamid;
	216	u32 sdhc_streamid;
	217	u32 adma_streamid;
	218	u32 letechsftrstcr;
	219	u32 core0_sft_rst;
	220	u32 core1_sft_rst;
	221	u32 resv6[1];
	222	u32 usb_hi_addr;
	223	u32 etsecclkadjcr;
	224	u32 sai_clk;
	225	u32 resv7[1];
	226	u32 dcu_streamid;
	227	u32 usb2_streamid;
	228	u32 ftm_reset;
	229	u32 altcbar;
	230	u32 qspi_cfg;
	231	u32 pmcintecr;
	232	u32 pmcintlecr;
	233	u32 pmcintsr;
	234	u32 qos1;
	235	u32 qos2;
	236	u32 qos3;
	237	u32 cci_cfg;
88c857df	238	u32 endiancr;
d60a2099 WH	239	u32 etsecdmamcr;
	240	u32 usb3prm3cr;
	241	u32 resv9[1];
	242	u32 debug_streamid;
	243	u32 resv10[5];
	244	u32 snpcnfgcr;
349cfc97	245	u32 hrstcr;
d60a2099 WH	246	u32 intpcr;
	247	u32 resv12[20];
	248	u32 scfgrevcr;
	249	u32 coresrencr;
	250	u32 pex2pmrdsr;
6c4a1eba	251	u32 eddrtqcfg;
d60a2099 WH	252	u32 ddrc2cr;
	253	u32 ddrc3cr;
	254	u32 ddrc4cr;
	255	u32 ddrgcr;
	256	u32 resv13[120];
	257	u32 qeioclkcr;
	258	u32 etsecmcr;
	259	u32 sdhciovserlcr;
	260	u32 resv14[61];
d8222dbe	261	u32 sparecr[8];
349cfc97 HZ	262	u32 resv15[248];
	263	u32 core0sftrstsr;
	264	u32 clusterpmcr;
d60a2099 WH	265	};
	266
	267	/* Clocking */
	268	struct ccsr_clk {
	269	struct {
	270	u32 clkcncsr; /* core cluster n clock control status */
	271	u8 res_004[0x1c];
	272	} clkcsr[2];
	273	u8 res_040[0x7c0]; /* 0x100 */
	274	struct {
	275	u32 pllcngsr;
	276	u8 res_804[0x1c];
	277	} pllcgsr[2];
	278	u8 res_840[0x1c0];
	279	u32 clkpcsr; /* 0xa00 Platform clock domain control/status */
	280	u8 res_a04[0x1fc];
	281	u32 pllpgsr; /* 0xc00 Platform PLL General Status */
	282	u8 res_c04[0x1c];
	283	u32 plldgsr; /* 0xc20 DDR PLL General Status */
	284	u8 res_c24[0x3dc];
	285	};
	286
	287	/* System Counter */
	288	struct sctr_regs {
	289	u32 cntcr;
	290	u32 cntsr;
	291	u32 cntcv1;
	292	u32 cntcv2;
	293	u32 resv1[4];
	294	u32 cntfid0;
	295	u32 cntfid1;
	296	u32 resv2[1002];
	297	u32 counterid[12];
	298	};
	299
	300	#define MAX_SERDES 1
	301	#define SRDS_MAX_LANES 4
	302	#define SRDS_MAX_BANK 2
	303
	304	#define SRDS_RSTCTL_RST 0x80000000
	305	#define SRDS_RSTCTL_RSTDONE 0x40000000
	306	#define SRDS_RSTCTL_RSTERR 0x20000000
	307	#define SRDS_RSTCTL_SWRST 0x10000000
	308	#define SRDS_RSTCTL_SDEN 0x00000020
	309	#define SRDS_RSTCTL_SDRST_B 0x00000040
	310	#define SRDS_RSTCTL_PLLRST_B 0x00000080
	311	#define SRDS_PLLCR0_POFF 0x80000000
	312	#define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
	313	#define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
	314	#define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
	315	#define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
	316	#define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
	317	#define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
	318	#define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000
	319	#define SRDS_PLLCR0_PLL_LCK 0x00800000
	320	#define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000
	321	#define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
	322	#define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000
	323	#define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000
	324	#define SRDS_PLLCR0_FRATE_SEL_4 0x00070000
	325	#define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000
	326	#define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000
	327	#define SRDS_PLLCR1_PLL_BWSEL 0x08000000
	328
329	struct ccsr_serdes {
330	struct {
331	u32 rstctl; /* Reset Control Register */
332
333	u32 pllcr0; /* PLL Control Register 0 */
334
335	u32 pllcr1; /* PLL Control Register 1 */
336	u32 res_0c; /* 0x00c */
337	u32 pllcr3;
338	u32 pllcr4;
339	u8 res_18[0x20-0x18];
340	} bank[2];
341	u8 res_40[0x90-0x40];
342	u32 srdstcalcr; /* 0x90 TX Calibration Control */
343	u8 res_94[0xa0-0x94];
344	u32 srdsrcalcr; /* 0xa0 RX Calibration Control */
345	u8 res_a4[0xb0-0xa4];
346	u32 srdsgr0; /* 0xb0 General Register 0 */
347	u8 res_b4[0xe0-0xb4];
348	u32 srdspccr0; /* 0xe0 Protocol Converter Config 0 */
349	u32 srdspccr1; /* 0xe4 Protocol Converter Config 1 */
350	u32 srdspccr2; /* 0xe8 Protocol Converter Config 2 */
351	u32 srdspccr3; /* 0xec Protocol Converter Config 3 */
352	u32 srdspccr4; /* 0xf0 Protocol Converter Config 4 */
353	u8 res_f4[0x100-0xf4];
354	struct {
355	u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */
356	u8 res_104[0x120-0x104];
357	} srdslnpssr[4];
358	u8 res_180[0x300-0x180];
359	u32 srdspexeqcr;
360	u32 srdspexeqpcr[11];
361	u8 res_330[0x400-0x330];
362	u32 srdspexapcr;
363	u8 res_404[0x440-0x404];
364	u32 srdspexbpcr;
365	u8 res_444[0x800-0x444];
366	struct {
367	u32 gcr0; /* 0x800 General Control Register 0 */
368	u32 gcr1; /* 0x804 General Control Register 1 */
369	u32 gcr2; /* 0x808 General Control Register 2 */
370	u32 sscr0;
371	u32 recr0; /* 0x810 Receive Equalization Control */
372	u32 recr1;
373	u32 tecr0; /* 0x818 Transmit Equalization Control */
374	u32 sscr1;
375	u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */
376	u8 res_824[0x83c-0x824];
377	u32 tcsr3;
378	} lane[4]; /* Lane A, B, C, D, E, F, G, H */
379	u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */
380	};
381
d60a2099	382
d09e401b	383
4632ad77	384	/* AHCI (sata) register map */
	385	struct ccsr_ahci {
	386	u32 res1[0xa4/4]; /* 0x0 - 0xa4 */
	387	u32 pcfg; /* port config */
	388	u32 ppcfg; /* port phy1 config */
	389	u32 pp2c; /* port phy2 config */
	390	u32 pp3c; /* port phy3 config */
	391	u32 pp4c; /* port phy4 config */
	392	u32 pp5c; /* port phy5 config */
	393	u32 paxic; /* port AXI config */
	394	u32 axicc; /* AXI cache control */
	395	u32 axipc; /* AXI PROT control */
	396	u32 ptc; /* port Trans Config */
	397	u32 pts; /* port Trans Status */
	398	u32 plc; /* port link config */
	399	u32 plc1; /* port link config1 */
	400	u32 plc2; /* port link config2 */
	401	u32 pls; /* port link status */
	402	u32 pls1; /* port link status1 */
	403	u32 pcmdc; /* port CMD config */
	404	u32 ppcs; /* port phy control status */
	405	u32 pberr; /* port 0/1 BIST error */
	406	u32 cmds; /* port 0/1 CMD status error */
	407	};
0c028a03	408
349cfc97 HZ	409	#define RCPM_POWMGTCSR 0x130
	410	#define RCPM_POWMGTCSR_SERDES_PW 0x80000000
	411	#define RCPM_POWMGTCSR_LPM20_REQ 0x00100000
	412	#define RCPM_POWMGTCSR_LPM20_ST 0x00000200
	413	#define RCPM_POWMGTCSR_P_LPM20_ST 0x00000100
	414	#define RCPM_IPPDEXPCR0 0x140
	415	#define RCPM_IPPDEXPCR0_ETSEC 0x80000000
	416	#define RCPM_IPPDEXPCR0_GPIO 0x00000040
	417	#define RCPM_IPPDEXPCR1 0x144
	418	#define RCPM_IPPDEXPCR1_LPUART 0x40000000
	419	#define RCPM_IPPDEXPCR1_FLEXTIMER 0x20000000
	420	#define RCPM_IPPDEXPCR1_OCRAM1 0x10000000
	421	#define RCPM_NFIQOUTR 0x15c
	422	#define RCPM_NIRQOUTR 0x16c
	423	#define RCPM_DSIMSKR 0x18c
	424	#define RCPM_CLPCL10SETR 0x1c4
	425	#define RCPM_CLPCL10SETR_C0 0x00000001
	426
	427	struct ccsr_rcpm {
	428	u8 rev1[0x4c];
	429	u32 twaitsr;
	430	u8 rev2[0xe0];
	431	u32 powmgtcsr;
	432	u8 rev3[0xc];
	433	u32 ippdexpcr0;
	434	u32 ippdexpcr1;
	435	u8 rev4[0x14];
	436	u32 nfiqoutr;
	437	u8 rev5[0xc];
	438	u32 nirqoutr;
	439	u8 rev6[0x1c];
	440	u32 dsimskr;
	441	u8 rev7[0x34];
	442	u32 clpcl10setr;
	443	};
	444
0c028a03 SL	445	uint get_svr(void);
0c028a03 SL	446
d60a2099	447	#endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */