[people/ms/u-boot.git] / arch / arm / include / asm / arch-mx28 / regs-apbh.h

/*
 * Freescale i.MX28 APBH Register Definitions
 *
 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
 * on behalf of DENX Software Engineering GmbH
 *
 * Based on code from LTIB:
 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 *
 */

#ifndef __REGS_APBH_H__
#define __REGS_APBH_H__

#include <asm/arch/regs-common.h>

#ifndef	__ASSEMBLY__
struct mx28_apbh_regs {
	mx28_reg_32(hw_apbh_ctrl0)
	mx28_reg_32(hw_apbh_ctrl1)
	mx28_reg_32(hw_apbh_ctrl2)
	mx28_reg_32(hw_apbh_channel_ctrl)
	mx28_reg_32(hw_apbh_devsel)
	mx28_reg_32(hw_apbh_dma_burst_size)
	mx28_reg_32(hw_apbh_debug)

	uint32_t	reserved[36];

	union {
	struct {
		mx28_reg_32(hw_apbh_ch_curcmdar)
		mx28_reg_32(hw_apbh_ch_nxtcmdar)
		mx28_reg_32(hw_apbh_ch_cmd)
		mx28_reg_32(hw_apbh_ch_bar)
		mx28_reg_32(hw_apbh_ch_sema)
		mx28_reg_32(hw_apbh_ch_debug1)
		mx28_reg_32(hw_apbh_ch_debug2)
	} ch[16];
	struct {
		mx28_reg_32(hw_apbh_ch0_curcmdar)
		mx28_reg_32(hw_apbh_ch0_nxtcmdar)
		mx28_reg_32(hw_apbh_ch0_cmd)
		mx28_reg_32(hw_apbh_ch0_bar)
		mx28_reg_32(hw_apbh_ch0_sema)
		mx28_reg_32(hw_apbh_ch0_debug1)
		mx28_reg_32(hw_apbh_ch0_debug2)
		mx28_reg_32(hw_apbh_ch1_curcmdar)
		mx28_reg_32(hw_apbh_ch1_nxtcmdar)
		mx28_reg_32(hw_apbh_ch1_cmd)
		mx28_reg_32(hw_apbh_ch1_bar)
		mx28_reg_32(hw_apbh_ch1_sema)
		mx28_reg_32(hw_apbh_ch1_debug1)
		mx28_reg_32(hw_apbh_ch1_debug2)
		mx28_reg_32(hw_apbh_ch2_curcmdar)
		mx28_reg_32(hw_apbh_ch2_nxtcmdar)
		mx28_reg_32(hw_apbh_ch2_cmd)
		mx28_reg_32(hw_apbh_ch2_bar)
		mx28_reg_32(hw_apbh_ch2_sema)
		mx28_reg_32(hw_apbh_ch2_debug1)
		mx28_reg_32(hw_apbh_ch2_debug2)
		mx28_reg_32(hw_apbh_ch3_curcmdar)
		mx28_reg_32(hw_apbh_ch3_nxtcmdar)
		mx28_reg_32(hw_apbh_ch3_cmd)
		mx28_reg_32(hw_apbh_ch3_bar)
		mx28_reg_32(hw_apbh_ch3_sema)
		mx28_reg_32(hw_apbh_ch3_debug1)
		mx28_reg_32(hw_apbh_ch3_debug2)
		mx28_reg_32(hw_apbh_ch4_curcmdar)
		mx28_reg_32(hw_apbh_ch4_nxtcmdar)
		mx28_reg_32(hw_apbh_ch4_cmd)
		mx28_reg_32(hw_apbh_ch4_bar)
		mx28_reg_32(hw_apbh_ch4_sema)
		mx28_reg_32(hw_apbh_ch4_debug1)
		mx28_reg_32(hw_apbh_ch4_debug2)
		mx28_reg_32(hw_apbh_ch5_curcmdar)
		mx28_reg_32(hw_apbh_ch5_nxtcmdar)
		mx28_reg_32(hw_apbh_ch5_cmd)
		mx28_reg_32(hw_apbh_ch5_bar)
		mx28_reg_32(hw_apbh_ch5_sema)
		mx28_reg_32(hw_apbh_ch5_debug1)
		mx28_reg_32(hw_apbh_ch5_debug2)
		mx28_reg_32(hw_apbh_ch6_curcmdar)
		mx28_reg_32(hw_apbh_ch6_nxtcmdar)
		mx28_reg_32(hw_apbh_ch6_cmd)
		mx28_reg_32(hw_apbh_ch6_bar)
		mx28_reg_32(hw_apbh_ch6_sema)
		mx28_reg_32(hw_apbh_ch6_debug1)
		mx28_reg_32(hw_apbh_ch6_debug2)
		mx28_reg_32(hw_apbh_ch7_curcmdar)
		mx28_reg_32(hw_apbh_ch7_nxtcmdar)
		mx28_reg_32(hw_apbh_ch7_cmd)
		mx28_reg_32(hw_apbh_ch7_bar)
		mx28_reg_32(hw_apbh_ch7_sema)
		mx28_reg_32(hw_apbh_ch7_debug1)
		mx28_reg_32(hw_apbh_ch7_debug2)
		mx28_reg_32(hw_apbh_ch8_curcmdar)
		mx28_reg_32(hw_apbh_ch8_nxtcmdar)
		mx28_reg_32(hw_apbh_ch8_cmd)
		mx28_reg_32(hw_apbh_ch8_bar)
		mx28_reg_32(hw_apbh_ch8_sema)
		mx28_reg_32(hw_apbh_ch8_debug1)
		mx28_reg_32(hw_apbh_ch8_debug2)
		mx28_reg_32(hw_apbh_ch9_curcmdar)
		mx28_reg_32(hw_apbh_ch9_nxtcmdar)
		mx28_reg_32(hw_apbh_ch9_cmd)
		mx28_reg_32(hw_apbh_ch9_bar)
		mx28_reg_32(hw_apbh_ch9_sema)
		mx28_reg_32(hw_apbh_ch9_debug1)
		mx28_reg_32(hw_apbh_ch9_debug2)
		mx28_reg_32(hw_apbh_ch10_curcmdar)
		mx28_reg_32(hw_apbh_ch10_nxtcmdar)
		mx28_reg_32(hw_apbh_ch10_cmd)
		mx28_reg_32(hw_apbh_ch10_bar)
		mx28_reg_32(hw_apbh_ch10_sema)
		mx28_reg_32(hw_apbh_ch10_debug1)
		mx28_reg_32(hw_apbh_ch10_debug2)
		mx28_reg_32(hw_apbh_ch11_curcmdar)
		mx28_reg_32(hw_apbh_ch11_nxtcmdar)
		mx28_reg_32(hw_apbh_ch11_cmd)
		mx28_reg_32(hw_apbh_ch11_bar)
		mx28_reg_32(hw_apbh_ch11_sema)
		mx28_reg_32(hw_apbh_ch11_debug1)
		mx28_reg_32(hw_apbh_ch11_debug2)
		mx28_reg_32(hw_apbh_ch12_curcmdar)
		mx28_reg_32(hw_apbh_ch12_nxtcmdar)
		mx28_reg_32(hw_apbh_ch12_cmd)
		mx28_reg_32(hw_apbh_ch12_bar)
		mx28_reg_32(hw_apbh_ch12_sema)
		mx28_reg_32(hw_apbh_ch12_debug1)
		mx28_reg_32(hw_apbh_ch12_debug2)
		mx28_reg_32(hw_apbh_ch13_curcmdar)
		mx28_reg_32(hw_apbh_ch13_nxtcmdar)
		mx28_reg_32(hw_apbh_ch13_cmd)
		mx28_reg_32(hw_apbh_ch13_bar)
		mx28_reg_32(hw_apbh_ch13_sema)
		mx28_reg_32(hw_apbh_ch13_debug1)
		mx28_reg_32(hw_apbh_ch13_debug2)
		mx28_reg_32(hw_apbh_ch14_curcmdar)
		mx28_reg_32(hw_apbh_ch14_nxtcmdar)
		mx28_reg_32(hw_apbh_ch14_cmd)
		mx28_reg_32(hw_apbh_ch14_bar)
		mx28_reg_32(hw_apbh_ch14_sema)
		mx28_reg_32(hw_apbh_ch14_debug1)
		mx28_reg_32(hw_apbh_ch14_debug2)
		mx28_reg_32(hw_apbh_ch15_curcmdar)
		mx28_reg_32(hw_apbh_ch15_nxtcmdar)
		mx28_reg_32(hw_apbh_ch15_cmd)
		mx28_reg_32(hw_apbh_ch15_bar)
		mx28_reg_32(hw_apbh_ch15_sema)
		mx28_reg_32(hw_apbh_ch15_debug1)
		mx28_reg_32(hw_apbh_ch15_debug2)
	};
	};
	mx28_reg_32(hw_apbh_version)
};
#endif

#define	APBH_CTRL0_SFTRST				(1 << 31)
#define	APBH_CTRL0_CLKGATE				(1 << 30)
#define	APBH_CTRL0_AHB_BURST8_EN			(1 << 29)
#define	APBH_CTRL0_APB_BURST_EN				(1 << 28)
#define	APBH_CTRL0_RSVD0_MASK				(0xfff << 16)
#define	APBH_CTRL0_RSVD0_OFFSET				16
#define	APBH_CTRL0_CLKGATE_CHANNEL_MASK			0xffff
#define	APBH_CTRL0_CLKGATE_CHANNEL_OFFSET		0
#define	APBH_CTRL0_CLKGATE_CHANNEL_SSP0			0x0001
#define	APBH_CTRL0_CLKGATE_CHANNEL_SSP1			0x0002
#define	APBH_CTRL0_CLKGATE_CHANNEL_SSP2			0x0004
#define	APBH_CTRL0_CLKGATE_CHANNEL_SSP3			0x0008
#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND0		0x0010
#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND1		0x0020
#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND2		0x0040
#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND3		0x0080
#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND4		0x0100
#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND5		0x0200
#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND6		0x0400
#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND7		0x0800
#define	APBH_CTRL0_CLKGATE_CHANNEL_HSADC		0x1000
#define	APBH_CTRL0_CLKGATE_CHANNEL_LCDIF		0x2000

#define	APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN			(1 << 31)
#define	APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN			(1 << 30)
#define	APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN			(1 << 29)
#define	APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN			(1 << 28)
#define	APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN			(1 << 27)
#define	APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN			(1 << 26)
#define	APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN			(1 << 25)
#define	APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN			(1 << 24)
#define	APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN			(1 << 23)
#define	APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN			(1 << 22)
#define	APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN			(1 << 21)
#define	APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN			(1 << 20)
#define	APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN			(1 << 19)
#define	APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN			(1 << 18)
#define	APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN			(1 << 17)
#define	APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN			(1 << 16)
#define	APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_OFFSET		16
#define	APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_MASK		(0xffff << 16)
#define	APBH_CTRL1_CH15_CMDCMPLT_IRQ			(1 << 15)
#define	APBH_CTRL1_CH14_CMDCMPLT_IRQ			(1 << 14)
#define	APBH_CTRL1_CH13_CMDCMPLT_IRQ			(1 << 13)
#define	APBH_CTRL1_CH12_CMDCMPLT_IRQ			(1 << 12)
#define	APBH_CTRL1_CH11_CMDCMPLT_IRQ			(1 << 11)
#define	APBH_CTRL1_CH10_CMDCMPLT_IRQ			(1 << 10)
#define	APBH_CTRL1_CH9_CMDCMPLT_IRQ			(1 << 9)
#define	APBH_CTRL1_CH8_CMDCMPLT_IRQ			(1 << 8)
#define	APBH_CTRL1_CH7_CMDCMPLT_IRQ			(1 << 7)
#define	APBH_CTRL1_CH6_CMDCMPLT_IRQ			(1 << 6)
#define	APBH_CTRL1_CH5_CMDCMPLT_IRQ			(1 << 5)
#define	APBH_CTRL1_CH4_CMDCMPLT_IRQ			(1 << 4)
#define	APBH_CTRL1_CH3_CMDCMPLT_IRQ			(1 << 3)
#define	APBH_CTRL1_CH2_CMDCMPLT_IRQ			(1 << 2)
#define	APBH_CTRL1_CH1_CMDCMPLT_IRQ			(1 << 1)
#define	APBH_CTRL1_CH0_CMDCMPLT_IRQ			(1 << 0)

#define	APBH_CTRL2_CH15_ERROR_STATUS			(1 << 31)
#define	APBH_CTRL2_CH14_ERROR_STATUS			(1 << 30)
#define	APBH_CTRL2_CH13_ERROR_STATUS			(1 << 29)
#define	APBH_CTRL2_CH12_ERROR_STATUS			(1 << 28)
#define	APBH_CTRL2_CH11_ERROR_STATUS			(1 << 27)
#define	APBH_CTRL2_CH10_ERROR_STATUS			(1 << 26)
#define	APBH_CTRL2_CH9_ERROR_STATUS			(1 << 25)
#define	APBH_CTRL2_CH8_ERROR_STATUS			(1 << 24)
#define	APBH_CTRL2_CH7_ERROR_STATUS			(1 << 23)
#define	APBH_CTRL2_CH6_ERROR_STATUS			(1 << 22)
#define	APBH_CTRL2_CH5_ERROR_STATUS			(1 << 21)
#define	APBH_CTRL2_CH4_ERROR_STATUS			(1 << 20)
#define	APBH_CTRL2_CH3_ERROR_STATUS			(1 << 19)
#define	APBH_CTRL2_CH2_ERROR_STATUS			(1 << 18)
#define	APBH_CTRL2_CH1_ERROR_STATUS			(1 << 17)
#define	APBH_CTRL2_CH0_ERROR_STATUS			(1 << 16)
#define	APBH_CTRL2_CH15_ERROR_IRQ			(1 << 15)
#define	APBH_CTRL2_CH14_ERROR_IRQ			(1 << 14)
#define	APBH_CTRL2_CH13_ERROR_IRQ			(1 << 13)
#define	APBH_CTRL2_CH12_ERROR_IRQ			(1 << 12)
#define	APBH_CTRL2_CH11_ERROR_IRQ			(1 << 11)
#define	APBH_CTRL2_CH10_ERROR_IRQ			(1 << 10)
#define	APBH_CTRL2_CH9_ERROR_IRQ			(1 << 9)
#define	APBH_CTRL2_CH8_ERROR_IRQ			(1 << 8)
#define	APBH_CTRL2_CH7_ERROR_IRQ			(1 << 7)
#define	APBH_CTRL2_CH6_ERROR_IRQ			(1 << 6)
#define	APBH_CTRL2_CH5_ERROR_IRQ			(1 << 5)
#define	APBH_CTRL2_CH4_ERROR_IRQ			(1 << 4)
#define	APBH_CTRL2_CH3_ERROR_IRQ			(1 << 3)
#define	APBH_CTRL2_CH2_ERROR_IRQ			(1 << 2)
#define	APBH_CTRL2_CH1_ERROR_IRQ			(1 << 1)
#define	APBH_CTRL2_CH0_ERROR_IRQ			(1 << 0)

#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK		(0xffff << 16)
#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET		16
#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP0		(0x0001 << 16)
#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP1		(0x0002 << 16)
#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP2		(0x0004 << 16)
#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP3		(0x0008 << 16)
#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND0		(0x0010 << 16)
#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND1		(0x0020 << 16)
#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND2		(0x0040 << 16)
#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND3		(0x0080 << 16)
#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND4		(0x0100 << 16)
#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND5		(0x0200 << 16)
#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND6		(0x0400 << 16)
#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND7		(0x0800 << 16)
#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_HSADC		(0x1000 << 16)
#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_LCDIF		(0x2000 << 16)
#define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK		0xffff
#define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_OFFSET		0
#define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP0		0x0001
#define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP1		0x0002
#define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP2		0x0004
#define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP3		0x0008
#define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND0		0x0010
#define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND1		0x0020
#define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND2		0x0040
#define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND3		0x0080
#define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND4		0x0100
#define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND5		0x0200
#define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND6		0x0400
#define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND7		0x0800
#define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_HSADC		0x1000
#define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF		0x2000

#define	APBH_DEVSEL_CH15_MASK				(0x3 << 30)
#define	APBH_DEVSEL_CH15_OFFSET				30
#define	APBH_DEVSEL_CH14_MASK				(0x3 << 28)
#define	APBH_DEVSEL_CH14_OFFSET				28
#define	APBH_DEVSEL_CH13_MASK				(0x3 << 26)
#define	APBH_DEVSEL_CH13_OFFSET				26
#define	APBH_DEVSEL_CH12_MASK				(0x3 << 24)
#define	APBH_DEVSEL_CH12_OFFSET				24
#define	APBH_DEVSEL_CH11_MASK				(0x3 << 22)
#define	APBH_DEVSEL_CH11_OFFSET				22
#define	APBH_DEVSEL_CH10_MASK				(0x3 << 20)
#define	APBH_DEVSEL_CH10_OFFSET				20
#define	APBH_DEVSEL_CH9_MASK				(0x3 << 18)
#define	APBH_DEVSEL_CH9_OFFSET				18
#define	APBH_DEVSEL_CH8_MASK				(0x3 << 16)
#define	APBH_DEVSEL_CH8_OFFSET				16
#define	APBH_DEVSEL_CH7_MASK				(0x3 << 14)
#define	APBH_DEVSEL_CH7_OFFSET				14
#define	APBH_DEVSEL_CH6_MASK				(0x3 << 12)
#define	APBH_DEVSEL_CH6_OFFSET				12
#define	APBH_DEVSEL_CH5_MASK				(0x3 << 10)
#define	APBH_DEVSEL_CH5_OFFSET				10
#define	APBH_DEVSEL_CH4_MASK				(0x3 << 8)
#define	APBH_DEVSEL_CH4_OFFSET				8
#define	APBH_DEVSEL_CH3_MASK				(0x3 << 6)
#define	APBH_DEVSEL_CH3_OFFSET				6
#define	APBH_DEVSEL_CH2_MASK				(0x3 << 4)
#define	APBH_DEVSEL_CH2_OFFSET				4
#define	APBH_DEVSEL_CH1_MASK				(0x3 << 2)
#define	APBH_DEVSEL_CH1_OFFSET				2
#define	APBH_DEVSEL_CH0_MASK				(0x3 << 0)
#define	APBH_DEVSEL_CH0_OFFSET				0

#define	APBH_DMA_BURST_SIZE_CH15_MASK			(0x3 << 30)
#define	APBH_DMA_BURST_SIZE_CH15_OFFSET			30
#define	APBH_DMA_BURST_SIZE_CH14_MASK			(0x3 << 28)
#define	APBH_DMA_BURST_SIZE_CH14_OFFSET			28
#define	APBH_DMA_BURST_SIZE_CH13_MASK			(0x3 << 26)
#define	APBH_DMA_BURST_SIZE_CH13_OFFSET			26
#define	APBH_DMA_BURST_SIZE_CH12_MASK			(0x3 << 24)
#define	APBH_DMA_BURST_SIZE_CH12_OFFSET			24
#define	APBH_DMA_BURST_SIZE_CH11_MASK			(0x3 << 22)
#define	APBH_DMA_BURST_SIZE_CH11_OFFSET			22
#define	APBH_DMA_BURST_SIZE_CH10_MASK			(0x3 << 20)
#define	APBH_DMA_BURST_SIZE_CH10_OFFSET			20
#define	APBH_DMA_BURST_SIZE_CH9_MASK			(0x3 << 18)
#define	APBH_DMA_BURST_SIZE_CH9_OFFSET			18
#define	APBH_DMA_BURST_SIZE_CH8_MASK			(0x3 << 16)
#define	APBH_DMA_BURST_SIZE_CH8_OFFSET			16
#define	APBH_DMA_BURST_SIZE_CH8_BURST0			(0x0 << 16)
#define	APBH_DMA_BURST_SIZE_CH8_BURST4			(0x1 << 16)
#define	APBH_DMA_BURST_SIZE_CH8_BURST8			(0x2 << 16)
#define	APBH_DMA_BURST_SIZE_CH7_MASK			(0x3 << 14)
#define	APBH_DMA_BURST_SIZE_CH7_OFFSET			14
#define	APBH_DMA_BURST_SIZE_CH6_MASK			(0x3 << 12)
#define	APBH_DMA_BURST_SIZE_CH6_OFFSET			12
#define	APBH_DMA_BURST_SIZE_CH5_MASK			(0x3 << 10)
#define	APBH_DMA_BURST_SIZE_CH5_OFFSET			10
#define	APBH_DMA_BURST_SIZE_CH4_MASK			(0x3 << 8)
#define	APBH_DMA_BURST_SIZE_CH4_OFFSET			8
#define	APBH_DMA_BURST_SIZE_CH3_MASK			(0x3 << 6)
#define	APBH_DMA_BURST_SIZE_CH3_OFFSET			6
#define	APBH_DMA_BURST_SIZE_CH3_BURST0			(0x0 << 6)
#define	APBH_DMA_BURST_SIZE_CH3_BURST4			(0x1 << 6)
#define	APBH_DMA_BURST_SIZE_CH3_BURST8			(0x2 << 6)

#define	APBH_DMA_BURST_SIZE_CH2_MASK			(0x3 << 4)
#define	APBH_DMA_BURST_SIZE_CH2_OFFSET			4
#define	APBH_DMA_BURST_SIZE_CH2_BURST0			(0x0 << 4)
#define	APBH_DMA_BURST_SIZE_CH2_BURST4			(0x1 << 4)
#define	APBH_DMA_BURST_SIZE_CH2_BURST8			(0x2 << 4)
#define	APBH_DMA_BURST_SIZE_CH1_MASK			(0x3 << 2)
#define	APBH_DMA_BURST_SIZE_CH1_OFFSET			2
#define	APBH_DMA_BURST_SIZE_CH1_BURST0			(0x0 << 2)
#define	APBH_DMA_BURST_SIZE_CH1_BURST4			(0x1 << 2)
#define	APBH_DMA_BURST_SIZE_CH1_BURST8			(0x2 << 2)

#define	APBH_DMA_BURST_SIZE_CH0_MASK			0x3
#define	APBH_DMA_BURST_SIZE_CH0_OFFSET			0
#define	APBH_DMA_BURST_SIZE_CH0_BURST0			0x0
#define	APBH_DMA_BURST_SIZE_CH0_BURST4			0x1
#define	APBH_DMA_BURST_SIZE_CH0_BURST8			0x2

#define	APBH_DEBUG_GPMI_ONE_FIFO			(1 << 0)

#define	APBH_CHn_CURCMDAR_CMD_ADDR_MASK			0xffffffff
#define	APBH_CHn_CURCMDAR_CMD_ADDR_OFFSET		0

#define	APBH_CHn_NXTCMDAR_CMD_ADDR_MASK			0xffffffff
#define	APBH_CHn_NXTCMDAR_CMD_ADDR_OFFSET		0

#define	APBH_CHn_CMD_XFER_COUNT_MASK			(0xffff << 16)
#define	APBH_CHn_CMD_XFER_COUNT_OFFSET			16
#define	APBH_CHn_CMD_CMDWORDS_MASK			(0xf << 12)
#define	APBH_CHn_CMD_CMDWORDS_OFFSET			12
#define	APBH_CHn_CMD_HALTONTERMINATE			(1 << 8)
#define	APBH_CHn_CMD_WAIT4ENDCMD			(1 << 7)
#define	APBH_CHn_CMD_SEMAPHORE				(1 << 6)
#define	APBH_CHn_CMD_NANDWAIT4READY			(1 << 5)
#define	APBH_CHn_CMD_NANDLOCK				(1 << 4)
#define	APBH_CHn_CMD_IRQONCMPLT				(1 << 3)
#define	APBH_CHn_CMD_CHAIN				(1 << 2)
#define	APBH_CHn_CMD_COMMAND_MASK			0x3
#define	APBH_CHn_CMD_COMMAND_OFFSET			0
#define	APBH_CHn_CMD_COMMAND_NO_DMA_XFER		0x0
#define	APBH_CHn_CMD_COMMAND_DMA_WRITE			0x1
#define	APBH_CHn_CMD_COMMAND_DMA_READ			0x2
#define	APBH_CHn_CMD_COMMAND_DMA_SENSE			0x3

#define	APBH_CHn_BAR_ADDRESS_MASK			0xffffffff
#define	APBH_CHn_BAR_ADDRESS_OFFSET			0

#define	APBH_CHn_SEMA_RSVD2_MASK			(0xff << 24)
#define	APBH_CHn_SEMA_RSVD2_OFFSET			24
#define	APBH_CHn_SEMA_PHORE_MASK			(0xff << 16)
#define	APBH_CHn_SEMA_PHORE_OFFSET			16
#define	APBH_CHn_SEMA_RSVD1_MASK			(0xff << 8)
#define	APBH_CHn_SEMA_RSVD1_OFFSET			8
#define	APBH_CHn_SEMA_INCREMENT_SEMA_MASK		(0xff << 0)
#define	APBH_CHn_SEMA_INCREMENT_SEMA_OFFSET		0

#define	APBH_CHn_DEBUG1_REQ				(1 << 31)
#define	APBH_CHn_DEBUG1_BURST				(1 << 30)
#define	APBH_CHn_DEBUG1_KICK				(1 << 29)
#define	APBH_CHn_DEBUG1_END				(1 << 28)
#define	APBH_CHn_DEBUG1_SENSE				(1 << 27)
#define	APBH_CHn_DEBUG1_READY				(1 << 26)
#define	APBH_CHn_DEBUG1_LOCK				(1 << 25)
#define	APBH_CHn_DEBUG1_NEXTCMDADDRVALID		(1 << 24)
#define	APBH_CHn_DEBUG1_RD_FIFO_EMPTY			(1 << 23)
#define	APBH_CHn_DEBUG1_RD_FIFO_FULL			(1 << 22)
#define	APBH_CHn_DEBUG1_WR_FIFO_EMPTY			(1 << 21)
#define	APBH_CHn_DEBUG1_WR_FIFO_FULL			(1 << 20)
#define	APBH_CHn_DEBUG1_RSVD1_MASK			(0x7fff << 5)
#define	APBH_CHn_DEBUG1_RSVD1_OFFSET			5
#define	APBH_CHn_DEBUG1_STATEMACHINE_MASK		0x1f
#define	APBH_CHn_DEBUG1_STATEMACHINE_OFFSET		0
#define	APBH_CHn_DEBUG1_STATEMACHINE_IDLE		0x00
#define	APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD1		0x01
#define	APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD3		0x02
#define	APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD2		0x03
#define	APBH_CHn_DEBUG1_STATEMACHINE_XFER_DECODE	0x04
#define	APBH_CHn_DEBUG1_STATEMACHINE_REQ_WAIT		0x05
#define	APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD4		0x06
#define	APBH_CHn_DEBUG1_STATEMACHINE_PIO_REQ		0x07
#define	APBH_CHn_DEBUG1_STATEMACHINE_READ_FLUSH		0x08
#define	APBH_CHn_DEBUG1_STATEMACHINE_READ_WAIT		0x09
#define	APBH_CHn_DEBUG1_STATEMACHINE_WRITE		0x0c
#define	APBH_CHn_DEBUG1_STATEMACHINE_READ_REQ		0x0d
#define	APBH_CHn_DEBUG1_STATEMACHINE_CHECK_CHAIN	0x0e
#define	APBH_CHn_DEBUG1_STATEMACHINE_XFER_COMPLETE	0x0f
#define	APBH_CHn_DEBUG1_STATEMACHINE_TERMINATE		0x14
#define	APBH_CHn_DEBUG1_STATEMACHINE_WAIT_END		0x15
#define	APBH_CHn_DEBUG1_STATEMACHINE_WRITE_WAIT		0x1c
#define	APBH_CHn_DEBUG1_STATEMACHINE_HALT_AFTER_TERM	0x1d
#define	APBH_CHn_DEBUG1_STATEMACHINE_CHECK_WAIT		0x1e
#define	APBH_CHn_DEBUG1_STATEMACHINE_WAIT_READY		0x1f

#define	APBH_CHn_DEBUG2_APB_BYTES_MASK			(0xffff << 16)
#define	APBH_CHn_DEBUG2_APB_BYTES_OFFSET		16
#define	APBH_CHn_DEBUG2_AHB_BYTES_MASK			0xffff
#define	APBH_CHn_DEBUG2_AHB_BYTES_OFFSET		0

#define	APBH_VERSION_MAJOR_MASK				(0xff << 24)
#define	APBH_VERSION_MAJOR_OFFSET			24
#define	APBH_VERSION_MINOR_MASK				(0xff << 16)
#define	APBH_VERSION_MINOR_OFFSET			16
#define	APBH_VERSION_STEP_MASK				0xffff
#define	APBH_VERSION_STEP_OFFSET			0

#endif	/* __REGS_APBH_H__ */
Commit	Line	Data
31650d64 MV	1	/*
	2	* Freescale i.MX28 APBH Register Definitions
	3	*
	4	* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
	5	* on behalf of DENX Software Engineering GmbH
	6	*
	7	* Based on code from LTIB:
	8	* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; either version 2 of the License, or
	13	* (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	23	*
	24	*/
	25
	26	#ifndef __REGS_APBH_H__
	27	#define __REGS_APBH_H__
	28
	29	#include <asm/arch/regs-common.h>
	30
	31	#ifndef __ASSEMBLY__
	32	struct mx28_apbh_regs {
b228e14e RD	33	mx28_reg_32(hw_apbh_ctrl0)
	34	mx28_reg_32(hw_apbh_ctrl1)
	35	mx28_reg_32(hw_apbh_ctrl2)
	36	mx28_reg_32(hw_apbh_channel_ctrl)
	37	mx28_reg_32(hw_apbh_devsel)
	38	mx28_reg_32(hw_apbh_dma_burst_size)
	39	mx28_reg_32(hw_apbh_debug)
31650d64 MV	40
	41	uint32_t reserved[36];
	42
	43	union {
	44	struct {
b228e14e RD	45	mx28_reg_32(hw_apbh_ch_curcmdar)
	46	mx28_reg_32(hw_apbh_ch_nxtcmdar)
	47	mx28_reg_32(hw_apbh_ch_cmd)
	48	mx28_reg_32(hw_apbh_ch_bar)
	49	mx28_reg_32(hw_apbh_ch_sema)
	50	mx28_reg_32(hw_apbh_ch_debug1)
	51	mx28_reg_32(hw_apbh_ch_debug2)
31650d64 MV	52	} ch[16];
31650d64 MV	53	struct {
b228e14e RD	54	mx28_reg_32(hw_apbh_ch0_curcmdar)
	55	mx28_reg_32(hw_apbh_ch0_nxtcmdar)
	56	mx28_reg_32(hw_apbh_ch0_cmd)
	57	mx28_reg_32(hw_apbh_ch0_bar)
	58	mx28_reg_32(hw_apbh_ch0_sema)
	59	mx28_reg_32(hw_apbh_ch0_debug1)
	60	mx28_reg_32(hw_apbh_ch0_debug2)
	61	mx28_reg_32(hw_apbh_ch1_curcmdar)
	62	mx28_reg_32(hw_apbh_ch1_nxtcmdar)
	63	mx28_reg_32(hw_apbh_ch1_cmd)
	64	mx28_reg_32(hw_apbh_ch1_bar)
	65	mx28_reg_32(hw_apbh_ch1_sema)
	66	mx28_reg_32(hw_apbh_ch1_debug1)
	67	mx28_reg_32(hw_apbh_ch1_debug2)
	68	mx28_reg_32(hw_apbh_ch2_curcmdar)
	69	mx28_reg_32(hw_apbh_ch2_nxtcmdar)
	70	mx28_reg_32(hw_apbh_ch2_cmd)
	71	mx28_reg_32(hw_apbh_ch2_bar)
	72	mx28_reg_32(hw_apbh_ch2_sema)
	73	mx28_reg_32(hw_apbh_ch2_debug1)
	74	mx28_reg_32(hw_apbh_ch2_debug2)
	75	mx28_reg_32(hw_apbh_ch3_curcmdar)
	76	mx28_reg_32(hw_apbh_ch3_nxtcmdar)
	77	mx28_reg_32(hw_apbh_ch3_cmd)
	78	mx28_reg_32(hw_apbh_ch3_bar)
	79	mx28_reg_32(hw_apbh_ch3_sema)
	80	mx28_reg_32(hw_apbh_ch3_debug1)
	81	mx28_reg_32(hw_apbh_ch3_debug2)
	82	mx28_reg_32(hw_apbh_ch4_curcmdar)
	83	mx28_reg_32(hw_apbh_ch4_nxtcmdar)
	84	mx28_reg_32(hw_apbh_ch4_cmd)
	85	mx28_reg_32(hw_apbh_ch4_bar)
	86	mx28_reg_32(hw_apbh_ch4_sema)
	87	mx28_reg_32(hw_apbh_ch4_debug1)
	88	mx28_reg_32(hw_apbh_ch4_debug2)
	89	mx28_reg_32(hw_apbh_ch5_curcmdar)
	90	mx28_reg_32(hw_apbh_ch5_nxtcmdar)
	91	mx28_reg_32(hw_apbh_ch5_cmd)
	92	mx28_reg_32(hw_apbh_ch5_bar)
	93	mx28_reg_32(hw_apbh_ch5_sema)
	94	mx28_reg_32(hw_apbh_ch5_debug1)
	95	mx28_reg_32(hw_apbh_ch5_debug2)
	96	mx28_reg_32(hw_apbh_ch6_curcmdar)
	97	mx28_reg_32(hw_apbh_ch6_nxtcmdar)
	98	mx28_reg_32(hw_apbh_ch6_cmd)
	99	mx28_reg_32(hw_apbh_ch6_bar)
	100	mx28_reg_32(hw_apbh_ch6_sema)
	101	mx28_reg_32(hw_apbh_ch6_debug1)
	102	mx28_reg_32(hw_apbh_ch6_debug2)
	103	mx28_reg_32(hw_apbh_ch7_curcmdar)
	104	mx28_reg_32(hw_apbh_ch7_nxtcmdar)
	105	mx28_reg_32(hw_apbh_ch7_cmd)
	106	mx28_reg_32(hw_apbh_ch7_bar)
	107	mx28_reg_32(hw_apbh_ch7_sema)
	108	mx28_reg_32(hw_apbh_ch7_debug1)
	109	mx28_reg_32(hw_apbh_ch7_debug2)
	110	mx28_reg_32(hw_apbh_ch8_curcmdar)
	111	mx28_reg_32(hw_apbh_ch8_nxtcmdar)
	112	mx28_reg_32(hw_apbh_ch8_cmd)
	113	mx28_reg_32(hw_apbh_ch8_bar)
	114	mx28_reg_32(hw_apbh_ch8_sema)
	115	mx28_reg_32(hw_apbh_ch8_debug1)
	116	mx28_reg_32(hw_apbh_ch8_debug2)
	117	mx28_reg_32(hw_apbh_ch9_curcmdar)
118	mx28_reg_32(hw_apbh_ch9_nxtcmdar)
119	mx28_reg_32(hw_apbh_ch9_cmd)
120	mx28_reg_32(hw_apbh_ch9_bar)
121	mx28_reg_32(hw_apbh_ch9_sema)
122	mx28_reg_32(hw_apbh_ch9_debug1)
123	mx28_reg_32(hw_apbh_ch9_debug2)
124	mx28_reg_32(hw_apbh_ch10_curcmdar)
125	mx28_reg_32(hw_apbh_ch10_nxtcmdar)
126	mx28_reg_32(hw_apbh_ch10_cmd)
127	mx28_reg_32(hw_apbh_ch10_bar)
128	mx28_reg_32(hw_apbh_ch10_sema)
129	mx28_reg_32(hw_apbh_ch10_debug1)
130	mx28_reg_32(hw_apbh_ch10_debug2)
131	mx28_reg_32(hw_apbh_ch11_curcmdar)
132	mx28_reg_32(hw_apbh_ch11_nxtcmdar)
133	mx28_reg_32(hw_apbh_ch11_cmd)
134	mx28_reg_32(hw_apbh_ch11_bar)
135	mx28_reg_32(hw_apbh_ch11_sema)
136	mx28_reg_32(hw_apbh_ch11_debug1)
137	mx28_reg_32(hw_apbh_ch11_debug2)
138	mx28_reg_32(hw_apbh_ch12_curcmdar)
139	mx28_reg_32(hw_apbh_ch12_nxtcmdar)
140	mx28_reg_32(hw_apbh_ch12_cmd)
141	mx28_reg_32(hw_apbh_ch12_bar)
142	mx28_reg_32(hw_apbh_ch12_sema)
143	mx28_reg_32(hw_apbh_ch12_debug1)
144	mx28_reg_32(hw_apbh_ch12_debug2)
145	mx28_reg_32(hw_apbh_ch13_curcmdar)
146	mx28_reg_32(hw_apbh_ch13_nxtcmdar)
147	mx28_reg_32(hw_apbh_ch13_cmd)
148	mx28_reg_32(hw_apbh_ch13_bar)
149	mx28_reg_32(hw_apbh_ch13_sema)
150	mx28_reg_32(hw_apbh_ch13_debug1)
151	mx28_reg_32(hw_apbh_ch13_debug2)
152	mx28_reg_32(hw_apbh_ch14_curcmdar)
153	mx28_reg_32(hw_apbh_ch14_nxtcmdar)
154	mx28_reg_32(hw_apbh_ch14_cmd)
155	mx28_reg_32(hw_apbh_ch14_bar)
156	mx28_reg_32(hw_apbh_ch14_sema)
157	mx28_reg_32(hw_apbh_ch14_debug1)
158	mx28_reg_32(hw_apbh_ch14_debug2)
159	mx28_reg_32(hw_apbh_ch15_curcmdar)
160	mx28_reg_32(hw_apbh_ch15_nxtcmdar)
161	mx28_reg_32(hw_apbh_ch15_cmd)
162	mx28_reg_32(hw_apbh_ch15_bar)
163	mx28_reg_32(hw_apbh_ch15_sema)
164	mx28_reg_32(hw_apbh_ch15_debug1)
165	mx28_reg_32(hw_apbh_ch15_debug2)
31650d64 MV	166	};
31650d64 MV	167	};
b228e14e	168	mx28_reg_32(hw_apbh_version)
31650d64 MV	169	};
	170	#endif
	171
	172	#define APBH_CTRL0_SFTRST (1 << 31)
	173	#define APBH_CTRL0_CLKGATE (1 << 30)
	174	#define APBH_CTRL0_AHB_BURST8_EN (1 << 29)
	175	#define APBH_CTRL0_APB_BURST_EN (1 << 28)
	176	#define APBH_CTRL0_RSVD0_MASK (0xfff << 16)
	177	#define APBH_CTRL0_RSVD0_OFFSET 16
	178	#define APBH_CTRL0_CLKGATE_CHANNEL_MASK 0xffff
	179	#define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 0
	180	#define APBH_CTRL0_CLKGATE_CHANNEL_SSP0 0x0001
	181	#define APBH_CTRL0_CLKGATE_CHANNEL_SSP1 0x0002
	182	#define APBH_CTRL0_CLKGATE_CHANNEL_SSP2 0x0004
	183	#define APBH_CTRL0_CLKGATE_CHANNEL_SSP3 0x0008
	184	#define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x0010
	185	#define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x0020
	186	#define APBH_CTRL0_CLKGATE_CHANNEL_NAND2 0x0040
	187	#define APBH_CTRL0_CLKGATE_CHANNEL_NAND3 0x0080
	188	#define APBH_CTRL0_CLKGATE_CHANNEL_NAND4 0x0100
	189	#define APBH_CTRL0_CLKGATE_CHANNEL_NAND5 0x0200
	190	#define APBH_CTRL0_CLKGATE_CHANNEL_NAND6 0x0400
	191	#define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0800
	192	#define APBH_CTRL0_CLKGATE_CHANNEL_HSADC 0x1000
	193	#define APBH_CTRL0_CLKGATE_CHANNEL_LCDIF 0x2000
	194
	195	#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN (1 << 31)
	196	#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN (1 << 30)
	197	#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN (1 << 29)
	198	#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN (1 << 28)
	199	#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN (1 << 27)
	200	#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN (1 << 26)
	201	#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN (1 << 25)
	202	#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN (1 << 24)
	203	#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN (1 << 23)
	204	#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN (1 << 22)
	205	#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN (1 << 21)
	206	#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN (1 << 20)
	207	#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN (1 << 19)
	208	#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN (1 << 18)
	209	#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN (1 << 17)
	210	#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN (1 << 16)
	211	#define APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_OFFSET 16
	212	#define APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_MASK (0xffff << 16)
	213	#define APBH_CTRL1_CH15_CMDCMPLT_IRQ (1 << 15)
	214	#define APBH_CTRL1_CH14_CMDCMPLT_IRQ (1 << 14)
	215	#define APBH_CTRL1_CH13_CMDCMPLT_IRQ (1 << 13)
	216	#define APBH_CTRL1_CH12_CMDCMPLT_IRQ (1 << 12)
	217	#define APBH_CTRL1_CH11_CMDCMPLT_IRQ (1 << 11)
	218	#define APBH_CTRL1_CH10_CMDCMPLT_IRQ (1 << 10)
	219	#define APBH_CTRL1_CH9_CMDCMPLT_IRQ (1 << 9)
	220	#define APBH_CTRL1_CH8_CMDCMPLT_IRQ (1 << 8)
	221	#define APBH_CTRL1_CH7_CMDCMPLT_IRQ (1 << 7)
	222	#define APBH_CTRL1_CH6_CMDCMPLT_IRQ (1 << 6)
	223	#define APBH_CTRL1_CH5_CMDCMPLT_IRQ (1 << 5)
	224	#define APBH_CTRL1_CH4_CMDCMPLT_IRQ (1 << 4)
	225	#define APBH_CTRL1_CH3_CMDCMPLT_IRQ (1 << 3)
	226	#define APBH_CTRL1_CH2_CMDCMPLT_IRQ (1 << 2)
	227	#define APBH_CTRL1_CH1_CMDCMPLT_IRQ (1 << 1)
	228	#define APBH_CTRL1_CH0_CMDCMPLT_IRQ (1 << 0)
	229
	230	#define APBH_CTRL2_CH15_ERROR_STATUS (1 << 31)
	231	#define APBH_CTRL2_CH14_ERROR_STATUS (1 << 30)
	232	#define APBH_CTRL2_CH13_ERROR_STATUS (1 << 29)
233	#define APBH_CTRL2_CH12_ERROR_STATUS (1 << 28)
234	#define APBH_CTRL2_CH11_ERROR_STATUS (1 << 27)
235	#define APBH_CTRL2_CH10_ERROR_STATUS (1 << 26)
236	#define APBH_CTRL2_CH9_ERROR_STATUS (1 << 25)
237	#define APBH_CTRL2_CH8_ERROR_STATUS (1 << 24)
238	#define APBH_CTRL2_CH7_ERROR_STATUS (1 << 23)
239	#define APBH_CTRL2_CH6_ERROR_STATUS (1 << 22)
240	#define APBH_CTRL2_CH5_ERROR_STATUS (1 << 21)
241	#define APBH_CTRL2_CH4_ERROR_STATUS (1 << 20)
242	#define APBH_CTRL2_CH3_ERROR_STATUS (1 << 19)
243	#define APBH_CTRL2_CH2_ERROR_STATUS (1 << 18)
244	#define APBH_CTRL2_CH1_ERROR_STATUS (1 << 17)
245	#define APBH_CTRL2_CH0_ERROR_STATUS (1 << 16)
246	#define APBH_CTRL2_CH15_ERROR_IRQ (1 << 15)
247	#define APBH_CTRL2_CH14_ERROR_IRQ (1 << 14)
248	#define APBH_CTRL2_CH13_ERROR_IRQ (1 << 13)
249	#define APBH_CTRL2_CH12_ERROR_IRQ (1 << 12)
250	#define APBH_CTRL2_CH11_ERROR_IRQ (1 << 11)
251	#define APBH_CTRL2_CH10_ERROR_IRQ (1 << 10)
252	#define APBH_CTRL2_CH9_ERROR_IRQ (1 << 9)
253	#define APBH_CTRL2_CH8_ERROR_IRQ (1 << 8)
254	#define APBH_CTRL2_CH7_ERROR_IRQ (1 << 7)
255	#define APBH_CTRL2_CH6_ERROR_IRQ (1 << 6)
256	#define APBH_CTRL2_CH5_ERROR_IRQ (1 << 5)
257	#define APBH_CTRL2_CH4_ERROR_IRQ (1 << 4)
258	#define APBH_CTRL2_CH3_ERROR_IRQ (1 << 3)
259	#define APBH_CTRL2_CH2_ERROR_IRQ (1 << 2)
260	#define APBH_CTRL2_CH1_ERROR_IRQ (1 << 1)
261	#define APBH_CTRL2_CH0_ERROR_IRQ (1 << 0)
262
263	#define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK (0xffff << 16)
264	#define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16
265	#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP0 (0x0001 << 16)
266	#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP1 (0x0002 << 16)
267	#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP2 (0x0004 << 16)
268	#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP3 (0x0008 << 16)
269	#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND0 (0x0010 << 16)
270	#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND1 (0x0020 << 16)
271	#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND2 (0x0040 << 16)
272	#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND3 (0x0080 << 16)
273	#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND4 (0x0100 << 16)
274	#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND5 (0x0200 << 16)
275	#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND6 (0x0400 << 16)
276	#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND7 (0x0800 << 16)
277	#define APBH_CHANNEL_CTRL_RESET_CHANNEL_HSADC (0x1000 << 16)
278	#define APBH_CHANNEL_CTRL_RESET_CHANNEL_LCDIF (0x2000 << 16)
279	#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK 0xffff
280	#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_OFFSET 0
281	#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP0 0x0001
282	#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP1 0x0002
283	#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP2 0x0004
284	#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP3 0x0008
285	#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND0 0x0010
286	#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND1 0x0020
287	#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND2 0x0040
288	#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND3 0x0080
289	#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND4 0x0100
290	#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND5 0x0200
291	#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND6 0x0400
292	#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND7 0x0800
293	#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_HSADC 0x1000
294	#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF 0x2000
295
296	#define APBH_DEVSEL_CH15_MASK (0x3 << 30)
297	#define APBH_DEVSEL_CH15_OFFSET 30
298	#define APBH_DEVSEL_CH14_MASK (0x3 << 28)
299	#define APBH_DEVSEL_CH14_OFFSET 28
300	#define APBH_DEVSEL_CH13_MASK (0x3 << 26)
301	#define APBH_DEVSEL_CH13_OFFSET 26
302	#define APBH_DEVSEL_CH12_MASK (0x3 << 24)
303	#define APBH_DEVSEL_CH12_OFFSET 24
304	#define APBH_DEVSEL_CH11_MASK (0x3 << 22)
305	#define APBH_DEVSEL_CH11_OFFSET 22
306	#define APBH_DEVSEL_CH10_MASK (0x3 << 20)
307	#define APBH_DEVSEL_CH10_OFFSET 20
308	#define APBH_DEVSEL_CH9_MASK (0x3 << 18)
309	#define APBH_DEVSEL_CH9_OFFSET 18
310	#define APBH_DEVSEL_CH8_MASK (0x3 << 16)
311	#define APBH_DEVSEL_CH8_OFFSET 16
312	#define APBH_DEVSEL_CH7_MASK (0x3 << 14)
313	#define APBH_DEVSEL_CH7_OFFSET 14
314	#define APBH_DEVSEL_CH6_MASK (0x3 << 12)
315	#define APBH_DEVSEL_CH6_OFFSET 12
316	#define APBH_DEVSEL_CH5_MASK (0x3 << 10)
317	#define APBH_DEVSEL_CH5_OFFSET 10
318	#define APBH_DEVSEL_CH4_MASK (0x3 << 8)
319	#define APBH_DEVSEL_CH4_OFFSET 8
320	#define APBH_DEVSEL_CH3_MASK (0x3 << 6)
321	#define APBH_DEVSEL_CH3_OFFSET 6
322	#define APBH_DEVSEL_CH2_MASK (0x3 << 4)
323	#define APBH_DEVSEL_CH2_OFFSET 4
324	#define APBH_DEVSEL_CH1_MASK (0x3 << 2)
325	#define APBH_DEVSEL_CH1_OFFSET 2
326	#define APBH_DEVSEL_CH0_MASK (0x3 << 0)
327	#define APBH_DEVSEL_CH0_OFFSET 0
328
329	#define APBH_DMA_BURST_SIZE_CH15_MASK (0x3 << 30)
330	#define APBH_DMA_BURST_SIZE_CH15_OFFSET 30
331	#define APBH_DMA_BURST_SIZE_CH14_MASK (0x3 << 28)
332	#define APBH_DMA_BURST_SIZE_CH14_OFFSET 28
333	#define APBH_DMA_BURST_SIZE_CH13_MASK (0x3 << 26)
334	#define APBH_DMA_BURST_SIZE_CH13_OFFSET 26
335	#define APBH_DMA_BURST_SIZE_CH12_MASK (0x3 << 24)
336	#define APBH_DMA_BURST_SIZE_CH12_OFFSET 24
337	#define APBH_DMA_BURST_SIZE_CH11_MASK (0x3 << 22)
338	#define APBH_DMA_BURST_SIZE_CH11_OFFSET 22
339	#define APBH_DMA_BURST_SIZE_CH10_MASK (0x3 << 20)
340	#define APBH_DMA_BURST_SIZE_CH10_OFFSET 20
341	#define APBH_DMA_BURST_SIZE_CH9_MASK (0x3 << 18)
342	#define APBH_DMA_BURST_SIZE_CH9_OFFSET 18
343	#define APBH_DMA_BURST_SIZE_CH8_MASK (0x3 << 16)
344	#define APBH_DMA_BURST_SIZE_CH8_OFFSET 16
345	#define APBH_DMA_BURST_SIZE_CH8_BURST0 (0x0 << 16)
346	#define APBH_DMA_BURST_SIZE_CH8_BURST4 (0x1 << 16)
347	#define APBH_DMA_BURST_SIZE_CH8_BURST8 (0x2 << 16)
348	#define APBH_DMA_BURST_SIZE_CH7_MASK (0x3 << 14)
349	#define APBH_DMA_BURST_SIZE_CH7_OFFSET 14
350	#define APBH_DMA_BURST_SIZE_CH6_MASK (0x3 << 12)
351	#define APBH_DMA_BURST_SIZE_CH6_OFFSET 12
352	#define APBH_DMA_BURST_SIZE_CH5_MASK (0x3 << 10)
353	#define APBH_DMA_BURST_SIZE_CH5_OFFSET 10
354	#define APBH_DMA_BURST_SIZE_CH4_MASK (0x3 << 8)
355	#define APBH_DMA_BURST_SIZE_CH4_OFFSET 8
356	#define APBH_DMA_BURST_SIZE_CH3_MASK (0x3 << 6)
357	#define APBH_DMA_BURST_SIZE_CH3_OFFSET 6
358	#define APBH_DMA_BURST_SIZE_CH3_BURST0 (0x0 << 6)
359	#define APBH_DMA_BURST_SIZE_CH3_BURST4 (0x1 << 6)
360	#define APBH_DMA_BURST_SIZE_CH3_BURST8 (0x2 << 6)
361
362	#define APBH_DMA_BURST_SIZE_CH2_MASK (0x3 << 4)
363	#define APBH_DMA_BURST_SIZE_CH2_OFFSET 4
364	#define APBH_DMA_BURST_SIZE_CH2_BURST0 (0x0 << 4)
365	#define APBH_DMA_BURST_SIZE_CH2_BURST4 (0x1 << 4)
366	#define APBH_DMA_BURST_SIZE_CH2_BURST8 (0x2 << 4)
367	#define APBH_DMA_BURST_SIZE_CH1_MASK (0x3 << 2)
368	#define APBH_DMA_BURST_SIZE_CH1_OFFSET 2
369	#define APBH_DMA_BURST_SIZE_CH1_BURST0 (0x0 << 2)
370	#define APBH_DMA_BURST_SIZE_CH1_BURST4 (0x1 << 2)
371	#define APBH_DMA_BURST_SIZE_CH1_BURST8 (0x2 << 2)
372
373	#define APBH_DMA_BURST_SIZE_CH0_MASK 0x3
374	#define APBH_DMA_BURST_SIZE_CH0_OFFSET 0
375	#define APBH_DMA_BURST_SIZE_CH0_BURST0 0x0
376	#define APBH_DMA_BURST_SIZE_CH0_BURST4 0x1
377	#define APBH_DMA_BURST_SIZE_CH0_BURST8 0x2
378
379	#define APBH_DEBUG_GPMI_ONE_FIFO (1 << 0)
380
381	#define APBH_CHn_CURCMDAR_CMD_ADDR_MASK 0xffffffff
382	#define APBH_CHn_CURCMDAR_CMD_ADDR_OFFSET 0
383
384	#define APBH_CHn_NXTCMDAR_CMD_ADDR_MASK 0xffffffff
385	#define APBH_CHn_NXTCMDAR_CMD_ADDR_OFFSET 0
386
387	#define APBH_CHn_CMD_XFER_COUNT_MASK (0xffff << 16)
388	#define APBH_CHn_CMD_XFER_COUNT_OFFSET 16
389	#define APBH_CHn_CMD_CMDWORDS_MASK (0xf << 12)
390	#define APBH_CHn_CMD_CMDWORDS_OFFSET 12
391	#define APBH_CHn_CMD_HALTONTERMINATE (1 << 8)
392	#define APBH_CHn_CMD_WAIT4ENDCMD (1 << 7)
393	#define APBH_CHn_CMD_SEMAPHORE (1 << 6)
394	#define APBH_CHn_CMD_NANDWAIT4READY (1 << 5)
395	#define APBH_CHn_CMD_NANDLOCK (1 << 4)
396	#define APBH_CHn_CMD_IRQONCMPLT (1 << 3)
397	#define APBH_CHn_CMD_CHAIN (1 << 2)
398	#define APBH_CHn_CMD_COMMAND_MASK 0x3
399	#define APBH_CHn_CMD_COMMAND_OFFSET 0
400	#define APBH_CHn_CMD_COMMAND_NO_DMA_XFER 0x0
401	#define APBH_CHn_CMD_COMMAND_DMA_WRITE 0x1
402	#define APBH_CHn_CMD_COMMAND_DMA_READ 0x2
403	#define APBH_CHn_CMD_COMMAND_DMA_SENSE 0x3
404
405	#define APBH_CHn_BAR_ADDRESS_MASK 0xffffffff
406	#define APBH_CHn_BAR_ADDRESS_OFFSET 0
407
408	#define APBH_CHn_SEMA_RSVD2_MASK (0xff << 24)
409	#define APBH_CHn_SEMA_RSVD2_OFFSET 24
410	#define APBH_CHn_SEMA_PHORE_MASK (0xff << 16)
411	#define APBH_CHn_SEMA_PHORE_OFFSET 16
412	#define APBH_CHn_SEMA_RSVD1_MASK (0xff << 8)
413	#define APBH_CHn_SEMA_RSVD1_OFFSET 8
414	#define APBH_CHn_SEMA_INCREMENT_SEMA_MASK (0xff << 0)
415	#define APBH_CHn_SEMA_INCREMENT_SEMA_OFFSET 0
416
417	#define APBH_CHn_DEBUG1_REQ (1 << 31)
418	#define APBH_CHn_DEBUG1_BURST (1 << 30)
419	#define APBH_CHn_DEBUG1_KICK (1 << 29)
420	#define APBH_CHn_DEBUG1_END (1 << 28)
421	#define APBH_CHn_DEBUG1_SENSE (1 << 27)
422	#define APBH_CHn_DEBUG1_READY (1 << 26)
423	#define APBH_CHn_DEBUG1_LOCK (1 << 25)
424	#define APBH_CHn_DEBUG1_NEXTCMDADDRVALID (1 << 24)
425	#define APBH_CHn_DEBUG1_RD_FIFO_EMPTY (1 << 23)
426	#define APBH_CHn_DEBUG1_RD_FIFO_FULL (1 << 22)
427	#define APBH_CHn_DEBUG1_WR_FIFO_EMPTY (1 << 21)
428	#define APBH_CHn_DEBUG1_WR_FIFO_FULL (1 << 20)
429	#define APBH_CHn_DEBUG1_RSVD1_MASK (0x7fff << 5)
430	#define APBH_CHn_DEBUG1_RSVD1_OFFSET 5
431	#define APBH_CHn_DEBUG1_STATEMACHINE_MASK 0x1f
432	#define APBH_CHn_DEBUG1_STATEMACHINE_OFFSET 0
433	#define APBH_CHn_DEBUG1_STATEMACHINE_IDLE 0x00
434	#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD1 0x01
435	#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD3 0x02
436	#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD2 0x03
437	#define APBH_CHn_DEBUG1_STATEMACHINE_XFER_DECODE 0x04
438	#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_WAIT 0x05
439	#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD4 0x06
440	#define APBH_CHn_DEBUG1_STATEMACHINE_PIO_REQ 0x07
441	#define APBH_CHn_DEBUG1_STATEMACHINE_READ_FLUSH 0x08
442	#define APBH_CHn_DEBUG1_STATEMACHINE_READ_WAIT 0x09
443	#define APBH_CHn_DEBUG1_STATEMACHINE_WRITE 0x0c
444	#define APBH_CHn_DEBUG1_STATEMACHINE_READ_REQ 0x0d
445	#define APBH_CHn_DEBUG1_STATEMACHINE_CHECK_CHAIN 0x0e
446	#define APBH_CHn_DEBUG1_STATEMACHINE_XFER_COMPLETE 0x0f
447	#define APBH_CHn_DEBUG1_STATEMACHINE_TERMINATE 0x14
448	#define APBH_CHn_DEBUG1_STATEMACHINE_WAIT_END 0x15
449	#define APBH_CHn_DEBUG1_STATEMACHINE_WRITE_WAIT 0x1c
450	#define APBH_CHn_DEBUG1_STATEMACHINE_HALT_AFTER_TERM 0x1d
451	#define APBH_CHn_DEBUG1_STATEMACHINE_CHECK_WAIT 0x1e
452	#define APBH_CHn_DEBUG1_STATEMACHINE_WAIT_READY 0x1f
453
454	#define APBH_CHn_DEBUG2_APB_BYTES_MASK (0xffff << 16)
455	#define APBH_CHn_DEBUG2_APB_BYTES_OFFSET 16
456	#define APBH_CHn_DEBUG2_AHB_BYTES_MASK 0xffff
457	#define APBH_CHn_DEBUG2_AHB_BYTES_OFFSET 0
458
459	#define APBH_VERSION_MAJOR_MASK (0xff << 24)
460	#define APBH_VERSION_MAJOR_OFFSET 24
461	#define APBH_VERSION_MINOR_MASK (0xff << 16)
462	#define APBH_VERSION_MINOR_OFFSET 16
463	#define APBH_VERSION_STEP_MASK 0xffff
464	#define APBH_VERSION_STEP_OFFSET 0
465
466	#endif /* __REGS_APBH_H__ */