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6e9a0a39 MV |
1 | /* |
2 | * Freescale i.MX28 SSP Register Definitions | |
3 | * | |
4 | * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> | |
5 | * | |
6 | * Based on code from LTIB: | |
7 | * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | */ | |
24 | ||
25 | #ifndef __MX28_REGS_SSP_H__ | |
26 | #define __MX28_REGS_SSP_H__ | |
27 | ||
28 | #include <asm/arch/regs-common.h> | |
29 | ||
30 | #ifndef __ASSEMBLY__ | |
31 | struct mx28_ssp_regs { | |
b228e14e RD |
32 | mx28_reg_32(hw_ssp_ctrl0) |
33 | mx28_reg_32(hw_ssp_cmd0) | |
34 | mx28_reg_32(hw_ssp_cmd1) | |
35 | mx28_reg_32(hw_ssp_xfer_size) | |
36 | mx28_reg_32(hw_ssp_block_size) | |
37 | mx28_reg_32(hw_ssp_compref) | |
38 | mx28_reg_32(hw_ssp_compmask) | |
39 | mx28_reg_32(hw_ssp_timing) | |
40 | mx28_reg_32(hw_ssp_ctrl1) | |
41 | mx28_reg_32(hw_ssp_data) | |
42 | mx28_reg_32(hw_ssp_sdresp0) | |
43 | mx28_reg_32(hw_ssp_sdresp1) | |
44 | mx28_reg_32(hw_ssp_sdresp2) | |
45 | mx28_reg_32(hw_ssp_sdresp3) | |
46 | mx28_reg_32(hw_ssp_ddr_ctrl) | |
47 | mx28_reg_32(hw_ssp_dll_ctrl) | |
48 | mx28_reg_32(hw_ssp_status) | |
49 | mx28_reg_32(hw_ssp_dll_sts) | |
50 | mx28_reg_32(hw_ssp_debug) | |
51 | mx28_reg_32(hw_ssp_version) | |
6e9a0a39 MV |
52 | }; |
53 | #endif | |
54 | ||
55 | #define SSP_CTRL0_SFTRST (1 << 31) | |
56 | #define SSP_CTRL0_CLKGATE (1 << 30) | |
57 | #define SSP_CTRL0_RUN (1 << 29) | |
58 | #define SSP_CTRL0_SDIO_IRQ_CHECK (1 << 28) | |
59 | #define SSP_CTRL0_LOCK_CS (1 << 27) | |
60 | #define SSP_CTRL0_IGNORE_CRC (1 << 26) | |
61 | #define SSP_CTRL0_READ (1 << 25) | |
62 | #define SSP_CTRL0_DATA_XFER (1 << 24) | |
63 | #define SSP_CTRL0_BUS_WIDTH_MASK (0x3 << 22) | |
64 | #define SSP_CTRL0_BUS_WIDTH_OFFSET 22 | |
65 | #define SSP_CTRL0_BUS_WIDTH_ONE_BIT (0x0 << 22) | |
66 | #define SSP_CTRL0_BUS_WIDTH_FOUR_BIT (0x1 << 22) | |
67 | #define SSP_CTRL0_BUS_WIDTH_EIGHT_BIT (0x2 << 22) | |
68 | #define SSP_CTRL0_WAIT_FOR_IRQ (1 << 21) | |
69 | #define SSP_CTRL0_WAIT_FOR_CMD (1 << 20) | |
70 | #define SSP_CTRL0_LONG_RESP (1 << 19) | |
71 | #define SSP_CTRL0_CHECK_RESP (1 << 18) | |
72 | #define SSP_CTRL0_GET_RESP (1 << 17) | |
73 | #define SSP_CTRL0_ENABLE (1 << 16) | |
74 | ||
75 | #define SSP_CMD0_SOFT_TERMINATE (1 << 26) | |
76 | #define SSP_CMD0_DBL_DATA_RATE_EN (1 << 25) | |
77 | #define SSP_CMD0_PRIM_BOOT_OP_EN (1 << 24) | |
78 | #define SSP_CMD0_BOOT_ACK_EN (1 << 23) | |
79 | #define SSP_CMD0_SLOW_CLKING_EN (1 << 22) | |
80 | #define SSP_CMD0_CONT_CLKING_EN (1 << 21) | |
81 | #define SSP_CMD0_APPEND_8CYC (1 << 20) | |
82 | #define SSP_CMD0_CMD_MASK 0xff | |
83 | #define SSP_CMD0_CMD_OFFSET 0 | |
84 | #define SSP_CMD0_CMD_MMC_GO_IDLE_STATE 0x00 | |
85 | #define SSP_CMD0_CMD_MMC_SEND_OP_COND 0x01 | |
86 | #define SSP_CMD0_CMD_MMC_ALL_SEND_CID 0x02 | |
87 | #define SSP_CMD0_CMD_MMC_SET_RELATIVE_ADDR 0x03 | |
88 | #define SSP_CMD0_CMD_MMC_SET_DSR 0x04 | |
89 | #define SSP_CMD0_CMD_MMC_RESERVED_5 0x05 | |
90 | #define SSP_CMD0_CMD_MMC_SWITCH 0x06 | |
91 | #define SSP_CMD0_CMD_MMC_SELECT_DESELECT_CARD 0x07 | |
92 | #define SSP_CMD0_CMD_MMC_SEND_EXT_CSD 0x08 | |
93 | #define SSP_CMD0_CMD_MMC_SEND_CSD 0x09 | |
94 | #define SSP_CMD0_CMD_MMC_SEND_CID 0x0a | |
95 | #define SSP_CMD0_CMD_MMC_READ_DAT_UNTIL_STOP 0x0b | |
96 | #define SSP_CMD0_CMD_MMC_STOP_TRANSMISSION 0x0c | |
97 | #define SSP_CMD0_CMD_MMC_SEND_STATUS 0x0d | |
98 | #define SSP_CMD0_CMD_MMC_BUSTEST_R 0x0e | |
99 | #define SSP_CMD0_CMD_MMC_GO_INACTIVE_STATE 0x0f | |
100 | #define SSP_CMD0_CMD_MMC_SET_BLOCKLEN 0x10 | |
101 | #define SSP_CMD0_CMD_MMC_READ_SINGLE_BLOCK 0x11 | |
102 | #define SSP_CMD0_CMD_MMC_READ_MULTIPLE_BLOCK 0x12 | |
103 | #define SSP_CMD0_CMD_MMC_BUSTEST_W 0x13 | |
104 | #define SSP_CMD0_CMD_MMC_WRITE_DAT_UNTIL_STOP 0x14 | |
105 | #define SSP_CMD0_CMD_MMC_SET_BLOCK_COUNT 0x17 | |
106 | #define SSP_CMD0_CMD_MMC_WRITE_BLOCK 0x18 | |
107 | #define SSP_CMD0_CMD_MMC_WRITE_MULTIPLE_BLOCK 0x19 | |
108 | #define SSP_CMD0_CMD_MMC_PROGRAM_CID 0x1a | |
109 | #define SSP_CMD0_CMD_MMC_PROGRAM_CSD 0x1b | |
110 | #define SSP_CMD0_CMD_MMC_SET_WRITE_PROT 0x1c | |
111 | #define SSP_CMD0_CMD_MMC_CLR_WRITE_PROT 0x1d | |
112 | #define SSP_CMD0_CMD_MMC_SEND_WRITE_PROT 0x1e | |
113 | #define SSP_CMD0_CMD_MMC_ERASE_GROUP_START 0x23 | |
114 | #define SSP_CMD0_CMD_MMC_ERASE_GROUP_END 0x24 | |
115 | #define SSP_CMD0_CMD_MMC_ERASE 0x26 | |
116 | #define SSP_CMD0_CMD_MMC_FAST_IO 0x27 | |
117 | #define SSP_CMD0_CMD_MMC_GO_IRQ_STATE 0x28 | |
118 | #define SSP_CMD0_CMD_MMC_LOCK_UNLOCK 0x2a | |
119 | #define SSP_CMD0_CMD_MMC_APP_CMD 0x37 | |
120 | #define SSP_CMD0_CMD_MMC_GEN_CMD 0x38 | |
121 | #define SSP_CMD0_CMD_SD_GO_IDLE_STATE 0x00 | |
122 | #define SSP_CMD0_CMD_SD_ALL_SEND_CID 0x02 | |
123 | #define SSP_CMD0_CMD_SD_SEND_RELATIVE_ADDR 0x03 | |
124 | #define SSP_CMD0_CMD_SD_SET_DSR 0x04 | |
125 | #define SSP_CMD0_CMD_SD_IO_SEND_OP_COND 0x05 | |
126 | #define SSP_CMD0_CMD_SD_SELECT_DESELECT_CARD 0x07 | |
127 | #define SSP_CMD0_CMD_SD_SEND_CSD 0x09 | |
128 | #define SSP_CMD0_CMD_SD_SEND_CID 0x0a | |
129 | #define SSP_CMD0_CMD_SD_STOP_TRANSMISSION 0x0c | |
130 | #define SSP_CMD0_CMD_SD_SEND_STATUS 0x0d | |
131 | #define SSP_CMD0_CMD_SD_GO_INACTIVE_STATE 0x0f | |
132 | #define SSP_CMD0_CMD_SD_SET_BLOCKLEN 0x10 | |
133 | #define SSP_CMD0_CMD_SD_READ_SINGLE_BLOCK 0x11 | |
134 | #define SSP_CMD0_CMD_SD_READ_MULTIPLE_BLOCK 0x12 | |
135 | #define SSP_CMD0_CMD_SD_WRITE_BLOCK 0x18 | |
136 | #define SSP_CMD0_CMD_SD_WRITE_MULTIPLE_BLOCK 0x19 | |
137 | #define SSP_CMD0_CMD_SD_PROGRAM_CSD 0x1b | |
138 | #define SSP_CMD0_CMD_SD_SET_WRITE_PROT 0x1c | |
139 | #define SSP_CMD0_CMD_SD_CLR_WRITE_PROT 0x1d | |
140 | #define SSP_CMD0_CMD_SD_SEND_WRITE_PROT 0x1e | |
141 | #define SSP_CMD0_CMD_SD_ERASE_WR_BLK_START 0x20 | |
142 | #define SSP_CMD0_CMD_SD_ERASE_WR_BLK_END 0x21 | |
143 | #define SSP_CMD0_CMD_SD_ERASE_GROUP_START 0x23 | |
144 | #define SSP_CMD0_CMD_SD_ERASE_GROUP_END 0x24 | |
145 | #define SSP_CMD0_CMD_SD_ERASE 0x26 | |
146 | #define SSP_CMD0_CMD_SD_LOCK_UNLOCK 0x2a | |
147 | #define SSP_CMD0_CMD_SD_IO_RW_DIRECT 0x34 | |
148 | #define SSP_CMD0_CMD_SD_IO_RW_EXTENDED 0x35 | |
149 | #define SSP_CMD0_CMD_SD_APP_CMD 0x37 | |
150 | #define SSP_CMD0_CMD_SD_GEN_CMD 0x38 | |
151 | ||
152 | #define SSP_CMD1_CMD_ARG_MASK 0xffffffff | |
153 | #define SSP_CMD1_CMD_ARG_OFFSET 0 | |
154 | ||
155 | #define SSP_XFER_SIZE_XFER_COUNT_MASK 0xffffffff | |
156 | #define SSP_XFER_SIZE_XFER_COUNT_OFFSET 0 | |
157 | ||
158 | #define SSP_BLOCK_SIZE_BLOCK_COUNT_MASK (0xffffff << 4) | |
159 | #define SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET 4 | |
160 | #define SSP_BLOCK_SIZE_BLOCK_SIZE_MASK 0xf | |
161 | #define SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET 0 | |
162 | ||
163 | #define SSP_COMPREF_REFERENCE_MASK 0xffffffff | |
164 | #define SSP_COMPREF_REFERENCE_OFFSET 0 | |
165 | ||
166 | #define SSP_COMPMASK_MASK_MASK 0xffffffff | |
167 | #define SSP_COMPMASK_MASK_OFFSET 0 | |
168 | ||
169 | #define SSP_TIMING_TIMEOUT_MASK (0xffff << 16) | |
170 | #define SSP_TIMING_TIMEOUT_OFFSET 16 | |
171 | #define SSP_TIMING_CLOCK_DIVIDE_MASK (0xff << 8) | |
172 | #define SSP_TIMING_CLOCK_DIVIDE_OFFSET 8 | |
173 | #define SSP_TIMING_CLOCK_RATE_MASK 0xff | |
174 | #define SSP_TIMING_CLOCK_RATE_OFFSET 0 | |
175 | ||
176 | #define SSP_CTRL1_SDIO_IRQ (1 << 31) | |
177 | #define SSP_CTRL1_SDIO_IRQ_EN (1 << 30) | |
178 | #define SSP_CTRL1_RESP_ERR_IRQ (1 << 29) | |
179 | #define SSP_CTRL1_RESP_ERR_IRQ_EN (1 << 28) | |
180 | #define SSP_CTRL1_RESP_TIMEOUT_IRQ (1 << 27) | |
181 | #define SSP_CTRL1_RESP_TIMEOUT_IRQ_EN (1 << 26) | |
182 | #define SSP_CTRL1_DATA_TIMEOUT_IRQ (1 << 25) | |
183 | #define SSP_CTRL1_DATA_TIMEOUT_IRQ_EN (1 << 24) | |
184 | #define SSP_CTRL1_DATA_CRC_IRQ (1 << 23) | |
185 | #define SSP_CTRL1_DATA_CRC_IRQ_EN (1 << 22) | |
186 | #define SSP_CTRL1_FIFO_UNDERRUN_IRQ (1 << 21) | |
187 | #define SSP_CTRL1_FIFO_UNDERRUN_EN (1 << 20) | |
188 | #define SSP_CTRL1_CEATA_CCS_ERR_IRQ (1 << 19) | |
189 | #define SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN (1 << 18) | |
190 | #define SSP_CTRL1_RECV_TIMEOUT_IRQ (1 << 17) | |
191 | #define SSP_CTRL1_RECV_TIMEOUT_IRQ_EN (1 << 16) | |
192 | #define SSP_CTRL1_FIFO_OVERRUN_IRQ (1 << 15) | |
193 | #define SSP_CTRL1_FIFO_OVERRUN_IRQ_EN (1 << 14) | |
194 | #define SSP_CTRL1_DMA_ENABLE (1 << 13) | |
195 | #define SSP_CTRL1_CEATA_CCS_ERR_EN (1 << 12) | |
196 | #define SSP_CTRL1_SLAVE_OUT_DISABLE (1 << 11) | |
197 | #define SSP_CTRL1_PHASE (1 << 10) | |
198 | #define SSP_CTRL1_POLARITY (1 << 9) | |
199 | #define SSP_CTRL1_SLAVE_MODE (1 << 8) | |
200 | #define SSP_CTRL1_WORD_LENGTH_MASK (0xf << 4) | |
201 | #define SSP_CTRL1_WORD_LENGTH_OFFSET 4 | |
202 | #define SSP_CTRL1_WORD_LENGTH_RESERVED0 (0x0 << 4) | |
203 | #define SSP_CTRL1_WORD_LENGTH_RESERVED1 (0x1 << 4) | |
204 | #define SSP_CTRL1_WORD_LENGTH_RESERVED2 (0x2 << 4) | |
205 | #define SSP_CTRL1_WORD_LENGTH_FOUR_BITS (0x3 << 4) | |
206 | #define SSP_CTRL1_WORD_LENGTH_EIGHT_BITS (0x7 << 4) | |
207 | #define SSP_CTRL1_WORD_LENGTH_SIXTEEN_BITS (0xf << 4) | |
208 | #define SSP_CTRL1_SSP_MODE_MASK 0xf | |
209 | #define SSP_CTRL1_SSP_MODE_OFFSET 0 | |
210 | #define SSP_CTRL1_SSP_MODE_SPI 0x0 | |
211 | #define SSP_CTRL1_SSP_MODE_SSI 0x1 | |
212 | #define SSP_CTRL1_SSP_MODE_SD_MMC 0x3 | |
213 | #define SSP_CTRL1_SSP_MODE_MS 0x4 | |
214 | ||
215 | #define SSP_DATA_DATA_MASK 0xffffffff | |
216 | #define SSP_DATA_DATA_OFFSET 0 | |
217 | ||
218 | #define SSP_SDRESP0_RESP0_MASK 0xffffffff | |
219 | #define SSP_SDRESP0_RESP0_OFFSET 0 | |
220 | ||
221 | #define SSP_SDRESP1_RESP1_MASK 0xffffffff | |
222 | #define SSP_SDRESP1_RESP1_OFFSET 0 | |
223 | ||
224 | #define SSP_SDRESP2_RESP2_MASK 0xffffffff | |
225 | #define SSP_SDRESP2_RESP2_OFFSET 0 | |
226 | ||
227 | #define SSP_SDRESP3_RESP3_MASK 0xffffffff | |
228 | #define SSP_SDRESP3_RESP3_OFFSET 0 | |
229 | ||
230 | #define SSP_DDR_CTRL_DMA_BURST_TYPE_MASK (0x3 << 30) | |
231 | #define SSP_DDR_CTRL_DMA_BURST_TYPE_OFFSET 30 | |
232 | #define SSP_DDR_CTRL_NIBBLE_POS (1 << 1) | |
233 | #define SSP_DDR_CTRL_TXCLK_DELAY_TYPE (1 << 0) | |
234 | ||
235 | #define SSP_DLL_CTRL_REF_UPDATE_INT_MASK (0xf << 28) | |
236 | #define SSP_DLL_CTRL_REF_UPDATE_INT_OFFSET 28 | |
237 | #define SSP_DLL_CTRL_SLV_UPDATE_INT_MASK (0xff << 20) | |
238 | #define SSP_DLL_CTRL_SLV_UPDATE_INT_OFFSET 20 | |
239 | #define SSP_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0x3f << 10) | |
240 | #define SSP_DLL_CTRL_SLV_OVERRIDE_VAL_OFFSET 10 | |
241 | #define SSP_DLL_CTRL_SLV_OVERRIDE (1 << 9) | |
242 | #define SSP_DLL_CTRL_GATE_UPDATE (1 << 7) | |
243 | #define SSP_DLL_CTRL_SLV_DLY_TARGET_MASK (0xf << 3) | |
244 | #define SSP_DLL_CTRL_SLV_DLY_TARGET_OFFSET 3 | |
245 | #define SSP_DLL_CTRL_SLV_FORCE_UPD (1 << 2) | |
246 | #define SSP_DLL_CTRL_RESET (1 << 1) | |
247 | #define SSP_DLL_CTRL_ENABLE (1 << 0) | |
248 | ||
249 | #define SSP_STATUS_PRESENT (1 << 31) | |
250 | #define SSP_STATUS_MS_PRESENT (1 << 30) | |
251 | #define SSP_STATUS_SD_PRESENT (1 << 29) | |
252 | #define SSP_STATUS_CARD_DETECT (1 << 28) | |
253 | #define SSP_STATUS_DMABURST (1 << 22) | |
254 | #define SSP_STATUS_DMASENSE (1 << 21) | |
255 | #define SSP_STATUS_DMATERM (1 << 20) | |
256 | #define SSP_STATUS_DMAREQ (1 << 19) | |
257 | #define SSP_STATUS_DMAEND (1 << 18) | |
258 | #define SSP_STATUS_SDIO_IRQ (1 << 17) | |
259 | #define SSP_STATUS_RESP_CRC_ERR (1 << 16) | |
260 | #define SSP_STATUS_RESP_ERR (1 << 15) | |
261 | #define SSP_STATUS_RESP_TIMEOUT (1 << 14) | |
262 | #define SSP_STATUS_DATA_CRC_ERR (1 << 13) | |
263 | #define SSP_STATUS_TIMEOUT (1 << 12) | |
264 | #define SSP_STATUS_RECV_TIMEOUT_STAT (1 << 11) | |
265 | #define SSP_STATUS_CEATA_CCS_ERR (1 << 10) | |
266 | #define SSP_STATUS_FIFO_OVRFLW (1 << 9) | |
267 | #define SSP_STATUS_FIFO_FULL (1 << 8) | |
268 | #define SSP_STATUS_FIFO_EMPTY (1 << 5) | |
269 | #define SSP_STATUS_FIFO_UNDRFLW (1 << 4) | |
270 | #define SSP_STATUS_CMD_BUSY (1 << 3) | |
271 | #define SSP_STATUS_DATA_BUSY (1 << 2) | |
272 | #define SSP_STATUS_BUSY (1 << 0) | |
273 | ||
274 | #define SSP_DLL_STS_REF_SEL_MASK (0x3f << 8) | |
275 | #define SSP_DLL_STS_REF_SEL_OFFSET 8 | |
276 | #define SSP_DLL_STS_SLV_SEL_MASK (0x3f << 2) | |
277 | #define SSP_DLL_STS_SLV_SEL_OFFSET 2 | |
278 | #define SSP_DLL_STS_REF_LOCK (1 << 1) | |
279 | #define SSP_DLL_STS_SLV_LOCK (1 << 0) | |
280 | ||
281 | #define SSP_DEBUG_DATACRC_ERR_MASK (0xf << 28) | |
282 | #define SSP_DEBUG_DATACRC_ERR_OFFSET 28 | |
283 | #define SSP_DEBUG_DATA_STALL (1 << 27) | |
284 | #define SSP_DEBUG_DAT_SM_MASK (0x7 << 24) | |
285 | #define SSP_DEBUG_DAT_SM_OFFSET 24 | |
286 | #define SSP_DEBUG_DAT_SM_DSM_IDLE (0x0 << 24) | |
287 | #define SSP_DEBUG_DAT_SM_DSM_WORD (0x2 << 24) | |
288 | #define SSP_DEBUG_DAT_SM_DSM_CRC1 (0x3 << 24) | |
289 | #define SSP_DEBUG_DAT_SM_DSM_CRC2 (0x4 << 24) | |
290 | #define SSP_DEBUG_DAT_SM_DSM_END (0x5 << 24) | |
291 | #define SSP_DEBUG_MSTK_SM_MASK (0xf << 20) | |
292 | #define SSP_DEBUG_MSTK_SM_OFFSET 20 | |
293 | #define SSP_DEBUG_MSTK_SM_MSTK_IDLE (0x0 << 20) | |
294 | #define SSP_DEBUG_MSTK_SM_MSTK_CKON (0x1 << 20) | |
295 | #define SSP_DEBUG_MSTK_SM_MSTK_BS1 (0x2 << 20) | |
296 | #define SSP_DEBUG_MSTK_SM_MSTK_TPC (0x3 << 20) | |
297 | #define SSP_DEBUG_MSTK_SM_MSTK_BS2 (0x4 << 20) | |
298 | #define SSP_DEBUG_MSTK_SM_MSTK_HDSHK (0x5 << 20) | |
299 | #define SSP_DEBUG_MSTK_SM_MSTK_BS3 (0x6 << 20) | |
300 | #define SSP_DEBUG_MSTK_SM_MSTK_RW (0x7 << 20) | |
301 | #define SSP_DEBUG_MSTK_SM_MSTK_CRC1 (0x8 << 20) | |
302 | #define SSP_DEBUG_MSTK_SM_MSTK_CRC2 (0x9 << 20) | |
303 | #define SSP_DEBUG_MSTK_SM_MSTK_BS0 (0xa << 20) | |
304 | #define SSP_DEBUG_MSTK_SM_MSTK_END1 (0xb << 20) | |
305 | #define SSP_DEBUG_MSTK_SM_MSTK_END2W (0xc << 20) | |
306 | #define SSP_DEBUG_MSTK_SM_MSTK_END2R (0xd << 20) | |
307 | #define SSP_DEBUG_MSTK_SM_MSTK_DONE (0xe << 20) | |
308 | #define SSP_DEBUG_CMD_OE (1 << 19) | |
309 | #define SSP_DEBUG_DMA_SM_MASK (0x7 << 16) | |
310 | #define SSP_DEBUG_DMA_SM_OFFSET 16 | |
311 | #define SSP_DEBUG_DMA_SM_DMA_IDLE (0x0 << 16) | |
312 | #define SSP_DEBUG_DMA_SM_DMA_DMAREQ (0x1 << 16) | |
313 | #define SSP_DEBUG_DMA_SM_DMA_DMAACK (0x2 << 16) | |
314 | #define SSP_DEBUG_DMA_SM_DMA_STALL (0x3 << 16) | |
315 | #define SSP_DEBUG_DMA_SM_DMA_BUSY (0x4 << 16) | |
316 | #define SSP_DEBUG_DMA_SM_DMA_DONE (0x5 << 16) | |
317 | #define SSP_DEBUG_DMA_SM_DMA_COUNT (0x6 << 16) | |
318 | #define SSP_DEBUG_MMC_SM_MASK (0xf << 12) | |
319 | #define SSP_DEBUG_MMC_SM_OFFSET 12 | |
320 | #define SSP_DEBUG_MMC_SM_MMC_IDLE (0x0 << 12) | |
321 | #define SSP_DEBUG_MMC_SM_MMC_CMD (0x1 << 12) | |
322 | #define SSP_DEBUG_MMC_SM_MMC_TRC (0x2 << 12) | |
323 | #define SSP_DEBUG_MMC_SM_MMC_RESP (0x3 << 12) | |
324 | #define SSP_DEBUG_MMC_SM_MMC_RPRX (0x4 << 12) | |
325 | #define SSP_DEBUG_MMC_SM_MMC_TX (0x5 << 12) | |
326 | #define SSP_DEBUG_MMC_SM_MMC_CTOK (0x6 << 12) | |
327 | #define SSP_DEBUG_MMC_SM_MMC_RX (0x7 << 12) | |
328 | #define SSP_DEBUG_MMC_SM_MMC_CCS (0x8 << 12) | |
329 | #define SSP_DEBUG_MMC_SM_MMC_PUP (0x9 << 12) | |
330 | #define SSP_DEBUG_MMC_SM_MMC_WAIT (0xa << 12) | |
331 | #define SSP_DEBUG_CMD_SM_MASK (0x3 << 10) | |
332 | #define SSP_DEBUG_CMD_SM_OFFSET 10 | |
333 | #define SSP_DEBUG_CMD_SM_CSM_IDLE (0x0 << 10) | |
334 | #define SSP_DEBUG_CMD_SM_CSM_INDEX (0x1 << 10) | |
335 | #define SSP_DEBUG_CMD_SM_CSM_ARG (0x2 << 10) | |
336 | #define SSP_DEBUG_CMD_SM_CSM_CRC (0x3 << 10) | |
337 | #define SSP_DEBUG_SSP_CMD (1 << 9) | |
338 | #define SSP_DEBUG_SSP_RESP (1 << 8) | |
339 | #define SSP_DEBUG_SSP_RXD_MASK 0xff | |
340 | #define SSP_DEBUG_SSP_RXD_OFFSET 0 | |
341 | ||
342 | #define SSP_VERSION_MAJOR_MASK (0xff << 24) | |
343 | #define SSP_VERSION_MAJOR_OFFSET 24 | |
344 | #define SSP_VERSION_MINOR_MASK (0xff << 16) | |
345 | #define SSP_VERSION_MINOR_OFFSET 16 | |
346 | #define SSP_VERSION_STEP_MASK 0xffff | |
347 | #define SSP_VERSION_STEP_OFFSET 0 | |
348 | ||
349 | #endif /* __MX28_REGS_SSP_H__ */ |