[people/ms/u-boot.git] / arch / arm / include / asm / arch-mx5 / imx-regs.h

/*
 * (C) Copyright 2009 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __ASM_ARCH_MX5_IMX_REGS_H__
#define __ASM_ARCH_MX5_IMX_REGS_H__

#define ARCH_MXC

#if defined(CONFIG_MX51)
#define IRAM_BASE_ADDR		0x1FFE0000	/* internal ram */
#define IPU_SOC_BASE_ADDR	0x40000000
#define IPU_SOC_OFFSET		0x1E000000
#define SPBA0_BASE_ADDR         0x70000000
#define AIPS1_BASE_ADDR         0x73F00000
#define AIPS2_BASE_ADDR         0x83F00000
#define CSD0_BASE_ADDR          0x90000000
#define CSD1_BASE_ADDR          0xA0000000
#define NFC_BASE_ADDR_AXI       0xCFFF0000
#define CS1_BASE_ADDR           0xB8000000
#elif defined(CONFIG_MX53)
#define IPU_SOC_BASE_ADDR	0x18000000
#define IPU_SOC_OFFSET		0x06000000
#define SPBA0_BASE_ADDR         0x50000000
#define AIPS1_BASE_ADDR         0x53F00000
#define AIPS2_BASE_ADDR         0x63F00000
#define CSD0_BASE_ADDR          0x70000000
#define CSD1_BASE_ADDR          0xB0000000
#define NFC_BASE_ADDR_AXI       0xF7FF0000
#define IRAM_BASE_ADDR          0xF8000000
#define CS1_BASE_ADDR           0xF4000000
#define SATA_BASE_ADDR		0x10000000
#else
#error "CPU_TYPE not defined"
#endif

#define IRAM_SIZE		0x00020000	/* 128 KB */

/*
 * SPBA global module enabled #0
 */
#define MMC_SDHC1_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00004000)
#define MMC_SDHC2_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00008000)
#define UART3_BASE		(SPBA0_BASE_ADDR + 0x0000C000)
#define CSPI1_BASE_ADDR 	(SPBA0_BASE_ADDR + 0x00010000)
#define SSI2_BASE_ADDR		(SPBA0_BASE_ADDR + 0x00014000)
#define MMC_SDHC3_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00020000)
#define MMC_SDHC4_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00024000)
#define SPDIF_BASE_ADDR		(SPBA0_BASE_ADDR + 0x00028000)
#define ATA_DMA_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00030000)
#define SLIM_DMA_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00034000)
#define HSI2C_DMA_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00038000)
#define SPBA_CTRL_BASE_ADDR	(SPBA0_BASE_ADDR + 0x0003C000)

/*
 * AIPS 1
 */
#define OTG_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00080000)
#define GPIO1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00084000)
#define GPIO2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00088000)
#define GPIO3_BASE_ADDR		(AIPS1_BASE_ADDR + 0x0008C000)
#define GPIO4_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00090000)
#define KPP_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00094000)
#define WDOG1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00098000)
#define WDOG2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x0009C000)
#define GPT1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000A0000)
#define SRTC_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000A4000)
#define IOMUXC_BASE_ADDR	(AIPS1_BASE_ADDR + 0x000A8000)
#define EPIT1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000AC000)
#define EPIT2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000B0000)
#define PWM1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000B4000)
#define PWM2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000B8000)
#define UART1_BASE		(AIPS1_BASE_ADDR + 0x000BC000)
#define UART2_BASE		(AIPS1_BASE_ADDR + 0x000C0000)
#define SRC_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000D0000)
#define CCM_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000D4000)
#define GPC_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000D8000)

#if defined(CONFIG_MX53)
#define GPIO5_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000DC000)
#define GPIO6_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000E0000)
#define GPIO7_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000E4000)
#define I2C3_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000EC000)
#define UART4_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000F0000)
#endif
/*
 * AIPS 2
 */
#define PLL1_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00080000)
#define PLL2_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00084000)
#define PLL3_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00088000)
#ifdef	CONFIG_MX53
#define PLL4_BASE_ADDR		(AIPS2_BASE_ADDR + 0x0008c000)
#endif
#define AHBMAX_BASE_ADDR	(AIPS2_BASE_ADDR + 0x00094000)
#define IIM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00098000)
#define CSU_BASE_ADDR		(AIPS2_BASE_ADDR + 0x0009C000)
#define ARM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000A0000)
#define OWIRE_BASE_ADDR 	(AIPS2_BASE_ADDR + 0x000A4000)
#define FIRI_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000A8000)
#define CSPI2_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000AC000)
#define SDMA_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000B0000)
#define SCC_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000B4000)
#define ROMCP_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000B8000)
#define RTIC_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000BC000)
#define CSPI3_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000C0000)
#define I2C2_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000C4000)
#define I2C1_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000C8000)
#define SSI1_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000CC000)
#define AUDMUX_BASE_ADDR	(AIPS2_BASE_ADDR + 0x000D0000)
#define M4IF_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000D8000)
#define ESDCTL_BASE_ADDR	(AIPS2_BASE_ADDR + 0x000D9000)
#define WEIM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000DA000)
#define NFC_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000DB000)
#define EMI_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000DBF00)
#define MIPI_HSC_BASE_ADDR	(AIPS2_BASE_ADDR + 0x000DC000)
#define ATA_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000E0000)
#define SIM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000E4000)
#define SSI3BASE_ADDR		(AIPS2_BASE_ADDR + 0x000E8000)
#define FEC_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000EC000)
#define TVE_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000F0000)
#define VPU_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000F4000)
#define SAHARA_BASE_ADDR	(AIPS2_BASE_ADDR + 0x000F8000)

#if defined(CONFIG_MX53)
#define UART5_BASE_ADDR         (AIPS2_BASE_ADDR + 0x00090000)
#endif

/*
 * WEIM CSnGCR1
 */
#define CSEN		1
#define SWR		(1 << 1)
#define SRD		(1 << 2)
#define MUM		(1 << 3)
#define WFL		(1 << 4)
#define RFL		(1 << 5)
#define CRE		(1 << 6)
#define CREP		(1 << 7)
#define BL(x)		(((x) & 0x7) << 8)
#define WC		(1 << 11)
#define BCD(x)		(((x) & 0x3) << 12)
#define BCS(x)		(((x) & 0x3) << 14)
#define DSZ(x)		(((x) & 0x7) << 16)
#define SP		(1 << 19)
#define CSREC(x)	(((x) & 0x7) << 20)
#define AUS		(1 << 23)
#define GBC(x)		(((x) & 0x7) << 24)
#define WP		(1 << 27)
#define PSZ(x)		(((x) & 0x0f << 28)

/*
 * WEIM CSnGCR2
 */
#define ADH(x)		(((x) & 0x3))
#define DAPS(x)		(((x) & 0x0f << 4)
#define DAE		(1 << 8)
#define DAP		(1 << 9)
#define MUX16_BYP	(1 << 12)

/*
 * WEIM CSnRCR1
 */
#define RCSN(x)		(((x) & 0x7))
#define RCSA(x)		(((x) & 0x7) << 4)
#define OEN(x)		(((x) & 0x7) << 8)
#define OEA(x)		(((x) & 0x7) << 12)
#define RADVN(x)	(((x) & 0x7) << 16)
#define RAL		(1 << 19)
#define RADVA(x)	(((x) & 0x7) << 20)
#define RWSC(x)		(((x) & 0x3f) << 24)

/*
 * WEIM CSnRCR2
 */
#define RBEN(x)		(((x) & 0x7))
#define RBE		(1 << 3)
#define RBEA(x)		(((x) & 0x7) << 4)
#define RL(x)		(((x) & 0x3) << 8)
#define PAT(x)		(((x) & 0x7) << 12)
#define APR		(1 << 15)

/*
 * WEIM CSnWCR1
 */
#define WCSN(x)		(((x) & 0x7))
#define WCSA(x)		(((x) & 0x7) << 3)
#define WEN(x)		(((x) & 0x7) << 6)
#define WEA(x)		(((x) & 0x7) << 9)
#define WBEN(x)		(((x) & 0x7) << 12)
#define WBEA(x)		(((x) & 0x7) << 15)
#define WADVN(x)	(((x) & 0x7) << 18)
#define WADVA(x)	(((x) & 0x7) << 21)
#define WWSC(x)		(((x) & 0x3f) << 24)
#define WBED1		(1 << 30)
#define WAL		(1 << 31)

/*
 * WEIM CSnWCR2
 */
#define WBED		1

/*
 * CSPI register definitions
 */
#define MXC_ECSPI
#define MXC_CSPICTRL_EN		(1 << 0)
#define MXC_CSPICTRL_MODE	(1 << 1)
#define MXC_CSPICTRL_XCH	(1 << 2)
#define MXC_CSPICTRL_MODE_MASK	(0xf << 4)
#define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 12)
#define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0xfff) << 20)
#define MXC_CSPICTRL_PREDIV(x)	(((x) & 0xF) << 12)
#define MXC_CSPICTRL_POSTDIV(x)	(((x) & 0xF) << 8)
#define MXC_CSPICTRL_SELCHAN(x)	(((x) & 0x3) << 18)
#define MXC_CSPICTRL_MAXBITS	0xfff
#define MXC_CSPICTRL_TC		(1 << 7)
#define MXC_CSPICTRL_RXOVF	(1 << 6)
#define MXC_CSPIPERIOD_32KHZ	(1 << 15)
#define MAX_SPI_BYTES	32

/* Bit position inside CTRL register to be associated with SS */
#define MXC_CSPICTRL_CHAN	18

/* Bit position inside CON register to be associated with SS */
#define MXC_CSPICON_PHA		0  /* SCLK phase control */
#define MXC_CSPICON_POL		4  /* SCLK polarity */
#define MXC_CSPICON_SSPOL	12 /* SS polarity */
#define MXC_CSPICON_CTL		20 /* inactive state of SCLK */
#define MXC_SPI_BASE_ADDRESSES \
	CSPI1_BASE_ADDR, \
	CSPI2_BASE_ADDR, \
	CSPI3_BASE_ADDR,

/*
 * Number of GPIO pins per port
 */
#define GPIO_NUM_PIN            32

#define IIM_SREV	0x24
#define ROM_SI_REV	0x48

#define NFC_BUF_SIZE	0x1000

/* M4IF */
#define M4IF_FBPM0	0x40
#define M4IF_FIDBP	0x48
#define M4IF_GENP_WEIM_MM_MASK		0x00000001
#define WEIM_GCR2_MUX16_BYP_GRANT_MASK	0x00001000

/* Assuming 24MHz input clock with doubler ON */
/*                            MFI         PDF */
#define DP_OP_864	((8 << 4) + ((1 - 1)  << 0))
#define DP_MFD_864	(180 - 1) /* PL Dither mode */
#define DP_MFN_864	180
#define DP_MFN_800_DIT	60 /* PL Dither mode */

#define DP_OP_850	((8 << 4) + ((1 - 1)  << 0))
#define DP_MFD_850	(48 - 1)
#define DP_MFN_850	41

#define DP_OP_800	((8 << 4) + ((1 - 1)  << 0))
#define DP_MFD_800	(3 - 1)
#define DP_MFN_800	1

#define DP_OP_700	((7 << 4) + ((1 - 1)  << 0))
#define DP_MFD_700	(24 - 1)
#define DP_MFN_700	7

#define DP_OP_665	((6 << 4) + ((1 - 1)  << 0))
#define DP_MFD_665	(96 - 1)
#define DP_MFN_665	89

#define DP_OP_532	((5 << 4) + ((1 - 1)  << 0))
#define DP_MFD_532	(24 - 1)
#define DP_MFN_532	13

#define DP_OP_400	((8 << 4) + ((2 - 1)  << 0))
#define DP_MFD_400	(3 - 1)
#define DP_MFN_400	1

#define DP_OP_455	((9 << 4) + ((2 - 1)  << 0))
#define DP_MFD_455	(48 - 1)
#define DP_MFN_455	23

#define DP_OP_216	((6 << 4) + ((3 - 1)  << 0))
#define DP_MFD_216	(4 - 1)
#define DP_MFN_216	3

#define IMX_IIM_BASE            (IIM_BASE_ADDR)

#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>

#define __REG(x)	(*((volatile u32 *)(x)))
#define __REG16(x)	(*((volatile u16 *)(x)))
#define __REG8(x)	(*((volatile u8 *)(x)))

struct clkctl {
	u32	ccr;
	u32	ccdr;
	u32	csr;
	u32	ccsr;
	u32	cacrr;
	u32	cbcdr;
	u32	cbcmr;
	u32	cscmr1;
	u32	cscmr2;
	u32	cscdr1;
	u32	cs1cdr;
	u32	cs2cdr;
	u32	cdcdr;
	u32	chsccdr;
	u32	cscdr2;
	u32	cscdr3;
	u32	cscdr4;
	u32	cwdr;
	u32	cdhipr;
	u32	cdcr;
	u32	ctor;
	u32	clpcr;
	u32	cisr;
	u32	cimr;
	u32	ccosr;
	u32	cgpr;
	u32	ccgr0;
	u32	ccgr1;
	u32	ccgr2;
	u32	ccgr3;
	u32	ccgr4;
	u32	ccgr5;
	u32	ccgr6;
#if defined(CONFIG_MX53)
	u32	ccgr7;
#endif
	u32	cmeor;
};

/* DPLL registers */
struct dpll {
	u32	dp_ctl;
	u32	dp_config;
	u32	dp_op;
	u32	dp_mfd;
	u32	dp_mfn;
	u32	dp_mfn_minus;
	u32	dp_mfn_plus;
	u32	dp_hfs_op;
	u32	dp_hfs_mfd;
	u32	dp_hfs_mfn;
	u32	dp_mfn_togc;
	u32	dp_destat;
};
/* WEIM registers */
struct weim {
	u32	cs0gcr1;
	u32	cs0gcr2;
	u32	cs0rcr1;
	u32	cs0rcr2;
	u32	cs0wcr1;
	u32	cs0wcr2;
	u32	cs1gcr1;
	u32	cs1gcr2;
	u32	cs1rcr1;
	u32	cs1rcr2;
	u32	cs1wcr1;
	u32	cs1wcr2;
	u32	cs2gcr1;
	u32	cs2gcr2;
	u32	cs2rcr1;
	u32	cs2rcr2;
	u32	cs2wcr1;
	u32	cs2wcr2;
	u32	cs3gcr1;
	u32	cs3gcr2;
	u32	cs3rcr1;
	u32	cs3rcr2;
	u32	cs3wcr1;
	u32	cs3wcr2;
	u32	cs4gcr1;
	u32	cs4gcr2;
	u32	cs4rcr1;
	u32	cs4rcr2;
	u32	cs4wcr1;
	u32	cs4wcr2;
	u32	cs5gcr1;
	u32	cs5gcr2;
	u32	cs5rcr1;
	u32	cs5rcr2;
	u32	cs5wcr1;
	u32	cs5wcr2;
	u32	wcr;
	u32	wiar;
	u32	ear;
};

#if defined(CONFIG_MX51)
struct iomuxc {
	u32	gpr[2];
	u32	omux0;
	u32	omux1;
	u32	omux2;
	u32	omux3;
	u32	omux4;
};
#elif defined(CONFIG_MX53)
struct iomuxc {
	u32	gpr[3];
	u32	omux0;
	u32	omux1;
	u32	omux2;
	u32	omux3;
	u32	omux4;
};
#endif

#define IOMUXC_GPR2_BITMAP_SPWG	0
#define IOMUXC_GPR2_BITMAP_JEIDA	1

#define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET	6
#define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK	(1 << IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
#define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA	(IOMUXC_GPR2_BITMAP_JEIDA << \
						 IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
#define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG	(IOMUXC_GPR2_BITMAP_SPWG << \
						 IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)

#define IOMUXC_GPR2_DATA_WIDTH_18	0
#define IOMUXC_GPR2_DATA_WIDTH_24	1

#define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET	5
#define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK		(1 << IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
#define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT	(IOMUXC_GPR2_DATA_WIDTH_18 << \
						 IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
#define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT	(IOMUXC_GPR2_DATA_WIDTH_24 << \
						 IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)

#define IOMUXC_GPR2_MODE_DISABLED	0
#define IOMUXC_GPR2_MODE_ENABLED_DI0	1
#define IOMUXC_GPR2_MODE_ENABLED_DI1	3

#define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET	0
#define IOMUXC_GPR2_LVDS_CH0_MODE_MASK		(3 << IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
#define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED	(IOMUXC_GPR2_MODE_DISABLED << \
						 IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0	(IOMUXC_GPR2_MODE_ENABLED_DI0 << \
						 IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1	(IOMUXC_GPR2_MODE_ENABLED_DI1 << \
						 IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)

/* System Reset Controller (SRC) */
struct src {
	u32	scr;
	u32	sbmr;
	u32	srsr;
	u32	reserved1[2];
	u32	sisr;
	u32	simr;
};

struct srtc_regs {
	u32	lpscmr;		/* 0x00 */
	u32	lpsclr;		/* 0x04 */
	u32	lpsar;		/* 0x08 */
	u32	lpsmcr;		/* 0x0c */
	u32	lpcr;		/* 0x10 */
	u32	lpsr;		/* 0x14 */
	u32	lppdr;		/* 0x18 */
	u32	lpgr;		/* 0x1c */
	u32	hpcmr;		/* 0x20 */
	u32	hpclr;		/* 0x24 */
	u32	hpamr;		/* 0x28 */
	u32	hpalr;		/* 0x2c */
	u32	hpcr;		/* 0x30 */
	u32	hpisr;		/* 0x34 */
	u32	hpienr;		/* 0x38 */
};

/* CSPI registers */
struct cspi_regs {
	u32 rxdata;
	u32 txdata;
	u32 ctrl;
	u32 cfg;
	u32 intr;
	u32 dma;
	u32 stat;
	u32 period;
};

struct iim_regs {
	u32	stat;
	u32	statm;
	u32     err;
	u32	emask;
	u32	fctl;
	u32	ua;
	u32	la;
	u32	sdat;
	u32	prev;
	u32	srev;
	u32	prg_p;
	u32	scs0;
	u32	scs1;
	u32	scs2;
	u32	scs3;
	u32	res0[0x1f1];
	struct fuse_bank {
		u32	fuse_regs[0x20];
		u32	fuse_rsvd[0xe0];
#if defined(CONFIG_MX51)
	} bank[4];
#elif defined(CONFIG_MX53)
	} bank[5];
#endif
};

struct fuse_bank0_regs {
	u32	fuse0_7[8];
	u32	uid[8];
	u32	fuse16_23[8];
#if defined(CONFIG_MX51)
	u32	imei[8];
#elif defined(CONFIG_MX53)
	u32	gp[8];
#endif
};

struct fuse_bank1_regs {
	u32	fuse0_8[9];
	u32	mac_addr[6];
	u32	fuse15_31[0x11];
};

#if defined(CONFIG_MX53)
struct fuse_bank4_regs {
	u32	fuse0_4[5];
	u32	gp[3];
	u32	fuse8_31[0x18];
};
#endif

#define PWMCR_PRESCALER(x)	(((x - 1) & 0xFFF) << 4)
#define PWMCR_DOZEEN		(1 << 24)
#define PWMCR_WAITEN		(1 << 23)
#define PWMCR_DBGEN		(1 << 22)
#define PWMCR_CLKSRC_IPG_HIGH	(2 << 16)
#define PWMCR_CLKSRC_IPG	(1 << 16)
#define PWMCR_EN		(1 << 0)

struct pwm_regs {
	u32	cr;
	u32	sr;
	u32	ir;
	u32	sar;
	u32	pr;
	u32	cnr;
};

#endif /* __ASSEMBLER__*/

#endif				/* __ASM_ARCH_MX5_IMX_REGS_H__ */
Commit	Line	Data
fb87a1ed SB	1	/*
	2	* (C) Copyright 2009 Freescale Semiconductor, Inc.
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
fb87a1ed SB	5	*/
fb87a1ed SB	6
595f3e56 LHR	7	#ifndef __ASM_ARCH_MX5_IMX_REGS_H__
595f3e56 LHR	8	#define __ASM_ARCH_MX5_IMX_REGS_H__
fb87a1ed	9
8e99ecd7 BT	10	#define ARCH_MXC
8e99ecd7 BT	11
595f3e56	12	#if defined(CONFIG_MX51)
1ab027cb	13	#define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */
fff6ef72 FE	14	#define IPU_SOC_BASE_ADDR 0x40000000
fff6ef72 FE	15	#define IPU_SOC_OFFSET 0x1E000000
595f3e56 LHR	16	#define SPBA0_BASE_ADDR 0x70000000
	17	#define AIPS1_BASE_ADDR 0x73F00000
	18	#define AIPS2_BASE_ADDR 0x83F00000
	19	#define CSD0_BASE_ADDR 0x90000000
	20	#define CSD1_BASE_ADDR 0xA0000000
	21	#define NFC_BASE_ADDR_AXI 0xCFFF0000
ac4020e3	22	#define CS1_BASE_ADDR 0xB8000000
595f3e56	23	#elif defined(CONFIG_MX53)
fff6ef72 FE	24	#define IPU_SOC_BASE_ADDR 0x18000000
fff6ef72 FE	25	#define IPU_SOC_OFFSET 0x06000000
595f3e56 LHR	26	#define SPBA0_BASE_ADDR 0x50000000
	27	#define AIPS1_BASE_ADDR 0x53F00000
	28	#define AIPS2_BASE_ADDR 0x63F00000
	29	#define CSD0_BASE_ADDR 0x70000000
	30	#define CSD1_BASE_ADDR 0xB0000000
	31	#define NFC_BASE_ADDR_AXI 0xF7FF0000
	32	#define IRAM_BASE_ADDR 0xF8000000
ac4020e3	33	#define CS1_BASE_ADDR 0xF4000000
d87c85ce	34	#define SATA_BASE_ADDR 0x10000000
595f3e56 LHR	35	#else
	36	#error "CPU_TYPE not defined"
	37	#endif
	38
	39	#define IRAM_SIZE 0x00020000 /* 128 KB */
fb87a1ed SB	40
	41	/*
	42	* SPBA global module enabled #0
	43	*/
fb87a1ed SB	44	#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
fb87a1ed SB	45	#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000)
40f6fffe	46	#define UART3_BASE (SPBA0_BASE_ADDR + 0x0000C000)
fb87a1ed SB	47	#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
	48	#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000)
	49	#define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000)
	50	#define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
	51	#define SPDIF_BASE_ADDR (SPBA0_BASE_ADDR + 0x00028000)
	52	#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00030000)
	53	#define SLIM_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00034000)
	54	#define HSI2C_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00038000)
	55	#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000)
	56
	57	/*
	58	* AIPS 1
	59	*/
fb87a1ed SB	60	#define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000)
	61	#define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000)
	62	#define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000)
	63	#define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000)
	64	#define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000)
	65	#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000)
	66	#define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000)
	67	#define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000)
	68	#define GPT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000)
	69	#define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000)
	70	#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000)
	71	#define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000)
	72	#define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000)
	73	#define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000)
	74	#define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000)
40f6fffe SB	75	#define UART1_BASE (AIPS1_BASE_ADDR + 0x000BC000)
40f6fffe SB	76	#define UART2_BASE (AIPS1_BASE_ADDR + 0x000C0000)
fb87a1ed SB	77	#define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000)
	78	#define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000)
	79	#define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000)
	80
595f3e56 LHR	81	#if defined(CONFIG_MX53)
	82	#define GPIO5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000DC000)
	83	#define GPIO6_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E0000)
	84	#define GPIO7_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E4000)
df369dcd	85	#define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x000EC000)
4a9677e5	86	#define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000F0000)
595f3e56	87	#endif
fb87a1ed SB	88	/*
	89	* AIPS 2
	90	*/
fb87a1ed SB	91	#define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
	92	#define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000)
	93	#define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000)
bf2eaf51 MV	94	#ifdef CONFIG_MX53
	95	#define PLL4_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008c000)
	96	#endif
fb87a1ed SB	97	#define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
	98	#define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
	99	#define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000)
	100	#define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000)
	101	#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
	102	#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000)
	103	#define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000)
	104	#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000)
	105	#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B4000)
	106	#define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000)
	107	#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000BC000)
	108	#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000)
	109	#define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000)
	110	#define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000)
	111	#define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000)
	112	#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000)
	113	#define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000)
	114	#define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000)
	115	#define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000)
	116	#define NFC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DB000)
	117	#define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00)
	118	#define MIPI_HSC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000)
	119	#define ATA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000)
	120	#define SIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E4000)
	121	#define SSI3BASE_ADDR (AIPS2_BASE_ADDR + 0x000E8000)
	122	#define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000)
	123	#define TVE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F0000)
	124	#define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000)
	125	#define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000)
	126
4a9677e5 SB	127	#if defined(CONFIG_MX53)
	128	#define UART5_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000)
	129	#endif
	130
ac4020e3 FE	131	/*
	132	* WEIM CSnGCR1
	133	*/
	134	#define CSEN 1
	135	#define SWR (1 << 1)
	136	#define SRD (1 << 2)
	137	#define MUM (1 << 3)
	138	#define WFL (1 << 4)
	139	#define RFL (1 << 5)
	140	#define CRE (1 << 6)
	141	#define CREP (1 << 7)
	142	#define BL(x) (((x) & 0x7) << 8)
	143	#define WC (1 << 11)
	144	#define BCD(x) (((x) & 0x3) << 12)
	145	#define BCS(x) (((x) & 0x3) << 14)
	146	#define DSZ(x) (((x) & 0x7) << 16)
	147	#define SP (1 << 19)
	148	#define CSREC(x) (((x) & 0x7) << 20)
	149	#define AUS (1 << 23)
	150	#define GBC(x) (((x) & 0x7) << 24)
	151	#define WP (1 << 27)
	152	#define PSZ(x) (((x) & 0x0f << 28)
	153
	154	/*
	155	* WEIM CSnGCR2
	156	*/
	157	#define ADH(x) (((x) & 0x3))
	158	#define DAPS(x) (((x) & 0x0f << 4)
	159	#define DAE (1 << 8)
	160	#define DAP (1 << 9)
	161	#define MUX16_BYP (1 << 12)
	162
	163	/*
	164	* WEIM CSnRCR1
	165	*/
	166	#define RCSN(x) (((x) & 0x7))
	167	#define RCSA(x) (((x) & 0x7) << 4)
	168	#define OEN(x) (((x) & 0x7) << 8)
	169	#define OEA(x) (((x) & 0x7) << 12)
	170	#define RADVN(x) (((x) & 0x7) << 16)
	171	#define RAL (1 << 19)
	172	#define RADVA(x) (((x) & 0x7) << 20)
	173	#define RWSC(x) (((x) & 0x3f) << 24)
	174
	175	/*
	176	* WEIM CSnRCR2
	177	*/
	178	#define RBEN(x) (((x) & 0x7))
	179	#define RBE (1 << 3)
	180	#define RBEA(x) (((x) & 0x7) << 4)
	181	#define RL(x) (((x) & 0x3) << 8)
	182	#define PAT(x) (((x) & 0x7) << 12)
	183	#define APR (1 << 15)
	184
	185	/*
	186	* WEIM CSnWCR1
	187	*/
	188	#define WCSN(x) (((x) & 0x7))
	189	#define WCSA(x) (((x) & 0x7) << 3)
	190	#define WEN(x) (((x) & 0x7) << 6)
	191	#define WEA(x) (((x) & 0x7) << 9)
	192	#define WBEN(x) (((x) & 0x7) << 12)
	193	#define WBEA(x) (((x) & 0x7) << 15)
	194	#define WADVN(x) (((x) & 0x7) << 18)
195	#define WADVA(x) (((x) & 0x7) << 21)
196	#define WWSC(x) (((x) & 0x3f) << 24)
197	#define WBED1 (1 << 30)
198	#define WAL (1 << 31)
199
200	/*
201	* WEIM CSnWCR2
202	*/
203	#define WBED 1
204
08c61a58 EN	205	/*
	206	* CSPI register definitions
	207	*/
	208	#define MXC_ECSPI
	209	#define MXC_CSPICTRL_EN (1 << 0)
	210	#define MXC_CSPICTRL_MODE (1 << 1)
	211	#define MXC_CSPICTRL_XCH (1 << 2)
0f1411bc	212	#define MXC_CSPICTRL_MODE_MASK (0xf << 4)
08c61a58 EN	213	#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
	214	#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
	215	#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
	216	#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
	217	#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
	218	#define MXC_CSPICTRL_MAXBITS 0xfff
	219	#define MXC_CSPICTRL_TC (1 << 7)
	220	#define MXC_CSPICTRL_RXOVF (1 << 6)
	221	#define MXC_CSPIPERIOD_32KHZ (1 << 15)
	222	#define MAX_SPI_BYTES 32
	223
	224	/* Bit position inside CTRL register to be associated with SS */
	225	#define MXC_CSPICTRL_CHAN 18
	226
	227	/* Bit position inside CON register to be associated with SS */
d7cbcc76 MN	228	#define MXC_CSPICON_PHA 0 /* SCLK phase control */
	229	#define MXC_CSPICON_POL 4 /* SCLK polarity */
	230	#define MXC_CSPICON_SSPOL 12 /* SS polarity */
	231	#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
08c61a58 EN	232	#define MXC_SPI_BASE_ADDRESSES \
	233	CSPI1_BASE_ADDR, \
	234	CSPI2_BASE_ADDR, \
	235	CSPI3_BASE_ADDR,
	236
fb87a1ed	237	/*
fb87a1ed SB	238	* Number of GPIO pins per port
	239	*/
	240	#define GPIO_NUM_PIN 32
	241
	242	#define IIM_SREV 0x24
	243	#define ROM_SI_REV 0x48
	244
	245	#define NFC_BUF_SIZE 0x1000
	246
	247	/* M4IF */
	248	#define M4IF_FBPM0 0x40
	249	#define M4IF_FIDBP 0x48
1155d555 FE	250	#define M4IF_GENP_WEIM_MM_MASK 0x00000001
1155d555 FE	251	#define WEIM_GCR2_MUX16_BYP_GRANT_MASK 0x00001000
fb87a1ed SB	252
	253	/* Assuming 24MHz input clock with doubler ON */
	254	/* MFI PDF */
9db1bfa1 DJ	255	#define DP_OP_864 ((8 << 4) + ((1 - 1) << 0))
	256	#define DP_MFD_864 (180 - 1) /* PL Dither mode */
	257	#define DP_MFN_864 180
	258	#define DP_MFN_800_DIT 60 /* PL Dither mode */
	259
fb87a1ed SB	260	#define DP_OP_850 ((8 << 4) + ((1 - 1) << 0))
	261	#define DP_MFD_850 (48 - 1)
	262	#define DP_MFN_850 41
	263
	264	#define DP_OP_800 ((8 << 4) + ((1 - 1) << 0))
	265	#define DP_MFD_800 (3 - 1)
	266	#define DP_MFN_800 1
	267
	268	#define DP_OP_700 ((7 << 4) + ((1 - 1) << 0))
	269	#define DP_MFD_700 (24 - 1)
	270	#define DP_MFN_700 7
	271
	272	#define DP_OP_665 ((6 << 4) + ((1 - 1) << 0))
	273	#define DP_MFD_665 (96 - 1)
	274	#define DP_MFN_665 89
	275
	276	#define DP_OP_532 ((5 << 4) + ((1 - 1) << 0))
	277	#define DP_MFD_532 (24 - 1)
	278	#define DP_MFN_532 13
	279
	280	#define DP_OP_400 ((8 << 4) + ((2 - 1) << 0))
	281	#define DP_MFD_400 (3 - 1)
	282	#define DP_MFN_400 1
	283
782b0288 FE	284	#define DP_OP_455 ((9 << 4) + ((2 - 1) << 0))
	285	#define DP_MFD_455 (48 - 1)
	286	#define DP_MFN_455 23
	287
fb87a1ed SB	288	#define DP_OP_216 ((6 << 4) + ((3 - 1) << 0))
	289	#define DP_MFD_216 (4 - 1)
	290	#define DP_MFN_216 3
	291
565e39c5 LHR	292	#define IMX_IIM_BASE (IIM_BASE_ADDR)
565e39c5 LHR	293
f3554dfd SB	294	#if !(defined(__KERNEL_STRICT_NAMES) \|\| defined(__ASSEMBLY__))
	295	#include <asm/types.h>
	296
	297	#define __REG(x) (((volatile u32 )(x)))
	298	#define __REG16(x) (((volatile u16 )(x)))
	299	#define __REG8(x) (((volatile u8 )(x)))
fb87a1ed	300
fb87a1ed SB	301	struct clkctl {
	302	u32 ccr;
	303	u32 ccdr;
	304	u32 csr;
	305	u32 ccsr;
	306	u32 cacrr;
	307	u32 cbcdr;
	308	u32 cbcmr;
	309	u32 cscmr1;
	310	u32 cscmr2;
	311	u32 cscdr1;
	312	u32 cs1cdr;
	313	u32 cs2cdr;
	314	u32 cdcdr;
	315	u32 chsccdr;
	316	u32 cscdr2;
	317	u32 cscdr3;
	318	u32 cscdr4;
	319	u32 cwdr;
	320	u32 cdhipr;
	321	u32 cdcr;
	322	u32 ctor;
	323	u32 clpcr;
	324	u32 cisr;
	325	u32 cimr;
	326	u32 ccosr;
	327	u32 cgpr;
	328	u32 ccgr0;
	329	u32 ccgr1;
	330	u32 ccgr2;
	331	u32 ccgr3;
	332	u32 ccgr4;
	333	u32 ccgr5;
	334	u32 ccgr6;
0edf8b5b SB	335	#if defined(CONFIG_MX53)
	336	u32 ccgr7;
	337	#endif
fb87a1ed SB	338	u32 cmeor;
	339	};
	340
0edf8b5b SB	341	/* DPLL registers */
	342	struct dpll {
	343	u32 dp_ctl;
	344	u32 dp_config;
	345	u32 dp_op;
	346	u32 dp_mfd;
	347	u32 dp_mfn;
	348	u32 dp_mfn_minus;
	349	u32 dp_mfn_plus;
	350	u32 dp_hfs_op;
	351	u32 dp_hfs_mfd;
	352	u32 dp_hfs_mfn;
	353	u32 dp_mfn_togc;
	354	u32 dp_destat;
	355	};
fb87a1ed SB	356	/* WEIM registers */
fb87a1ed SB	357	struct weim {
ac4020e3 FE	358	u32 cs0gcr1;
	359	u32 cs0gcr2;
	360	u32 cs0rcr1;
	361	u32 cs0rcr2;
	362	u32 cs0wcr1;
	363	u32 cs0wcr2;
	364	u32 cs1gcr1;
	365	u32 cs1gcr2;
	366	u32 cs1rcr1;
	367	u32 cs1rcr2;
	368	u32 cs1wcr1;
	369	u32 cs1wcr2;
	370	u32 cs2gcr1;
	371	u32 cs2gcr2;
	372	u32 cs2rcr1;
	373	u32 cs2rcr2;
	374	u32 cs2wcr1;
	375	u32 cs2wcr2;
	376	u32 cs3gcr1;
	377	u32 cs3gcr2;
	378	u32 cs3rcr1;
	379	u32 cs3rcr2;
	380	u32 cs3wcr1;
	381	u32 cs3wcr2;
	382	u32 cs4gcr1;
	383	u32 cs4gcr2;
	384	u32 cs4rcr1;
	385	u32 cs4rcr2;
	386	u32 cs4wcr1;
	387	u32 cs4wcr2;
	388	u32 cs5gcr1;
	389	u32 cs5gcr2;
	390	u32 cs5rcr1;
	391	u32 cs5rcr2;
	392	u32 cs5wcr1;
	393	u32 cs5wcr2;
	394	u32 wcr;
	395	u32 wiar;
	396	u32 ear;
fb87a1ed SB	397	};
fb87a1ed SB	398
a682b3f7 FE	399	#if defined(CONFIG_MX51)
a682b3f7 FE	400	struct iomuxc {
32c81ea6	401	u32 gpr[2];
a682b3f7 FE	402	u32 omux0;
	403	u32 omux1;
	404	u32 omux2;
	405	u32 omux3;
	406	u32 omux4;
	407	};
	408	#elif defined(CONFIG_MX53)
	409	struct iomuxc {
32c81ea6	410	u32 gpr[3];
a682b3f7 FE	411	u32 omux0;
	412	u32 omux1;
	413	u32 omux2;
	414	u32 omux3;
	415	u32 omux4;
	416	};
	417	#endif
	418
54d8d494 MW	419	#define IOMUXC_GPR2_BITMAP_SPWG 0
	420	#define IOMUXC_GPR2_BITMAP_JEIDA 1
	421
	422	#define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET 6
	423	#define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK (1 << IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
	424	#define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA << \
	425	IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
	426	#define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG (IOMUXC_GPR2_BITMAP_SPWG << \
	427	IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
	428
	429	#define IOMUXC_GPR2_DATA_WIDTH_18 0
	430	#define IOMUXC_GPR2_DATA_WIDTH_24 1
	431
	432	#define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET 5
	433	#define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK (1 << IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
	434	#define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT (IOMUXC_GPR2_DATA_WIDTH_18 << \
	435	IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
	436	#define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT (IOMUXC_GPR2_DATA_WIDTH_24 << \
	437	IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
	438
	439	#define IOMUXC_GPR2_MODE_DISABLED 0
	440	#define IOMUXC_GPR2_MODE_ENABLED_DI0 1
	441	#define IOMUXC_GPR2_MODE_ENABLED_DI1 3
	442
	443	#define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET 0
	444	#define IOMUXC_GPR2_LVDS_CH0_MODE_MASK (3 << IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
	445	#define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED << \
	446	IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
	447	#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0 << \
	448	IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
	449	#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1 << \
	450	IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
	451
9583dfab SB	452	/* System Reset Controller (SRC) */
	453	struct src {
	454	u32 scr;
	455	u32 sbmr;
	456	u32 srsr;
	457	u32 reserved1[2];
	458	u32 sisr;
	459	u32 simr;
	460	};
565e39c5	461
124a06d7 TK	462	struct srtc_regs {
	463	u32 lpscmr; /* 0x00 */
	464	u32 lpsclr; /* 0x04 */
	465	u32 lpsar; /* 0x08 */
	466	u32 lpsmcr; /* 0x0c */
	467	u32 lpcr; /* 0x10 */
	468	u32 lpsr; /* 0x14 */
	469	u32 lppdr; /* 0x18 */
	470	u32 lpgr; /* 0x1c */
	471	u32 hpcmr; /* 0x20 */
	472	u32 hpclr; /* 0x24 */
	473	u32 hpamr; /* 0x28 */
	474	u32 hpalr; /* 0x2c */
	475	u32 hpcr; /* 0x30 */
	476	u32 hpisr; /* 0x34 */
	477	u32 hpienr; /* 0x38 */
	478	};
	479
ac87c17d SB	480	/* CSPI registers */
	481	struct cspi_regs {
	482	u32 rxdata;
	483	u32 txdata;
	484	u32 ctrl;
	485	u32 cfg;
	486	u32 intr;
	487	u32 dma;
	488	u32 stat;
	489	u32 period;
	490	};
	491
565e39c5 LHR	492	struct iim_regs {
	493	u32 stat;
	494	u32 statm;
	495	u32 err;
	496	u32 emask;
	497	u32 fctl;
	498	u32 ua;
	499	u32 la;
	500	u32 sdat;
	501	u32 prev;
	502	u32 srev;
8f3ff11c	503	u32 prg_p;
565e39c5 LHR	504	u32 scs0;
	505	u32 scs1;
	506	u32 scs2;
	507	u32 scs3;
	508	u32 res0[0x1f1];
	509	struct fuse_bank {
	510	u32 fuse_regs[0x20];
	511	u32 fuse_rsvd[0xe0];
8f3ff11c	512	#if defined(CONFIG_MX51)
565e39c5	513	} bank[4];
8f3ff11c BT	514	#elif defined(CONFIG_MX53)
	515	} bank[5];
	516	#endif
565e39c5 LHR	517	};
565e39c5 LHR	518
54cd1dee	519	struct fuse_bank0_regs {
6adbd302 BT	520	u32 fuse0_7[8];
	521	u32 uid[8];
	522	u32 fuse16_23[8];
	523	#if defined(CONFIG_MX51)
	524	u32 imei[8];
	525	#elif defined(CONFIG_MX53)
54cd1dee	526	u32 gp[8];
6adbd302	527	#endif
54cd1dee FE	528	};
54cd1dee FE	529
565e39c5 LHR	530	struct fuse_bank1_regs {
	531	u32 fuse0_8[9];
	532	u32 mac_addr[6];
	533	u32 fuse15_31[0x11];
	534	};
	535
6adbd302 BT	536	#if defined(CONFIG_MX53)
	537	struct fuse_bank4_regs {
	538	u32 fuse0_4[5];
	539	u32 gp[3];
	540	u32 fuse8_31[0x18];
	541	};
	542	#endif
	543
065a1ece MW	544	#define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)
	545	#define PWMCR_DOZEEN (1 << 24)
	546	#define PWMCR_WAITEN (1 << 23)
	547	#define PWMCR_DBGEN (1 << 22)
	548	#define PWMCR_CLKSRC_IPG_HIGH (2 << 16)
	549	#define PWMCR_CLKSRC_IPG (1 << 16)
	550	#define PWMCR_EN (1 << 0)
	551
	552	struct pwm_regs {
	553	u32 cr;
	554	u32 sr;
	555	u32 ir;
	556	u32 sar;
	557	u32 pr;
	558	u32 cnr;
	559	};
	560
fb87a1ed SB	561	#endif /* __ASSEMBLER__*/
fb87a1ed SB	562
595f3e56	563	#endif /* __ASM_ARCH_MX5_IMX_REGS_H__ */