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| 67adcee0 SB |
1 | /* |
| 2 | * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. | |
| 3 | * | |
| 4 | * See file CREDITS for list of people who contributed to this | |
| 5 | * project. | |
| 6 | * | |
| 7 | * This program is free software; you can redistribute it and/or | |
| 8 | * modify it under the terms of the GNU General Public License as | |
| 9 | * published by the Free Software Foundation; either version 2 of | |
| 10 | * the License, or (at your option) any later version. | |
| 11 | * | |
| 12 | * This program is distributed in the hope that it will be useful, | |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 15 | * GNU General Public License for more details. | |
| 16 | * | |
| 17 | * You should have received a copy of the GNU General Public License | |
| 18 | * along with this program; if not, write to the Free Software | |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 20 | * MA 02111-1307 USA | |
| 21 | */ | |
| 22 | ||
| ff9f475d JL |
23 | #ifndef __MACH_MX5_IOMUX_H__ |
| 24 | #define __MACH_MX5_IOMUX_H__ | |
| 67adcee0 SB |
25 | |
| 26 | #include <common.h> | |
| 27 | #include <asm/io.h> | |
| 28 | #include <asm/arch/imx-regs.h> | |
| ff9f475d | 29 | #include <asm/arch/mx5x_pins.h> |
| 67adcee0 SB |
30 | |
| 31 | typedef unsigned int iomux_pin_name_t; | |
| 32 | ||
| 33 | /* various IOMUX output functions */ | |
| 34 | typedef enum iomux_config { | |
| 35 | IOMUX_CONFIG_ALT0, /*!< used as alternate function 0 */ | |
| 36 | IOMUX_CONFIG_ALT1, /*!< used as alternate function 1 */ | |
| 37 | IOMUX_CONFIG_ALT2, /*!< used as alternate function 2 */ | |
| 38 | IOMUX_CONFIG_ALT3, /*!< used as alternate function 3 */ | |
| 39 | IOMUX_CONFIG_ALT4, /*!< used as alternate function 4 */ | |
| 40 | IOMUX_CONFIG_ALT5, /*!< used as alternate function 5 */ | |
| 41 | IOMUX_CONFIG_ALT6, /*!< used as alternate function 6 */ | |
| 42 | IOMUX_CONFIG_ALT7, /*!< used as alternate function 7 */ | |
| 43 | IOMUX_CONFIG_GPIO, /*!< added to help user use GPIO mode */ | |
| 44 | IOMUX_CONFIG_SION = 0x1 << 4, /*!< used as LOOPBACK:MUX SION bit */ | |
| 45 | } iomux_pin_cfg_t; | |
| 46 | ||
| 47 | /* various IOMUX pad functions */ | |
| 48 | typedef enum iomux_pad_config { | |
| 49 | PAD_CTL_SRE_SLOW = 0x0 << 0, /* Slow slew rate */ | |
| 50 | PAD_CTL_SRE_FAST = 0x1 << 0, /* Fast slew rate */ | |
| 51 | PAD_CTL_DRV_LOW = 0x0 << 1, /* Low drive strength */ | |
| 52 | PAD_CTL_DRV_MEDIUM = 0x1 << 1, /* Medium drive strength */ | |
| 53 | PAD_CTL_DRV_HIGH = 0x2 << 1, /* High drive strength */ | |
| 54 | PAD_CTL_DRV_MAX = 0x3 << 1, /* Max drive strength */ | |
| 55 | PAD_CTL_ODE_OPENDRAIN_NONE = 0x0 << 3, /* Opendrain disable */ | |
| 56 | PAD_CTL_ODE_OPENDRAIN_ENABLE = 0x1 << 3,/* Opendrain enable */ | |
| 57 | PAD_CTL_100K_PD = 0x0 << 4, /* 100Kohm pulldown */ | |
| 58 | PAD_CTL_47K_PU = 0x1 << 4, /* 47Kohm pullup */ | |
| 59 | PAD_CTL_100K_PU = 0x2 << 4, /* 100Kohm pullup */ | |
| 60 | PAD_CTL_22K_PU = 0x3 << 4, /* 22Kohm pullup */ | |
| 61 | PAD_CTL_PUE_KEEPER = 0x0 << 6, /* enable pulldown */ | |
| 62 | PAD_CTL_PUE_PULL = 0x1 << 6, /* enable pullup */ | |
| 63 | PAD_CTL_PKE_NONE = 0x0 << 7, /* Disable pullup/pulldown */ | |
| 64 | PAD_CTL_PKE_ENABLE = 0x1 << 7, /* Enable pullup/pulldown */ | |
| 65 | PAD_CTL_HYS_NONE = 0x0 << 8, /* Hysteresis disabled */ | |
| 66 | PAD_CTL_HYS_ENABLE = 0x1 << 8, /* Hysteresis enabled */ | |
| 67 | PAD_CTL_DDR_INPUT_CMOS = 0x0 << 9,/* DDR input CMOS */ | |
| 68 | PAD_CTL_DDR_INPUT_DDR = 0x1 << 9,/* DDR input DDR */ | |
| 69 | PAD_CTL_DRV_VOT_LOW = 0x0 << 13, /* Low voltage mode */ | |
| 70 | PAD_CTL_DRV_VOT_HIGH = 0x1 << 13,/* High voltage mode */ | |
| 71 | } iomux_pad_config_t; | |
| 72 | ||
| 73 | /* various IOMUX input select register index */ | |
| 74 | typedef enum iomux_input_select { | |
| 75 | MUX_IN_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0, | |
| 76 | MUX_IN_AUDMUX_P4_INPUT_DB_AMX_SELECT_I, | |
| 77 | MUX_IN_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT, | |
| 78 | MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT, | |
| 79 | MUX_IN_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT, | |
| 80 | MUX_IN_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT, | |
| 81 | MUX_IN_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT, | |
| 82 | MUX_IN_AUDMUX_P5_INPUT_RXFS_AMX_SELECT, | |
| 83 | MUX_IN_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT, | |
| 84 | MUX_IN_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT, | |
| 85 | MUX_IN_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT, | |
| 86 | MUX_IN_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT, | |
| 87 | MUX_IN_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT, | |
| 88 | MUX_IN_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT, | |
| 89 | MUX_IN_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT, | |
| 90 | MUX_IN_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT, | |
| 91 | MUX_IN_CCM_IPP_DI_CLK_SELECT_INPUT, | |
| 92 | /* TO2 */ | |
| 93 | MUX_IN_CCM_IPP_DI1_CLK_SELECT_INPUT, | |
| 94 | MUX_IN_CCM_PLL1_BYPASS_CLK_SELECT_INPUT, | |
| 95 | MUX_IN_CCM_PLL2_BYPASS_CLK_SELECT_INPUT, | |
| 96 | MUX_IN_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT, | |
| 97 | MUX_IN_CSPI_IPP_IND_MISO_SELECT_INPUT, | |
| 98 | MUX_IN_CSPI_IPP_IND_MOSI_SELECT_INPUT, | |
| 99 | MUX_IN_CSPI_IPP_IND_SS_B_1_SELECT_INPUT, | |
| 100 | MUX_IN_CSPI_IPP_IND_SS_B_2_SELECT_INPUT, | |
| 101 | MUX_IN_CSPI_IPP_IND_SS_B_3_SELECT_INPUT, | |
| 102 | MUX_IN_DPLLIP1_L1T_TOG_EN_SELECT_INPUT, | |
| 103 | /* TO2 */ | |
| 104 | MUX_IN_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT, | |
| 105 | MUX_IN_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT, | |
| 106 | MUX_IN_EMI_IPP_IND_RDY_INT_SELECT_INPUT, | |
| 107 | MUX_IN_ESDHC3_IPP_DAT0_IN_SELECT_INPUT, | |
| 108 | MUX_IN_ESDHC3_IPP_DAT1_IN_SELECT_INPUT, | |
| 109 | MUX_IN_ESDHC3_IPP_DAT2_IN_SELECT_INPUT, | |
| 110 | MUX_IN_ESDHC3_IPP_DAT3_IN_SELECT_INPUT, | |
| 111 | MUX_IN_FEC_FEC_COL_SELECT_INPUT, | |
| 112 | MUX_IN_FEC_FEC_CRS_SELECT_INPUT, | |
| 113 | MUX_IN_FEC_FEC_MDI_SELECT_INPUT, | |
| 114 | MUX_IN_FEC_FEC_RDATA_0_SELECT_INPUT, | |
| 115 | MUX_IN_FEC_FEC_RDATA_1_SELECT_INPUT, | |
| 116 | MUX_IN_FEC_FEC_RDATA_2_SELECT_INPUT, | |
| 117 | MUX_IN_FEC_FEC_RDATA_3_SELECT_INPUT, | |
| 118 | MUX_IN_FEC_FEC_RX_CLK_SELECT_INPUT, | |
| 119 | MUX_IN_FEC_FEC_RX_DV_SELECT_INPUT, | |
| 120 | MUX_IN_FEC_FEC_RX_ER_SELECT_INPUT, | |
| 121 | MUX_IN_FEC_FEC_TX_CLK_SELECT_INPUT, | |
| 122 | MUX_IN_GPIO3_IPP_IND_G_IN_1_SELECT_INPUT, | |
| 123 | MUX_IN_GPIO3_IPP_IND_G_IN_2_SELECT_INPUT, | |
| 124 | MUX_IN_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT, | |
| 125 | MUX_IN_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT, | |
| 126 | MUX_IN_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT, | |
| 127 | MUX_IN_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT, | |
| 128 | MUX_IN_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT, | |
| 129 | MUX_IN_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT, | |
| 130 | /* TO2 */ | |
| 131 | MUX_IN_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT, | |
| 132 | MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT, | |
| 133 | MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS2_DATA_EN_SELECT_INPUT, | |
| 134 | /* TO2 */ | |
| 135 | MUX_IN_HSC_MIPI_MIX_PAR_VSYNC_SELECT_INPUT, | |
| 136 | /* TO2 */ | |
| 137 | MUX_IN_HSC_MIPI_MIX_PAR_DI_WAIT_SELECT_INPUT, | |
| 138 | MUX_IN_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT, | |
| 139 | MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT, | |
| 140 | MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT, | |
| 141 | MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT, | |
| 142 | MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT, | |
| 143 | ||
| 144 | MUX_IN_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT, | |
| 145 | ||
| 146 | MUX_IN_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT, | |
| 147 | ||
| 148 | MUX_IN_KPP_IPP_IND_COL_6_SELECT_INPUT, | |
| 149 | MUX_IN_KPP_IPP_IND_COL_7_SELECT_INPUT, | |
| 150 | MUX_IN_KPP_IPP_IND_ROW_4_SELECT_INPUT, | |
| 151 | MUX_IN_KPP_IPP_IND_ROW_5_SELECT_INPUT, | |
| 152 | MUX_IN_KPP_IPP_IND_ROW_6_SELECT_INPUT, | |
| 153 | MUX_IN_KPP_IPP_IND_ROW_7_SELECT_INPUT, | |
| 154 | MUX_IN_UART1_IPP_UART_RTS_B_SELECT_INPUT, | |
| 155 | MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, | |
| 156 | MUX_IN_UART2_IPP_UART_RTS_B_SELECT_INPUT, | |
| 157 | MUX_IN_UART2_IPP_UART_RXD_MUX_SELECT_INPUT, | |
| 158 | MUX_IN_UART3_IPP_UART_RTS_B_SELECT_INPUT, | |
| 159 | MUX_IN_UART3_IPP_UART_RXD_MUX_SELECT_INPUT, | |
| 160 | MUX_IN_USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT, | |
| 161 | MUX_IN_USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT, | |
| 162 | MUX_IN_USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT, | |
| 163 | MUX_IN_USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT, | |
| 164 | MUX_IN_USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT, | |
| 165 | MUX_IN_USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT, | |
| 166 | MUX_IN_USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT, | |
| 167 | MUX_IN_USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT, | |
| 168 | MUX_IN_USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT, | |
| 169 | MUX_IN_USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT, | |
| 170 | MUX_IN_USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT, | |
| 171 | MUX_IN_USBOH3_IPP_IND_UH3_STP_SELECT_INPUT, | |
| 172 | MUX_INPUT_NUM_MUX, | |
| 173 | } iomux_input_select_t; | |
| 174 | ||
| 175 | /* various IOMUX input functions */ | |
| 176 | typedef enum iomux_input_config { | |
| 177 | INPUT_CTL_PATH0 = 0x0, | |
| 178 | INPUT_CTL_PATH1, | |
| 179 | INPUT_CTL_PATH2, | |
| 180 | INPUT_CTL_PATH3, | |
| 181 | INPUT_CTL_PATH4, | |
| 182 | INPUT_CTL_PATH5, | |
| 183 | INPUT_CTL_PATH6, | |
| 184 | INPUT_CTL_PATH7, | |
| 185 | } iomux_input_config_t; | |
| 186 | ||
| 187 | void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config); | |
| 188 | void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config); | |
| 189 | void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config); | |
| 190 | unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin); | |
| 191 | void mxc_iomux_set_input(iomux_input_select_t input, u32 config); | |
| 192 | ||
| ff9f475d | 193 | #endif /* __MACH_MX5_IOMUX_H__ */ |