projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 23608e23 JL |
1 | /* |
| 2 | * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. | |
| 3 | * | |
| 1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 23608e23 JL |
5 | */ |
| 6 | ||
| 7 | #ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__ | |
| 8 | #define __ARCH_ARM_MACH_MX6_CCM_REGS_H__ | |
| 9 | ||
| 492938a3 | 10 | #define CCM_CCOSR 0x020c4060 |
| 4f60c49a EN |
11 | #define CCM_CCGR0 0x020C4068 |
| 12 | #define CCM_CCGR1 0x020C406c | |
| 13 | #define CCM_CCGR2 0x020C4070 | |
| 14 | #define CCM_CCGR3 0x020C4074 | |
| 15 | #define CCM_CCGR4 0x020C4078 | |
| 16 | #define CCM_CCGR5 0x020C407c | |
| 17 | #define CCM_CCGR6 0x020C4080 | |
| 18 | ||
| 19 | #define PMU_MISC2 0x020C8170 | |
| 20 | ||
| 21 | #ifndef __ASSEMBLY__ | |
| 6a376046 | 22 | struct mxc_ccm_reg { |
| 23608e23 JL |
23 | u32 ccr; /* 0x0000 */ |
| 24 | u32 ccdr; | |
| 25 | u32 csr; | |
| 26 | u32 ccsr; | |
| 27 | u32 cacrr; /* 0x0010*/ | |
| 28 | u32 cbcdr; | |
| 29 | u32 cbcmr; | |
| 30 | u32 cscmr1; | |
| 31 | u32 cscmr2; /* 0x0020 */ | |
| 32 | u32 cscdr1; | |
| 33 | u32 cs1cdr; | |
| 34 | u32 cs2cdr; | |
| 35 | u32 cdcdr; /* 0x0030 */ | |
| da6df2d1 | 36 | u32 chsccdr; |
| 23608e23 JL |
37 | u32 cscdr2; |
| 38 | u32 cscdr3; | |
| 39 | u32 cscdr4; /* 0x0040 */ | |
| 40 | u32 resv0; | |
| 41 | u32 cdhipr; | |
| 42 | u32 cdcr; | |
| 43 | u32 ctor; /* 0x0050 */ | |
| 44 | u32 clpcr; | |
| 45 | u32 cisr; | |
| 46 | u32 cimr; | |
| 47 | u32 ccosr; /* 0x0060 */ | |
| 48 | u32 cgpr; | |
| 49 | u32 CCGR0; | |
| 50 | u32 CCGR1; | |
| 51 | u32 CCGR2; /* 0x0070 */ | |
| 52 | u32 CCGR3; | |
| 53 | u32 CCGR4; | |
| 54 | u32 CCGR5; | |
| 55 | u32 CCGR6; /* 0x0080 */ | |
| 56 | u32 CCGR7; | |
| 57 | u32 cmeor; | |
| 58 | u32 resv[0xfdd]; | |
| 59 | u32 analog_pll_sys; /* 0x4000 */ | |
| 60 | u32 analog_pll_sys_set; | |
| 61 | u32 analog_pll_sys_clr; | |
| 62 | u32 analog_pll_sys_tog; | |
| 63 | u32 analog_usb1_pll_480_ctrl; /* 0x4010 */ | |
| 64 | u32 analog_usb1_pll_480_ctrl_set; | |
| 65 | u32 analog_usb1_pll_480_ctrl_clr; | |
| 66 | u32 analog_usb1_pll_480_ctrl_tog; | |
| 67 | u32 analog_reserved0[4]; | |
| 68 | u32 analog_pll_528; /* 0x4030 */ | |
| 69 | u32 analog_pll_528_set; | |
| 70 | u32 analog_pll_528_clr; | |
| 71 | u32 analog_pll_528_tog; | |
| 72 | u32 analog_pll_528_ss; /* 0x4040 */ | |
| 73 | u32 analog_reserved1[3]; | |
| 74 | u32 analog_pll_528_num; /* 0x4050 */ | |
| 75 | u32 analog_reserved2[3]; | |
| 76 | u32 analog_pll_528_denom; /* 0x4060 */ | |
| 77 | u32 analog_reserved3[3]; | |
| 78 | u32 analog_pll_audio; /* 0x4070 */ | |
| 79 | u32 analog_pll_audio_set; | |
| 80 | u32 analog_pll_audio_clr; | |
| 81 | u32 analog_pll_audio_tog; | |
| 82 | u32 analog_pll_audio_num; /* 0x4080*/ | |
| 83 | u32 analog_reserved4[3]; | |
| 84 | u32 analog_pll_audio_denom; /* 0x4090 */ | |
| 85 | u32 analog_reserved5[3]; | |
| 86 | u32 analog_pll_video; /* 0x40a0 */ | |
| 87 | u32 analog_pll_video_set; | |
| 88 | u32 analog_pll_video_clr; | |
| 89 | u32 analog_pll_video_tog; | |
| 90 | u32 analog_pll_video_num; /* 0x40b0 */ | |
| 91 | u32 analog_reserved6[3]; | |
| 92 | u32 analog_pll_vedio_denon; /* 0x40c0 */ | |
| 93 | u32 analog_reserved7[7]; | |
| 94 | u32 analog_pll_enet; /* 0x40e0 */ | |
| 95 | u32 analog_pll_enet_set; | |
| 96 | u32 analog_pll_enet_clr; | |
| 97 | u32 analog_pll_enet_tog; | |
| 98 | u32 analog_pfd_480; /* 0x40f0 */ | |
| 99 | u32 analog_pfd_480_set; | |
| 100 | u32 analog_pfd_480_clr; | |
| 101 | u32 analog_pfd_480_tog; | |
| 102 | u32 analog_pfd_528; /* 0x4100 */ | |
| 103 | u32 analog_pfd_528_set; | |
| 104 | u32 analog_pfd_528_clr; | |
| 105 | u32 analog_pfd_528_tog; | |
| 106 | }; | |
| 4f60c49a | 107 | #endif |
| 23608e23 JL |
108 | |
| 109 | /* Define the bits in register CCR */ | |
| 110 | #define MXC_CCM_CCR_RBC_EN (1 << 27) | |
| 111 | #define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << 21) | |
| 112 | #define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21 | |
| 113 | #define MXC_CCM_CCR_WB_COUNT_MASK 0x7 | |
| 114 | #define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16) | |
| 115 | #define MXC_CCM_CCR_COSC_EN (1 << 12) | |
| 116 | #define MXC_CCM_CCR_OSCNT_MASK 0xFF | |
| 117 | #define MXC_CCM_CCR_OSCNT_OFFSET 0 | |
| 118 | ||
| 119 | /* Define the bits in register CCDR */ | |
| 120 | #define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16) | |
| 121 | #define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17) | |
| 122 | ||
| 123 | /* Define the bits in register CSR */ | |
| 124 | #define MXC_CCM_CSR_COSC_READY (1 << 5) | |
| 125 | #define MXC_CCM_CSR_REF_EN_B (1 << 0) | |
| 126 | ||
| 127 | /* Define the bits in register CCSR */ | |
| 128 | #define MXC_CCM_CCSR_PDF_540M_AUTO_DIS (1 << 15) | |
| 129 | #define MXC_CCM_CCSR_PDF_720M_AUTO_DIS (1 << 14) | |
| 130 | #define MXC_CCM_CCSR_PDF_454M_AUTO_DIS (1 << 13) | |
| 131 | #define MXC_CCM_CCSR_PDF_508M_AUTO_DIS (1 << 12) | |
| 132 | #define MXC_CCM_CCSR_PDF_594M_AUTO_DIS (1 << 11) | |
| 133 | #define MXC_CCM_CCSR_PDF_352M_AUTO_DIS (1 << 10) | |
| 134 | #define MXC_CCM_CCSR_PDF_400M_AUTO_DIS (1 << 9) | |
| 135 | #define MXC_CCM_CCSR_STEP_SEL (1 << 8) | |
| 136 | #define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2) | |
| 137 | #define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1) | |
| 138 | #define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0) | |
| 139 | ||
| 140 | /* Define the bits in register CACRR */ | |
| 141 | #define MXC_CCM_CACRR_ARM_PODF_OFFSET 0 | |
| 142 | #define MXC_CCM_CACRR_ARM_PODF_MASK 0x7 | |
| 143 | ||
| 144 | /* Define the bits in register CBCDR */ | |
| 145 | #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << 27) | |
| 146 | #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27 | |
| 147 | #define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL (1 << 26) | |
| 148 | #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25) | |
| 149 | #define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19) | |
| 150 | #define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19 | |
| 151 | #define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << 16) | |
| 152 | #define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16 | |
| 153 | #define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) | |
| 154 | #define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10 | |
| 155 | #define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) | |
| 156 | #define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8 | |
| 157 | #define MXC_CCM_CBCDR_AXI_ALT_SEL (1 << 7) | |
| 158 | #define MXC_CCM_CBCDR_AXI_SEL (1 << 6) | |
| 159 | #define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << 3) | |
| 160 | #define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET 3 | |
| 161 | #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << 0) | |
| 162 | #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET 0 | |
| 163 | ||
| 164 | /* Define the bits in register CBCMR */ | |
| 165 | #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << 29) | |
| 166 | #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29 | |
| 167 | #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << 26) | |
| 168 | #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26 | |
| 169 | #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << 23) | |
| 170 | #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23 | |
| 171 | #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21) | |
| 172 | #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21 | |
| 173 | #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL (1 << 20) | |
| 174 | #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18) | |
| 175 | #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18 | |
| 176 | #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16) | |
| 177 | #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET 16 | |
| 178 | #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) | |
| 179 | #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14 | |
| 180 | #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << 12) | |
| 181 | #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET 12 | |
| 182 | #define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11) | |
| 183 | #define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10) | |
| 184 | #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << 8) | |
| 185 | #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8 | |
| 186 | #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4) | |
| 187 | #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4 | |
| 188 | #define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL (1 << 1) | |
| 189 | #define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL (1 << 0) | |
| 190 | ||
| 191 | /* Define the bits in register CSCMR1 */ | |
| 192 | #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29) | |
| 193 | #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29 | |
| 194 | #define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << 27) | |
| 195 | #define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27 | |
| 196 | #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23) | |
| 197 | #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23 | |
| 198 | #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20) | |
| 199 | #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20 | |
| 200 | #define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19) | |
| 201 | #define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18) | |
| 202 | #define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17) | |
| 203 | #define MXC_CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16) | |
| 204 | #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << 14) | |
| 205 | #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET 14 | |
| 206 | #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) | |
| 207 | #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12 | |
| 208 | #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10) | |
| 209 | #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10 | |
| 210 | #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F | |
| 211 | ||
| 212 | /* Define the bits in register CSCMR2 */ | |
| 213 | #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19) | |
| 214 | #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19 | |
| 215 | #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11) | |
| 216 | #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10) | |
| 217 | #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3F << 2) | |
| 218 | #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 2 | |
| 219 | ||
| 220 | /* Define the bits in register CSCDR1 */ | |
| 221 | #define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << 25) | |
| 222 | #define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25 | |
| 223 | #define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << 22) | |
| 224 | #define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22 | |
| 225 | #define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19) | |
| 226 | #define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET 19 | |
| 227 | #define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << 16) | |
| 228 | #define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET 16 | |
| 229 | #define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << 11) | |
| 230 | #define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET 11 | |
| 231 | #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8 | |
| 232 | #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) | |
| 233 | #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6 | |
| 234 | #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) | |
| 25b4aa14 FE |
235 | #ifdef CONFIG_MX6SL |
| 236 | #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x1F | |
| 237 | #define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6) | |
| 238 | #else | |
| 23608e23 | 239 | #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F |
| 25b4aa14 | 240 | #endif |
| 23608e23 JL |
241 | #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0 |
| 242 | ||
| 243 | /* Define the bits in register CS1CDR */ | |
| 244 | #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25) | |
| 245 | #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25 | |
| 246 | #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << 16) | |
| 247 | #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET 16 | |
| 248 | #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << 9) | |
| 249 | #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET 9 | |
| 250 | #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6) | |
| 251 | #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET 6 | |
| 252 | #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK 0x3F | |
| 253 | #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0 | |
| 254 | ||
| 255 | /* Define the bits in register CS2CDR */ | |
| 256 | #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21) | |
| 257 | #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21 | |
| b29ca4a1 | 258 | #define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << 21) |
| 23608e23 JL |
259 | #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18) |
| 260 | #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18 | |
| b29ca4a1 | 261 | #define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << 18) |
| 23608e23 JL |
262 | #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << 16) |
| 263 | #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 16 | |
| b29ca4a1 | 264 | #define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) (((v) & 0x3) << 16) |
| 23608e23 JL |
265 | #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12) |
| 266 | #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12 | |
| 267 | #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9) | |
| 268 | #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET 9 | |
| 269 | #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6) | |
| 270 | #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET 6 | |
| 271 | #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK 0x3F | |
| 272 | #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET 0 | |
| 273 | ||
| 274 | /* Define the bits in register CDCDR */ | |
| 275 | #define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << 29) | |
| 276 | #define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET 29 | |
| 277 | #define MXC_CCM_CDCDR_HSI_TX_CLK_SEL (1 << 28) | |
| 278 | #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25) | |
| 279 | #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET 25 | |
| 280 | #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << 19) | |
| 281 | #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 19 | |
| 282 | #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << 20) | |
| 283 | #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET 20 | |
| 284 | #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 12) | |
| 285 | #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET 12 | |
| 286 | #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << 9) | |
| 287 | #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET 9 | |
| 288 | #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << 7) | |
| 289 | #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7 | |
| 290 | ||
| 291 | /* Define the bits in register CHSCCDR */ | |
| 292 | #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << 15) | |
| 293 | #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15 | |
| 294 | #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << 12) | |
| 295 | #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET 12 | |
| 296 | #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << 9) | |
| 297 | #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET 9 | |
| 298 | #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << 6) | |
| 299 | #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET 6 | |
| 300 | #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << 3) | |
| 301 | #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3 | |
| 302 | #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7) | |
| 303 | #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0 | |
| 304 | ||
| 344da71a EN |
305 | #define CHSCCDR_CLK_SEL_LDB_DI0 3 |
| 306 | #define CHSCCDR_PODF_DIVIDE_BY_3 2 | |
| 307 | #define CHSCCDR_IPU_PRE_CLK_540M_PFD 5 | |
| 308 | ||
| 23608e23 JL |
309 | /* Define the bits in register CSCDR2 */ |
| 310 | #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19) | |
| 311 | #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19 | |
| 312 | #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15) | |
| 313 | #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET 15 | |
| 314 | #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK (0x7 << 12) | |
| 315 | #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET 12 | |
| 316 | #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK (0x7 << 9) | |
| 317 | #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET 9 | |
| 318 | #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << 6) | |
| 319 | #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET 6 | |
| 320 | #define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK (0x7 << 3) | |
| 321 | #define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET 3 | |
| 322 | #define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK 0x7 | |
| 323 | #define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET 0 | |
| 324 | ||
| 325 | /* Define the bits in register CSCDR3 */ | |
| 326 | #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << 16) | |
| 327 | #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET 16 | |
| 328 | #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << 14) | |
| 329 | #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET 14 | |
| 330 | #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << 11) | |
| 331 | #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET 11 | |
| 332 | #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << 9) | |
| 333 | #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET 9 | |
| 334 | ||
| 335 | /* Define the bits in register CDHIPR */ | |
| 336 | #define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) | |
| 337 | #define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5) | |
| 338 | #define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY (1 << 4) | |
| 339 | #define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3) | |
| 340 | #define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2) | |
| 341 | #define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1) | |
| 342 | #define MXC_CCM_CDHIPR_AXI_PODF_BUSY 1 | |
| 343 | ||
| 344 | /* Define the bits in register CLPCR */ | |
| 345 | #define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27) | |
| 346 | #define MXC_CCM_CLPCR_MASK_SCU_IDLE (1 << 26) | |
| 347 | #define MXC_CCM_CLPCR_MASK_CORE3_WFI (1 << 25) | |
| 348 | #define MXC_CCM_CLPCR_MASK_CORE2_WFI (1 << 24) | |
| 349 | #define MXC_CCM_CLPCR_MASK_CORE1_WFI (1 << 23) | |
| 350 | #define MXC_CCM_CLPCR_MASK_CORE0_WFI (1 << 22) | |
| 351 | #define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS (1 << 21) | |
| 352 | #define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS (1 << 19) | |
| 353 | #define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17) | |
| 354 | #define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 17) | |
| 355 | #define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11) | |
| 356 | #define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9) | |
| 357 | #define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9 | |
| 358 | #define MXC_CCM_CLPCR_VSTBY (1 << 8) | |
| 359 | #define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7) | |
| 360 | #define MXC_CCM_CLPCR_SBYOS (1 << 6) | |
| 361 | #define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5) | |
| 362 | #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3) | |
| 363 | #define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET 3 | |
| 364 | #define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2) | |
| 365 | #define MXC_CCM_CLPCR_LPM_MASK 0x3 | |
| 366 | #define MXC_CCM_CLPCR_LPM_OFFSET 0 | |
| 367 | ||
| 368 | /* Define the bits in register CISR */ | |
| 369 | #define MXC_CCM_CISR_ARM_PODF_LOADED (1 << 26) | |
| 370 | #define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED (1 << 23) | |
| 371 | #define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22) | |
| 372 | #define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED (1 << 21) | |
| 373 | #define MXC_CCM_CISR_AHB_PODF_LOADED (1 << 20) | |
| 374 | #define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19) | |
| 375 | #define MXC_CCM_CISR_AXI_PODF_LOADED (1 << 17) | |
| 376 | #define MXC_CCM_CISR_COSC_READY (1 << 6) | |
| 377 | #define MXC_CCM_CISR_LRF_PLL 1 | |
| 378 | ||
| 379 | /* Define the bits in register CIMR */ | |
| 380 | #define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26) | |
| 381 | #define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED (1 << 23) | |
| 382 | #define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22) | |
| 383 | #define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (1 << 21) | |
| 384 | #define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20) | |
| 385 | #define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 22) | |
| 386 | #define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17) | |
| 387 | #define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6) | |
| 388 | #define MXC_CCM_CIMR_MASK_LRF_PLL 1 | |
| 389 | ||
| 390 | /* Define the bits in register CCOSR */ | |
| 391 | #define MXC_CCM_CCOSR_CKO2_EN_OFFSET (1 << 24) | |
| 392 | #define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21) | |
| 393 | #define MXC_CCM_CCOSR_CKO2_DIV_OFFSET 21 | |
| 394 | #define MXC_CCM_CCOSR_CKO2_SEL_OFFSET 16 | |
| 395 | #define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16) | |
| 396 | #define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7) | |
| 397 | #define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4) | |
| 398 | #define MXC_CCM_CCOSR_CKOL_DIV_OFFSET 4 | |
| 399 | #define MXC_CCM_CCOSR_CKOL_SEL_MASK 0xF | |
| 400 | #define MXC_CCM_CCOSR_CKOL_SEL_OFFSET 0 | |
| 401 | ||
| 402 | /* Define the bits in registers CGPR */ | |
| 403 | #define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4) | |
| 404 | #define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2) | |
| 405 | #define MXC_CCM_CGPR_PMIC_DELAY_SCALER 1 | |
| 406 | ||
| 407 | /* Define the bits in registers CCGRx */ | |
| 408 | #define MXC_CCM_CCGR_CG_MASK 3 | |
| 409 | ||
| 0bb7e316 | 410 | #define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 0 |
| 51f329a7 | 411 | #define MXC_CCM_CCGR0_AIPS_TZ1_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ1_OFFSET) |
| 0bb7e316 | 412 | #define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 2 |
| 51f329a7 | 413 | #define MXC_CCM_CCGR0_AIPS_TZ2_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ2_OFFSET) |
| b29ca4a1 | 414 | #define MXC_CCM_CCGR0_APBHDMA_OFFSET 4 |
| 51f329a7 | 415 | #define MXC_CCM_CCGR0_APBHDMA_MASK (3 << MXC_CCM_CCGR0_APBHDMA_OFFSET) |
| 0bb7e316 | 416 | #define MXC_CCM_CCGR0_ASRC_OFFSET 6 |
| 51f329a7 | 417 | #define MXC_CCM_CCGR0_ASRC_MASK (3 << MXC_CCM_CCGR0_ASRC_OFFSET) |
| 0bb7e316 | 418 | #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET 8 |
| 51f329a7 | 419 | #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK (3 << MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET) |
| 0bb7e316 | 420 | #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET 10 |
| 51f329a7 | 421 | #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET) |
| 0bb7e316 | 422 | #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET 12 |
| 51f329a7 | 423 | #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET) |
| 0bb7e316 | 424 | #define MXC_CCM_CCGR0_CAN1_OFFSET 14 |
| 51f329a7 | 425 | #define MXC_CCM_CCGR0_CAN1_MASK (3 << MXC_CCM_CCGR0_CAN1_OFFSET) |
| 0bb7e316 | 426 | #define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET 16 |
| 51f329a7 | 427 | #define MXC_CCM_CCGR0_CAN1_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET) |
| 0bb7e316 | 428 | #define MXC_CCM_CCGR0_CAN2_OFFSET 18 |
| 51f329a7 | 429 | #define MXC_CCM_CCGR0_CAN2_MASK (3 << MXC_CCM_CCGR0_CAN2_OFFSET) |
| 0bb7e316 | 430 | #define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET 20 |
| 51f329a7 | 431 | #define MXC_CCM_CCGR0_CAN2_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET) |
| 0bb7e316 | 432 | #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET 22 |
| 51f329a7 | 433 | #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK (3 << MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET) |
| 0bb7e316 | 434 | #define MXC_CCM_CCGR0_DCIC1_OFFSET 24 |
| 51f329a7 | 435 | #define MXC_CCM_CCGR0_DCIC1_MASK (3 << MXC_CCM_CCGR0_DCIC1_OFFSET) |
| 0bb7e316 | 436 | #define MXC_CCM_CCGR0_DCIC2_OFFSET 26 |
| 51f329a7 | 437 | #define MXC_CCM_CCGR0_DCIC2_MASK (3 << MXC_CCM_CCGR0_DCIC2_OFFSET) |
| 0bb7e316 | 438 | #define MXC_CCM_CCGR0_DTCP_OFFSET 28 |
| 51f329a7 | 439 | #define MXC_CCM_CCGR0_DTCP_MASK (3 << MXC_CCM_CCGR0_DTCP_OFFSET) |
| 0bb7e316 EN |
440 | |
| 441 | #define MXC_CCM_CCGR1_ECSPI1S_OFFSET 0 | |
| 51f329a7 | 442 | #define MXC_CCM_CCGR1_ECSPI1S_MASK (3 << MXC_CCM_CCGR1_ECSPI1S_OFFSET) |
| 0bb7e316 | 443 | #define MXC_CCM_CCGR1_ECSPI2S_OFFSET 2 |
| 51f329a7 | 444 | #define MXC_CCM_CCGR1_ECSPI2S_MASK (3 << MXC_CCM_CCGR1_ECSPI2S_OFFSET) |
| 0bb7e316 | 445 | #define MXC_CCM_CCGR1_ECSPI3S_OFFSET 4 |
| 51f329a7 | 446 | #define MXC_CCM_CCGR1_ECSPI3S_MASK (3 << MXC_CCM_CCGR1_ECSPI3S_OFFSET) |
| 0bb7e316 | 447 | #define MXC_CCM_CCGR1_ECSPI4S_OFFSET 6 |
| 51f329a7 | 448 | #define MXC_CCM_CCGR1_ECSPI4S_MASK (3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET) |
| 0bb7e316 | 449 | #define MXC_CCM_CCGR1_ECSPI5S_OFFSET 8 |
| 51f329a7 | 450 | #define MXC_CCM_CCGR1_ECSPI5S_MASK (3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET) |
| 0bb7e316 | 451 | #define MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET 10 |
| 51f329a7 | 452 | #define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET) |
| 0bb7e316 | 453 | #define MXC_CCM_CCGR1_EPIT1S_OFFSET 12 |
| 51f329a7 | 454 | #define MXC_CCM_CCGR1_EPIT1S_MASK (3 << MXC_CCM_CCGR1_EPIT1S_OFFSET) |
| 0bb7e316 | 455 | #define MXC_CCM_CCGR1_EPIT2S_OFFSET 14 |
| 51f329a7 | 456 | #define MXC_CCM_CCGR1_EPIT2S_MASK (3 << MXC_CCM_CCGR1_EPIT2S_OFFSET) |
| 0bb7e316 | 457 | #define MXC_CCM_CCGR1_ESAIS_OFFSET 16 |
| 51f329a7 | 458 | #define MXC_CCM_CCGR1_ESAIS_MASK (3 << MXC_CCM_CCGR1_ESAIS_OFFSET) |
| 0bb7e316 | 459 | #define MXC_CCM_CCGR1_GPT_BUS_OFFSET 20 |
| 51f329a7 | 460 | #define MXC_CCM_CCGR1_GPT_BUS_MASK (3 << MXC_CCM_CCGR1_GPT_BUS_OFFSET) |
| 0bb7e316 | 461 | #define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET 22 |
| 51f329a7 | 462 | #define MXC_CCM_CCGR1_GPT_SERIAL_MASK (3 << MXC_CCM_CCGR1_GPT_SERIAL_OFFSET) |
| 0bb7e316 | 463 | #define MXC_CCM_CCGR1_GPU2D_OFFSET 24 |
| 51f329a7 | 464 | #define MXC_CCM_CCGR1_GPU2D_MASK (3 << MXC_CCM_CCGR1_GPU2D_OFFSET) |
| 0bb7e316 | 465 | #define MXC_CCM_CCGR1_GPU3D_OFFSET 26 |
| 51f329a7 | 466 | #define MXC_CCM_CCGR1_GPU3D_MASK (3 << MXC_CCM_CCGR1_GPU3D_OFFSET) |
| 0bb7e316 EN |
467 | |
| 468 | #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0 | |
| 51f329a7 | 469 | #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET) |
| 0bb7e316 | 470 | #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET 4 |
| 51f329a7 | 471 | #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET) |
| 0bb7e316 | 472 | #define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET 6 |
| 51f329a7 | 473 | #define MXC_CCM_CCGR2_I2C1_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET) |
| 0bb7e316 | 474 | #define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET 8 |
| 51f329a7 | 475 | #define MXC_CCM_CCGR2_I2C2_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET) |
| 0bb7e316 | 476 | #define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET 10 |
| 51f329a7 | 477 | #define MXC_CCM_CCGR2_I2C3_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET) |
| 0bb7e316 | 478 | #define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET 12 |
| 51f329a7 | 479 | #define MXC_CCM_CCGR2_OCOTP_CTRL_MASK (3 << MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET) |
| 0bb7e316 | 480 | #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET 14 |
| 51f329a7 | 481 | #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK (3 << MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET) |
| 0bb7e316 | 482 | #define MXC_CCM_CCGR2_IPMUX1_OFFSET 16 |
| 51f329a7 | 483 | #define MXC_CCM_CCGR2_IPMUX1_MASK (3 << MXC_CCM_CCGR2_IPMUX1_OFFSET) |
| 0bb7e316 | 484 | #define MXC_CCM_CCGR2_IPMUX2_OFFSET 18 |
| 51f329a7 | 485 | #define MXC_CCM_CCGR2_IPMUX2_MASK (3 << MXC_CCM_CCGR2_IPMUX2_OFFSET) |
| 0bb7e316 | 486 | #define MXC_CCM_CCGR2_IPMUX3_OFFSET 20 |
| 51f329a7 | 487 | #define MXC_CCM_CCGR2_IPMUX3_MASK (3 << MXC_CCM_CCGR2_IPMUX3_OFFSET) |
| 0bb7e316 | 488 | #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22 |
| 51f329a7 | 489 | #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET) |
| 0bb7e316 | 490 | #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET 24 |
| 51f329a7 | 491 | #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET) |
| 0bb7e316 | 492 | #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26 |
| 51f329a7 | 493 | #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET) |
| 0bb7e316 EN |
494 | |
| 495 | #define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0 | |
| 51f329a7 | 496 | #define MXC_CCM_CCGR3_IPU1_IPU_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET) |
| 0bb7e316 | 497 | #define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2 |
| 51f329a7 | 498 | #define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET) |
| 0bb7e316 | 499 | #define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET 4 |
| 51f329a7 | 500 | #define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET) |
| 0bb7e316 | 501 | #define MXC_CCM_CCGR3_IPU2_IPU_OFFSET 6 |
| 51f329a7 | 502 | #define MXC_CCM_CCGR3_IPU2_IPU_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET) |
| 0bb7e316 | 503 | #define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8 |
| 51f329a7 | 504 | #define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET) |
| 0bb7e316 | 505 | #define MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET 10 |
| 51f329a7 | 506 | #define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET) |
| 0bb7e316 | 507 | #define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12 |
| 51f329a7 | 508 | #define MXC_CCM_CCGR3_LDB_DI0_MASK (3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET) |
| 0bb7e316 | 509 | #define MXC_CCM_CCGR3_LDB_DI1_OFFSET 14 |
| 51f329a7 | 510 | #define MXC_CCM_CCGR3_LDB_DI1_MASK (3 << MXC_CCM_CCGR3_LDB_DI1_OFFSET) |
| 0bb7e316 | 511 | #define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET 16 |
| 51f329a7 | 512 | #define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3 << MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET) |
| 0bb7e316 | 513 | #define MXC_CCM_CCGR3_MLB_OFFSET 18 |
| 51f329a7 | 514 | #define MXC_CCM_CCGR3_MLB_MASK (3 << MXC_CCM_CCGR3_MLB_OFFSET) |
| 0bb7e316 | 515 | #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET 20 |
| 51f329a7 | 516 | #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET) |
| 0bb7e316 | 517 | #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET 22 |
| 51f329a7 | 518 | #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET) |
| 0bb7e316 | 519 | #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET 24 |
| 51f329a7 | 520 | #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET) |
| 0bb7e316 | 521 | #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26 |
| 51f329a7 | 522 | #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET) |
| 0bb7e316 | 523 | #define MXC_CCM_CCGR3_OCRAM_OFFSET 28 |
| 51f329a7 | 524 | #define MXC_CCM_CCGR3_OCRAM_MASK (3 << MXC_CCM_CCGR3_OCRAM_OFFSET) |
| 0bb7e316 | 525 | #define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET 30 |
| 51f329a7 | 526 | #define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET) |
| 0bb7e316 EN |
527 | |
| 528 | #define MXC_CCM_CCGR4_PCIE_OFFSET 0 | |
| 51f329a7 | 529 | #define MXC_CCM_CCGR4_PCIE_MASK (3 << MXC_CCM_CCGR4_PCIE_OFFSET) |
| 0bb7e316 | 530 | #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET 8 |
| 51f329a7 | 531 | #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET) |
| 0bb7e316 | 532 | #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET 12 |
| 51f329a7 | 533 | #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET) |
| 0bb7e316 | 534 | #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET 14 |
| 51f329a7 | 535 | #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET) |
| 0bb7e316 | 536 | #define MXC_CCM_CCGR4_PWM1_OFFSET 16 |
| 51f329a7 | 537 | #define MXC_CCM_CCGR4_PWM1_MASK (3 << MXC_CCM_CCGR4_PWM1_OFFSET) |
| 0bb7e316 | 538 | #define MXC_CCM_CCGR4_PWM2_OFFSET 18 |
| 51f329a7 | 539 | #define MXC_CCM_CCGR4_PWM2_MASK (3 << MXC_CCM_CCGR4_PWM2_OFFSET) |
| 0bb7e316 | 540 | #define MXC_CCM_CCGR4_PWM3_OFFSET 20 |
| 51f329a7 | 541 | #define MXC_CCM_CCGR4_PWM3_MASK (3 << MXC_CCM_CCGR4_PWM3_OFFSET) |
| 0bb7e316 | 542 | #define MXC_CCM_CCGR4_PWM4_OFFSET 22 |
| 51f329a7 | 543 | #define MXC_CCM_CCGR4_PWM4_MASK (3 << MXC_CCM_CCGR4_PWM4_OFFSET) |
| 0bb7e316 | 544 | #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET 24 |
| 51f329a7 | 545 | #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET) |
| 0bb7e316 | 546 | #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET 26 |
| 51f329a7 | 547 | #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET) |
| 0bb7e316 | 548 | #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET 28 |
| 51f329a7 | 549 | #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET) |
| 0bb7e316 | 550 | #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET 30 |
| 51f329a7 | 551 | #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET) |
| 0bb7e316 EN |
552 | |
| 553 | #define MXC_CCM_CCGR5_ROM_OFFSET 0 | |
| 51f329a7 | 554 | #define MXC_CCM_CCGR5_ROM_MASK (3 << MXC_CCM_CCGR5_ROM_OFFSET) |
| 0bb7e316 | 555 | #define MXC_CCM_CCGR5_SATA_OFFSET 4 |
| 51f329a7 | 556 | #define MXC_CCM_CCGR5_SATA_MASK (3 << MXC_CCM_CCGR5_SATA_OFFSET) |
| 0bb7e316 | 557 | #define MXC_CCM_CCGR5_SDMA_OFFSET 6 |
| 51f329a7 | 558 | #define MXC_CCM_CCGR5_SDMA_MASK (3 << MXC_CCM_CCGR5_SDMA_OFFSET) |
| 0bb7e316 | 559 | #define MXC_CCM_CCGR5_SPBA_OFFSET 12 |
| 51f329a7 | 560 | #define MXC_CCM_CCGR5_SPBA_MASK (3 << MXC_CCM_CCGR5_SPBA_OFFSET) |
| 0bb7e316 | 561 | #define MXC_CCM_CCGR5_SPDIF_OFFSET 14 |
| 51f329a7 | 562 | #define MXC_CCM_CCGR5_SPDIF_MASK (3 << MXC_CCM_CCGR5_SPDIF_OFFSET) |
| 0bb7e316 | 563 | #define MXC_CCM_CCGR5_SSI1_OFFSET 18 |
| 51f329a7 | 564 | #define MXC_CCM_CCGR5_SSI1_MASK (3 << MXC_CCM_CCGR5_SSI1_OFFSET) |
| 0bb7e316 | 565 | #define MXC_CCM_CCGR5_SSI2_OFFSET 20 |
| 51f329a7 | 566 | #define MXC_CCM_CCGR5_SSI2_MASK (3 << MXC_CCM_CCGR5_SSI2_OFFSET) |
| 0bb7e316 | 567 | #define MXC_CCM_CCGR5_SSI3_OFFSET 22 |
| 51f329a7 | 568 | #define MXC_CCM_CCGR5_SSI3_MASK (3 << MXC_CCM_CCGR5_SSI3_OFFSET) |
| 0bb7e316 | 569 | #define MXC_CCM_CCGR5_UART_OFFSET 24 |
| 51f329a7 | 570 | #define MXC_CCM_CCGR5_UART_MASK (3 << MXC_CCM_CCGR5_UART_OFFSET) |
| 0bb7e316 | 571 | #define MXC_CCM_CCGR5_UART_SERIAL_OFFSET 26 |
| 51f329a7 | 572 | #define MXC_CCM_CCGR5_UART_SERIAL_MASK (3 << MXC_CCM_CCGR5_UART_SERIAL_OFFSET) |
| 0bb7e316 EN |
573 | |
| 574 | #define MXC_CCM_CCGR6_USBOH3_OFFSET 0 | |
| 51f329a7 | 575 | #define MXC_CCM_CCGR6_USBOH3_MASK (3 << MXC_CCM_CCGR6_USBOH3_OFFSET) |
| 0bb7e316 | 576 | #define MXC_CCM_CCGR6_USDHC1_OFFSET 2 |
| 51f329a7 | 577 | #define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET) |
| 0bb7e316 | 578 | #define MXC_CCM_CCGR6_USDHC2_OFFSET 4 |
| 51f329a7 | 579 | #define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET) |
| 0bb7e316 | 580 | #define MXC_CCM_CCGR6_USDHC3_OFFSET 6 |
| 51f329a7 | 581 | #define MXC_CCM_CCGR6_USDHC3_MASK (3 << MXC_CCM_CCGR6_USDHC3_OFFSET) |
| 0bb7e316 | 582 | #define MXC_CCM_CCGR6_USDHC4_OFFSET 8 |
| 51f329a7 | 583 | #define MXC_CCM_CCGR6_USDHC4_MASK (3 << MXC_CCM_CCGR6_USDHC4_OFFSET) |
| 0bb7e316 | 584 | #define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10 |
| 51f329a7 | 585 | #define MXC_CCM_CCGR6_EMI_SLOW_MASK (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET) |
| 0bb7e316 | 586 | #define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12 |
| 51f329a7 | 587 | #define MXC_CCM_CCGR6_VDOAXICLK_MASK (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET) |
| 0bb7e316 | 588 | |
| 23608e23 JL |
589 | #define BM_ANADIG_PLL_SYS_LOCK 0x80000000 |
| 590 | #define BP_ANADIG_PLL_SYS_RSVD0 20 | |
| 591 | #define BM_ANADIG_PLL_SYS_RSVD0 0x7FF00000 | |
| 592 | #define BF_ANADIG_PLL_SYS_RSVD0(v) \ | |
| 593 | (((v) << 20) & BM_ANADIG_PLL_SYS_RSVD0) | |
| 594 | #define BM_ANADIG_PLL_SYS_PLL_SEL 0x00080000 | |
| 595 | #define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL 0x00040000 | |
| 596 | #define BM_ANADIG_PLL_SYS_LVDS_SEL 0x00020000 | |
| 597 | #define BM_ANADIG_PLL_SYS_BYPASS 0x00010000 | |
| 598 | #define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC 14 | |
| 599 | #define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC 0x0000C000 | |
| 600 | #define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v) \ | |
| 601 | (((v) << 14) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC) | |
| 602 | #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M 0x0 | |
| 603 | #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1 | |
| 604 | #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2 | |
| 605 | #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR 0x3 | |
| 606 | #define BM_ANADIG_PLL_SYS_ENABLE 0x00002000 | |
| 607 | #define BM_ANADIG_PLL_SYS_POWERDOWN 0x00001000 | |
| 608 | #define BM_ANADIG_PLL_SYS_HOLD_RING_OFF 0x00000800 | |
| 609 | #define BM_ANADIG_PLL_SYS_DOUBLE_CP 0x00000400 | |
| 610 | #define BM_ANADIG_PLL_SYS_HALF_CP 0x00000200 | |
| 611 | #define BM_ANADIG_PLL_SYS_DOUBLE_LF 0x00000100 | |
| 612 | #define BM_ANADIG_PLL_SYS_HALF_LF 0x00000080 | |
| 613 | #define BP_ANADIG_PLL_SYS_DIV_SELECT 0 | |
| 614 | #define BM_ANADIG_PLL_SYS_DIV_SELECT 0x0000007F | |
| 615 | #define BF_ANADIG_PLL_SYS_DIV_SELECT(v) \ | |
| 616 | (((v) << 0) & BM_ANADIG_PLL_SYS_DIV_SELECT) | |
| 617 | ||
| 618 | #define BM_ANADIG_USB1_PLL_480_CTRL_LOCK 0x80000000 | |
| 619 | #define BP_ANADIG_USB1_PLL_480_CTRL_RSVD1 17 | |
| 620 | #define BM_ANADIG_USB1_PLL_480_CTRL_RSVD1 0x7FFE0000 | |
| 621 | #define BF_ANADIG_USB1_PLL_480_CTRL_RSVD1(v) \ | |
| 622 | (((v) << 17) & BM_ANADIG_USB1_PLL_480_CTRL_RSVD1) | |
| 623 | #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS 0x00010000 | |
| 624 | #define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 14 | |
| 625 | #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000 | |
| 626 | #define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v) \ | |
| 627 | (((v) << 14) & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC) | |
| 628 | #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0 | |
| 629 | #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1 | |
| 630 | #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2 | |
| 631 | #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3 | |
| 632 | #define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE 0x00002000 | |
| 633 | #define BM_ANADIG_USB1_PLL_480_CTRL_POWER 0x00001000 | |
| 634 | #define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF 0x00000800 | |
| 635 | #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP 0x00000400 | |
| 636 | #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP 0x00000200 | |
| 637 | #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF 0x00000100 | |
| 638 | #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF 0x00000080 | |
| 639 | #define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS 0x00000040 | |
| 640 | #define BM_ANADIG_USB1_PLL_480_CTRL_RSVD0 0x00000020 | |
| 641 | #define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0 2 | |
| 642 | #define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 0x0000001C | |
| 643 | #define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v) \ | |
| 644 | (((v) << 2) & BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0) | |
| 645 | #define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0 | |
| 646 | #define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0x00000003 | |
| 647 | #define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) \ | |
| 648 | (((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT) | |
| 649 | ||
| 650 | #define BM_ANADIG_PLL_528_LOCK 0x80000000 | |
| 651 | #define BP_ANADIG_PLL_528_RSVD1 19 | |
| 652 | #define BM_ANADIG_PLL_528_RSVD1 0x7FF80000 | |
| 653 | #define BF_ANADIG_PLL_528_RSVD1(v) \ | |
| 654 | (((v) << 19) & BM_ANADIG_PLL_528_RSVD1) | |
| 655 | #define BM_ANADIG_PLL_528_PFD_OFFSET_EN 0x00040000 | |
| 656 | #define BM_ANADIG_PLL_528_DITHER_ENABLE 0x00020000 | |
| 657 | #define BM_ANADIG_PLL_528_BYPASS 0x00010000 | |
| 658 | #define BP_ANADIG_PLL_528_BYPASS_CLK_SRC 14 | |
| 659 | #define BM_ANADIG_PLL_528_BYPASS_CLK_SRC 0x0000C000 | |
| 660 | #define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v) \ | |
| 661 | (((v) << 14) & BM_ANADIG_PLL_528_BYPASS_CLK_SRC) | |
| 662 | #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M 0x0 | |
| 663 | #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1 | |
| 664 | #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2 | |
| 665 | #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR 0x3 | |
| 666 | #define BM_ANADIG_PLL_528_ENABLE 0x00002000 | |
| 667 | #define BM_ANADIG_PLL_528_POWERDOWN 0x00001000 | |
| 668 | #define BM_ANADIG_PLL_528_HOLD_RING_OFF 0x00000800 | |
| 669 | #define BM_ANADIG_PLL_528_DOUBLE_CP 0x00000400 | |
| 670 | #define BM_ANADIG_PLL_528_HALF_CP 0x00000200 | |
| 671 | #define BM_ANADIG_PLL_528_DOUBLE_LF 0x00000100 | |
| 672 | #define BM_ANADIG_PLL_528_HALF_LF 0x00000080 | |
| 673 | #define BP_ANADIG_PLL_528_RSVD0 1 | |
| 674 | #define BM_ANADIG_PLL_528_RSVD0 0x0000007E | |
| 675 | #define BF_ANADIG_PLL_528_RSVD0(v) \ | |
| 676 | (((v) << 1) & BM_ANADIG_PLL_528_RSVD0) | |
| 677 | #define BM_ANADIG_PLL_528_DIV_SELECT 0x00000001 | |
| 678 | ||
| 679 | #define BP_ANADIG_PLL_528_SS_STOP 16 | |
| 680 | #define BM_ANADIG_PLL_528_SS_STOP 0xFFFF0000 | |
| 681 | #define BF_ANADIG_PLL_528_SS_STOP(v) \ | |
| 682 | (((v) << 16) & BM_ANADIG_PLL_528_SS_STOP) | |
| 683 | #define BM_ANADIG_PLL_528_SS_ENABLE 0x00008000 | |
| 684 | #define BP_ANADIG_PLL_528_SS_STEP 0 | |
| 685 | #define BM_ANADIG_PLL_528_SS_STEP 0x00007FFF | |
| 686 | #define BF_ANADIG_PLL_528_SS_STEP(v) \ | |
| 687 | (((v) << 0) & BM_ANADIG_PLL_528_SS_STEP) | |
| 688 | ||
| 689 | #define BP_ANADIG_PLL_528_NUM_RSVD0 30 | |
| 690 | #define BM_ANADIG_PLL_528_NUM_RSVD0 0xC0000000 | |
| 691 | #define BF_ANADIG_PLL_528_NUM_RSVD0(v) \ | |
| 692 | (((v) << 30) & BM_ANADIG_PLL_528_NUM_RSVD0) | |
| 693 | #define BP_ANADIG_PLL_528_NUM_A 0 | |
| 694 | #define BM_ANADIG_PLL_528_NUM_A 0x3FFFFFFF | |
| 695 | #define BF_ANADIG_PLL_528_NUM_A(v) \ | |
| 696 | (((v) << 0) & BM_ANADIG_PLL_528_NUM_A) | |
| 697 | ||
| 698 | #define BP_ANADIG_PLL_528_DENOM_RSVD0 30 | |
| 699 | #define BM_ANADIG_PLL_528_DENOM_RSVD0 0xC0000000 | |
| 700 | #define BF_ANADIG_PLL_528_DENOM_RSVD0(v) \ | |
| 701 | (((v) << 30) & BM_ANADIG_PLL_528_DENOM_RSVD0) | |
| 702 | #define BP_ANADIG_PLL_528_DENOM_B 0 | |
| 703 | #define BM_ANADIG_PLL_528_DENOM_B 0x3FFFFFFF | |
| 704 | #define BF_ANADIG_PLL_528_DENOM_B(v) \ | |
| 705 | (((v) << 0) & BM_ANADIG_PLL_528_DENOM_B) | |
| 706 | ||
| 707 | #define BM_ANADIG_PLL_AUDIO_LOCK 0x80000000 | |
| 708 | #define BP_ANADIG_PLL_AUDIO_RSVD0 22 | |
| 709 | #define BM_ANADIG_PLL_AUDIO_RSVD0 0x7FC00000 | |
| 710 | #define BF_ANADIG_PLL_AUDIO_RSVD0(v) \ | |
| 711 | (((v) << 22) & BM_ANADIG_PLL_AUDIO_RSVD0) | |
| 712 | #define BM_ANADIG_PLL_AUDIO_SSC_EN 0x00200000 | |
| 713 | #define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19 | |
| 714 | #define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 0x00180000 | |
| 715 | #define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \ | |
| 716 | (((v) << 19) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) | |
| 717 | #define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN 0x00040000 | |
| 718 | #define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE 0x00020000 | |
| 719 | #define BM_ANADIG_PLL_AUDIO_BYPASS 0x00010000 | |
| 720 | #define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14 | |
| 721 | #define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 0x0000C000 | |
| 722 | #define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \ | |
| 723 | (((v) << 14) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) | |
| 724 | #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0 | |
| 725 | #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1 | |
| 726 | #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2 | |
| 727 | #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3 | |
| 728 | #define BM_ANADIG_PLL_AUDIO_ENABLE 0x00002000 | |
| 729 | #define BM_ANADIG_PLL_AUDIO_POWERDOWN 0x00001000 | |
| 730 | #define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF 0x00000800 | |
| 731 | #define BM_ANADIG_PLL_AUDIO_DOUBLE_CP 0x00000400 | |
| 732 | #define BM_ANADIG_PLL_AUDIO_HALF_CP 0x00000200 | |
| 733 | #define BM_ANADIG_PLL_AUDIO_DOUBLE_LF 0x00000100 | |
| 734 | #define BM_ANADIG_PLL_AUDIO_HALF_LF 0x00000080 | |
| 735 | #define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0 | |
| 736 | #define BM_ANADIG_PLL_AUDIO_DIV_SELECT 0x0000007F | |
| 737 | #define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \ | |
| 738 | (((v) << 0) & BM_ANADIG_PLL_AUDIO_DIV_SELECT) | |
| 739 | ||
| 740 | #define BP_ANADIG_PLL_AUDIO_NUM_RSVD0 30 | |
| 741 | #define BM_ANADIG_PLL_AUDIO_NUM_RSVD0 0xC0000000 | |
| 742 | #define BF_ANADIG_PLL_AUDIO_NUM_RSVD0(v) \ | |
| 743 | (((v) << 30) & BM_ANADIG_PLL_AUDIO_NUM_RSVD0) | |
| 744 | #define BP_ANADIG_PLL_AUDIO_NUM_A 0 | |
| 745 | #define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF | |
| 746 | #define BF_ANADIG_PLL_AUDIO_NUM_A(v) \ | |
| 747 | (((v) << 0) & BM_ANADIG_PLL_AUDIO_NUM_A) | |
| 748 | ||
| 749 | #define BP_ANADIG_PLL_AUDIO_DENOM_RSVD0 30 | |
| 750 | #define BM_ANADIG_PLL_AUDIO_DENOM_RSVD0 0xC0000000 | |
| 751 | #define BF_ANADIG_PLL_AUDIO_DENOM_RSVD0(v) \ | |
| 752 | (((v) << 30) & BM_ANADIG_PLL_AUDIO_DENOM_RSVD0) | |
| 753 | #define BP_ANADIG_PLL_AUDIO_DENOM_B 0 | |
| 754 | #define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF | |
| 755 | #define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \ | |
| 756 | (((v) << 0) & BM_ANADIG_PLL_AUDIO_DENOM_B) | |
| 757 | ||
| 758 | #define BM_ANADIG_PLL_VIDEO_LOCK 0x80000000 | |
| 759 | #define BP_ANADIG_PLL_VIDEO_RSVD0 22 | |
| 760 | #define BM_ANADIG_PLL_VIDEO_RSVD0 0x7FC00000 | |
| 761 | #define BF_ANADIG_PLL_VIDEO_RSVD0(v) \ | |
| 762 | (((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0) | |
| 763 | #define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000 | |
| 764 | #define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 19 | |
| 765 | #define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 0x00180000 | |
| 766 | #define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v) \ | |
| 767 | (((v) << 19) & BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT) | |
| 768 | #define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000 | |
| 769 | #define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000 | |
| 770 | #define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000 | |
| 771 | #define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14 | |
| 772 | #define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 0x0000C000 | |
| 773 | #define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \ | |
| 774 | (((v) << 14) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) | |
| 775 | #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0 | |
| 776 | #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1 | |
| 777 | #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2 | |
| 778 | #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3 | |
| 779 | #define BM_ANADIG_PLL_VIDEO_ENABLE 0x00002000 | |
| 780 | #define BM_ANADIG_PLL_VIDEO_POWERDOWN 0x00001000 | |
| 781 | #define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF 0x00000800 | |
| 782 | #define BM_ANADIG_PLL_VIDEO_DOUBLE_CP 0x00000400 | |
| 783 | #define BM_ANADIG_PLL_VIDEO_HALF_CP 0x00000200 | |
| 784 | #define BM_ANADIG_PLL_VIDEO_DOUBLE_LF 0x00000100 | |
| 785 | #define BM_ANADIG_PLL_VIDEO_HALF_LF 0x00000080 | |
| 786 | #define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0 | |
| 787 | #define BM_ANADIG_PLL_VIDEO_DIV_SELECT 0x0000007F | |
| 788 | #define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \ | |
| 789 | (((v) << 0) & BM_ANADIG_PLL_VIDEO_DIV_SELECT) | |
| 790 | ||
| 791 | #define BP_ANADIG_PLL_VIDEO_NUM_RSVD0 30 | |
| 792 | #define BM_ANADIG_PLL_VIDEO_NUM_RSVD0 0xC0000000 | |
| 793 | #define BF_ANADIG_PLL_VIDEO_NUM_RSVD0(v) \ | |
| 794 | (((v) << 30) & BM_ANADIG_PLL_VIDEO_NUM_RSVD0) | |
| 795 | #define BP_ANADIG_PLL_VIDEO_NUM_A 0 | |
| 796 | #define BM_ANADIG_PLL_VIDEO_NUM_A 0x3FFFFFFF | |
| 797 | #define BF_ANADIG_PLL_VIDEO_NUM_A(v) \ | |
| 798 | (((v) << 0) & BM_ANADIG_PLL_VIDEO_NUM_A) | |
| 799 | ||
| 800 | #define BP_ANADIG_PLL_VIDEO_DENOM_RSVD0 30 | |
| 801 | #define BM_ANADIG_PLL_VIDEO_DENOM_RSVD0 0xC0000000 | |
| 802 | #define BF_ANADIG_PLL_VIDEO_DENOM_RSVD0(v) \ | |
| 803 | (((v) << 30) & BM_ANADIG_PLL_VIDEO_DENOM_RSVD0) | |
| 804 | #define BP_ANADIG_PLL_VIDEO_DENOM_B 0 | |
| 805 | #define BM_ANADIG_PLL_VIDEO_DENOM_B 0x3FFFFFFF | |
| 806 | #define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \ | |
| 807 | (((v) << 0) & BM_ANADIG_PLL_VIDEO_DENOM_B) | |
| 808 | ||
| 809 | #define BM_ANADIG_PLL_ENET_LOCK 0x80000000 | |
| 810 | #define BP_ANADIG_PLL_ENET_RSVD1 21 | |
| 811 | #define BM_ANADIG_PLL_ENET_RSVD1 0x7FE00000 | |
| 812 | #define BF_ANADIG_PLL_ENET_RSVD1(v) \ | |
| 813 | (((v) << 21) & BM_ANADIG_PLL_ENET_RSVD1) | |
| 814 | #define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000 | |
| 815 | #define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000 | |
| 816 | #define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000 | |
| 817 | #define BM_ANADIG_PLL_ENET_DITHER_ENABLE 0x00020000 | |
| 818 | #define BM_ANADIG_PLL_ENET_BYPASS 0x00010000 | |
| 819 | #define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14 | |
| 820 | #define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC 0x0000C000 | |
| 821 | #define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \ | |
| 822 | (((v) << 14) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC) | |
| 823 | #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0 | |
| 824 | #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1 | |
| 825 | #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2 | |
| 826 | #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3 | |
| 827 | #define BM_ANADIG_PLL_ENET_ENABLE 0x00002000 | |
| 828 | #define BM_ANADIG_PLL_ENET_POWERDOWN 0x00001000 | |
| 829 | #define BM_ANADIG_PLL_ENET_HOLD_RING_OFF 0x00000800 | |
| 830 | #define BM_ANADIG_PLL_ENET_DOUBLE_CP 0x00000400 | |
| 831 | #define BM_ANADIG_PLL_ENET_HALF_CP 0x00000200 | |
| 832 | #define BM_ANADIG_PLL_ENET_DOUBLE_LF 0x00000100 | |
| 833 | #define BM_ANADIG_PLL_ENET_HALF_LF 0x00000080 | |
| 834 | #define BP_ANADIG_PLL_ENET_RSVD0 2 | |
| 835 | #define BM_ANADIG_PLL_ENET_RSVD0 0x0000007C | |
| 836 | #define BF_ANADIG_PLL_ENET_RSVD0(v) \ | |
| 837 | (((v) << 2) & BM_ANADIG_PLL_ENET_RSVD0) | |
| 838 | #define BP_ANADIG_PLL_ENET_DIV_SELECT 0 | |
| 839 | #define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003 | |
| 840 | #define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \ | |
| 841 | (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT) | |
| 842 | ||
| 843 | #define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000 | |
| 844 | #define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000 | |
| 845 | #define BP_ANADIG_PFD_480_PFD3_FRAC 24 | |
| 846 | #define BM_ANADIG_PFD_480_PFD3_FRAC 0x3F000000 | |
| 847 | #define BF_ANADIG_PFD_480_PFD3_FRAC(v) \ | |
| 848 | (((v) << 24) & BM_ANADIG_PFD_480_PFD3_FRAC) | |
| 849 | #define BM_ANADIG_PFD_480_PFD2_CLKGATE 0x00800000 | |
| 850 | #define BM_ANADIG_PFD_480_PFD2_STABLE 0x00400000 | |
| 851 | #define BP_ANADIG_PFD_480_PFD2_FRAC 16 | |
| 852 | #define BM_ANADIG_PFD_480_PFD2_FRAC 0x003F0000 | |
| 853 | #define BF_ANADIG_PFD_480_PFD2_FRAC(v) \ | |
| 854 | (((v) << 16) & BM_ANADIG_PFD_480_PFD2_FRAC) | |
| 855 | #define BM_ANADIG_PFD_480_PFD1_CLKGATE 0x00008000 | |
| 856 | #define BM_ANADIG_PFD_480_PFD1_STABLE 0x00004000 | |
| 857 | #define BP_ANADIG_PFD_480_PFD1_FRAC 8 | |
| 858 | #define BM_ANADIG_PFD_480_PFD1_FRAC 0x00003F00 | |
| 859 | #define BF_ANADIG_PFD_480_PFD1_FRAC(v) \ | |
| 860 | (((v) << 8) & BM_ANADIG_PFD_480_PFD1_FRAC) | |
| 861 | #define BM_ANADIG_PFD_480_PFD0_CLKGATE 0x00000080 | |
| 862 | #define BM_ANADIG_PFD_480_PFD0_STABLE 0x00000040 | |
| 863 | #define BP_ANADIG_PFD_480_PFD0_FRAC 0 | |
| 864 | #define BM_ANADIG_PFD_480_PFD0_FRAC 0x0000003F | |
| 865 | #define BF_ANADIG_PFD_480_PFD0_FRAC(v) \ | |
| 866 | (((v) << 0) & BM_ANADIG_PFD_480_PFD0_FRAC) | |
| 867 | ||
| 868 | #define BM_ANADIG_PFD_528_PFD3_CLKGATE 0x80000000 | |
| 869 | #define BM_ANADIG_PFD_528_PFD3_STABLE 0x40000000 | |
| 870 | #define BP_ANADIG_PFD_528_PFD3_FRAC 24 | |
| 871 | #define BM_ANADIG_PFD_528_PFD3_FRAC 0x3F000000 | |
| 872 | #define BF_ANADIG_PFD_528_PFD3_FRAC(v) \ | |
| 873 | (((v) << 24) & BM_ANADIG_PFD_528_PFD3_FRAC) | |
| 874 | #define BM_ANADIG_PFD_528_PFD2_CLKGATE 0x00800000 | |
| 875 | #define BM_ANADIG_PFD_528_PFD2_STABLE 0x00400000 | |
| 876 | #define BP_ANADIG_PFD_528_PFD2_FRAC 16 | |
| 877 | #define BM_ANADIG_PFD_528_PFD2_FRAC 0x003F0000 | |
| 878 | #define BF_ANADIG_PFD_528_PFD2_FRAC(v) \ | |
| 879 | (((v) << 16) & BM_ANADIG_PFD_528_PFD2_FRAC) | |
| 880 | #define BM_ANADIG_PFD_528_PFD1_CLKGATE 0x00008000 | |
| 881 | #define BM_ANADIG_PFD_528_PFD1_STABLE 0x00004000 | |
| 882 | #define BP_ANADIG_PFD_528_PFD1_FRAC 8 | |
| 883 | #define BM_ANADIG_PFD_528_PFD1_FRAC 0x00003F00 | |
| 884 | #define BF_ANADIG_PFD_528_PFD1_FRAC(v) \ | |
| 885 | (((v) << 8) & BM_ANADIG_PFD_528_PFD1_FRAC) | |
| 886 | #define BM_ANADIG_PFD_528_PFD0_CLKGATE 0x00000080 | |
| 887 | #define BM_ANADIG_PFD_528_PFD0_STABLE 0x00000040 | |
| 888 | #define BP_ANADIG_PFD_528_PFD0_FRAC 0 | |
| 889 | #define BM_ANADIG_PFD_528_PFD0_FRAC 0x0000003F | |
| 890 | #define BF_ANADIG_PFD_528_PFD0_FRAC(v) \ | |
| 891 | (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC) | |
| 892 | ||
| 893 | #define PLL2_PFD0_FREQ 352000000 | |
| 894 | #define PLL2_PFD1_FREQ 594000000 | |
| 895 | #define PLL2_PFD2_FREQ 400000000 | |
| 896 | #define PLL2_PFD2_DIV_FREQ 200000000 | |
| 897 | #define PLL3_PFD0_FREQ 720000000 | |
| 898 | #define PLL3_PFD1_FREQ 540000000 | |
| 899 | #define PLL3_PFD2_FREQ 508200000 | |
| 900 | #define PLL3_PFD3_FREQ 454700000 | |
| 901 | #define PLL3_80M 80000000 | |
| 902 | #define PLL3_60M 60000000 | |
| 903 | ||
| 904 | #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */ |