[people/ms/u-boot.git] / arch / arm / include / asm / arch-mx6 / imx-regs.h

/*
 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.

 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.

 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
 */

#ifndef __ASM_ARCH_MX6_IMX_REGS_H__
#define __ASM_ARCH_MX6_IMX_REGS_H__

#define ARCH_MXC

#define CONFIG_SYS_CACHELINE_SIZE	32

#define ROMCP_ARB_BASE_ADDR             0x00000000
#define ROMCP_ARB_END_ADDR              0x000FFFFF
#define CAAM_ARB_BASE_ADDR              0x00100000
#define CAAM_ARB_END_ADDR               0x00103FFF
#define APBH_DMA_ARB_BASE_ADDR          0x00110000
#define APBH_DMA_ARB_END_ADDR           0x00117FFF
#define HDMI_ARB_BASE_ADDR              0x00120000
#define HDMI_ARB_END_ADDR               0x00128FFF
#define GPU_3D_ARB_BASE_ADDR            0x00130000
#define GPU_3D_ARB_END_ADDR             0x00133FFF
#define GPU_2D_ARB_BASE_ADDR            0x00134000
#define GPU_2D_ARB_END_ADDR             0x00137FFF
#define DTCP_ARB_BASE_ADDR              0x00138000
#define DTCP_ARB_END_ADDR               0x0013BFFF

/* GPV - PL301 configuration ports */
#define GPV2_BASE_ADDR			0x00200000
#define GPV3_BASE_ADDR			0x00300000
#define GPV4_BASE_ADDR			0x00800000
#define IRAM_BASE_ADDR			0x00900000
#define SCU_BASE_ADDR                   0x00A00000
#define IC_INTERFACES_BASE_ADDR         0x00A00100
#define GLOBAL_TIMER_BASE_ADDR          0x00A00200
#define PRIVATE_TIMERS_WD_BASE_ADDR     0x00A00600
#define IC_DISTRIBUTOR_BASE_ADDR        0x00A01000
#define GPV0_BASE_ADDR                  0x00B00000
#define GPV1_BASE_ADDR                  0x00C00000
#define PCIE_ARB_BASE_ADDR              0x01000000
#define PCIE_ARB_END_ADDR               0x01FFFFFF

#define AIPS1_ARB_BASE_ADDR             0x02000000
#define AIPS1_ARB_END_ADDR              0x020FFFFF
#define AIPS2_ARB_BASE_ADDR             0x02100000
#define AIPS2_ARB_END_ADDR              0x021FFFFF
#define SATA_ARB_BASE_ADDR              0x02200000
#define SATA_ARB_END_ADDR               0x02203FFF
#define OPENVG_ARB_BASE_ADDR            0x02204000
#define OPENVG_ARB_END_ADDR             0x02207FFF
#define HSI_ARB_BASE_ADDR               0x02208000
#define HSI_ARB_END_ADDR                0x0220BFFF
#define IPU1_ARB_BASE_ADDR              0x02400000
#define IPU1_ARB_END_ADDR               0x027FFFFF
#define IPU2_ARB_BASE_ADDR              0x02800000
#define IPU2_ARB_END_ADDR               0x02BFFFFF
#define WEIM_ARB_BASE_ADDR              0x08000000
#define WEIM_ARB_END_ADDR               0x0FFFFFFF

#define MMDC0_ARB_BASE_ADDR             0x10000000
#define MMDC0_ARB_END_ADDR              0x7FFFFFFF
#define MMDC1_ARB_BASE_ADDR             0x80000000
#define MMDC1_ARB_END_ADDR              0xFFFFFFFF

#define IPU_SOC_BASE_ADDR		IPU1_ARB_BASE_ADDR
#define IPU_SOC_OFFSET			0x00200000

/* Defines for Blocks connected via AIPS (SkyBlue) */
#define ATZ1_BASE_ADDR              AIPS1_ARB_BASE_ADDR
#define ATZ2_BASE_ADDR              AIPS2_ARB_BASE_ADDR
#define AIPS1_BASE_ADDR             AIPS1_ON_BASE_ADDR
#define AIPS2_BASE_ADDR             AIPS2_ON_BASE_ADDR

#define SPDIF_BASE_ADDR             (ATZ1_BASE_ADDR + 0x04000)
#define ECSPI1_BASE_ADDR            (ATZ1_BASE_ADDR + 0x08000)
#define ECSPI2_BASE_ADDR            (ATZ1_BASE_ADDR + 0x0C000)
#define ECSPI3_BASE_ADDR            (ATZ1_BASE_ADDR + 0x10000)
#define ECSPI4_BASE_ADDR            (ATZ1_BASE_ADDR + 0x14000)
#define ECSPI5_BASE_ADDR            (ATZ1_BASE_ADDR + 0x18000)
#define UART1_BASE                  (ATZ1_BASE_ADDR + 0x20000)
#define ESAI1_BASE_ADDR             (ATZ1_BASE_ADDR + 0x24000)
#define SSI1_BASE_ADDR              (ATZ1_BASE_ADDR + 0x28000)
#define SSI2_BASE_ADDR              (ATZ1_BASE_ADDR + 0x2C000)
#define SSI3_BASE_ADDR              (ATZ1_BASE_ADDR + 0x30000)
#define ASRC_BASE_ADDR              (ATZ1_BASE_ADDR + 0x34000)
#define SPBA_BASE_ADDR              (ATZ1_BASE_ADDR + 0x3C000)
#define VPU_BASE_ADDR               (ATZ1_BASE_ADDR + 0x40000)
#define AIPS1_ON_BASE_ADDR          (ATZ1_BASE_ADDR + 0x7C000)

#define AIPS1_OFF_BASE_ADDR         (ATZ1_BASE_ADDR + 0x80000)
#define PWM1_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x0000)
#define PWM2_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x4000)
#define PWM3_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x8000)
#define PWM4_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0xC000)
#define CAN1_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x10000)
#define CAN2_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x14000)
#define GPT1_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x18000)
#define GPIO1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x1C000)
#define GPIO2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x20000)
#define GPIO3_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x24000)
#define GPIO4_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x28000)
#define GPIO5_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x2C000)
#define GPIO6_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x30000)
#define GPIO7_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x34000)
#define KPP_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x38000)
#define WDOG1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x3C000)
#define WDOG2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x40000)
#define ANATOP_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x48000)
#define USB_PHY0_BASE_ADDR          (AIPS1_OFF_BASE_ADDR + 0x49000)
#define USB_PHY1_BASE_ADDR          (AIPS1_OFF_BASE_ADDR + 0x4a000)
#define CCM_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x44000)
#define SNVS_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x4C000)
#define EPIT1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x50000)
#define EPIT2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x54000)
#define SRC_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x58000)
#define GPC_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x5C000)
#define IOMUXC_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x60000)
#define DCIC1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x64000)
#define DCIC2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x68000)
#define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)

#define AIPS2_ON_BASE_ADDR          (ATZ2_BASE_ADDR + 0x7C000)
#define AIPS2_OFF_BASE_ADDR         (ATZ2_BASE_ADDR + 0x80000)
#define CAAM_BASE_ADDR              (ATZ2_BASE_ADDR)
#define ARM_BASE_ADDR		    (ATZ2_BASE_ADDR + 0x40000)
#define USBOH3_PL301_BASE_ADDR      (AIPS2_OFF_BASE_ADDR + 0x0000)
#define USBOH3_USB_BASE_ADDR        (AIPS2_OFF_BASE_ADDR + 0x4000)
#define ENET_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x8000)
#define MLB_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0xC000)
#define USDHC1_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x10000)
#define USDHC2_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x14000)
#define USDHC3_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x18000)
#define USDHC4_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x1C000)
#define I2C1_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x20000)
#define I2C2_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x24000)
#define I2C3_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x28000)
#define ROMCP_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x2C000)
#define MMDC_P0_BASE_ADDR           (AIPS2_OFF_BASE_ADDR + 0x30000)
#define MMDC_P1_BASE_ADDR           (AIPS2_OFF_BASE_ADDR + 0x34000)
#define WEIM_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x38000)
#define OCOTP_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x3C000)
#define CSU_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x40000)
#define IP2APB_PERFMON1_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x44000)
#define IP2APB_PERFMON2_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x48000)
#define IP2APB_PERFMON3_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x4C000)
#define IP2APB_TZASC1_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x50000)
#define IP2APB_TZASC2_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x54000)
#define AUDMUX_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x58000)
#define MIPI_CSI2_BASE_ADDR         (AIPS2_OFF_BASE_ADDR + 0x5C000)
#define MIPI_DSI_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0x60000)
#define VDOA_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x64000)
#define UART2_BASE                  (AIPS2_OFF_BASE_ADDR + 0x68000)
#define UART3_BASE                  (AIPS2_OFF_BASE_ADDR + 0x6C000)
#define UART4_BASE                  (AIPS2_OFF_BASE_ADDR + 0x70000)
#define UART5_BASE                  (AIPS2_OFF_BASE_ADDR + 0x74000)
#define IP2APB_USBPHY1_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x78000)
#define IP2APB_USBPHY2_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x7C000)

#define CHIP_REV_1_0                 0x10
#define IRAM_SIZE                    0x00040000
#define IMX_IIM_BASE                 OCOTP_BASE_ADDR
#define FEC_QUIRK_ENET_MAC

#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>

extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);

/* System Reset Controller (SRC) */
struct src {
	u32	scr;
	u32	sbmr1;
	u32	srsr;
	u32	reserved1[2];
	u32	sisr;
	u32	simr;
	u32     sbmr2;
	u32     gpr1;
	u32     gpr2;
	u32     gpr3;
	u32     gpr4;
	u32     gpr5;
	u32     gpr6;
	u32     gpr7;
	u32     gpr8;
	u32     gpr9;
	u32     gpr10;
};

/* GPR3 bitfields */
#define IOMUXC_GPR3_GPU_DBG_OFFSET		29
#define IOMUXC_GPR3_GPU_DBG_MASK		(3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
#define IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET	28
#define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK	(1<<IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET)
#define IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET	27
#define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK	(1<<IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET)
#define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET	26
#define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK	(1<<IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET)
#define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET	25
#define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK	(1<<IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET)
#define IOMUXC_GPR3_OCRAM_CTL_OFFSET		21
#define IOMUXC_GPR3_OCRAM_CTL_MASK		(0xf<<IOMUXC_GPR3_OCRAM_CTL_OFFSET)
#define IOMUXC_GPR3_OCRAM_STATUS_OFFSET		17
#define IOMUXC_GPR3_OCRAM_STATUS_MASK		(0xf<<IOMUXC_GPR3_OCRAM_STATUS_OFFSET)
#define IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET	16
#define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK	(1<<IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET)
#define IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET	15
#define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK	(1<<IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET)
#define IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET	14
#define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK	(1<<IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET)
#define IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET	13
#define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK	(1<<IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET)
#define IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET	12
#define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK	(1<<IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET)
#define IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET	11
#define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK	(1<<IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET)
#define IOMUXC_GPR3_IPU_DIAG_OFFSET		10
#define IOMUXC_GPR3_IPU_DIAG_MASK		(1<<IOMUXC_GPR3_IPU_DIAG_OFFSET)

#define IOMUXC_GPR3_MUX_SRC_IPU1_DI0	0
#define IOMUXC_GPR3_MUX_SRC_IPU1_DI1	1
#define IOMUXC_GPR3_MUX_SRC_IPU2_DI0	2
#define IOMUXC_GPR3_MUX_SRC_IPU2_DI1	3

#define IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET	8
#define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK		(3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET)

#define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET	6
#define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK		(3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)

#define IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET		4
#define IOMUXC_GPR3_MIPI_MUX_CTL_MASK		(3<<IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET)

#define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET		2
#define IOMUXC_GPR3_HDMI_MUX_CTL_MASK		(3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET)


/* ECSPI registers */
struct cspi_regs {
	u32 rxdata;
	u32 txdata;
	u32 ctrl;
	u32 cfg;
	u32 intr;
	u32 dma;
	u32 stat;
	u32 period;
};

/*
 * CSPI register definitions
 */
#define MXC_ECSPI
#define MXC_CSPICTRL_EN		(1 << 0)
#define MXC_CSPICTRL_MODE	(1 << 1)
#define MXC_CSPICTRL_XCH	(1 << 2)
#define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 12)
#define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0xfff) << 20)
#define MXC_CSPICTRL_PREDIV(x)	(((x) & 0xF) << 12)
#define MXC_CSPICTRL_POSTDIV(x)	(((x) & 0xF) << 8)
#define MXC_CSPICTRL_SELCHAN(x)	(((x) & 0x3) << 18)
#define MXC_CSPICTRL_MAXBITS	0xfff
#define MXC_CSPICTRL_TC		(1 << 7)
#define MXC_CSPICTRL_RXOVF	(1 << 6)
#define MXC_CSPIPERIOD_32KHZ	(1 << 15)
#define MAX_SPI_BYTES	32

/* Bit position inside CTRL register to be associated with SS */
#define MXC_CSPICTRL_CHAN	18

/* Bit position inside CON register to be associated with SS */
#define MXC_CSPICON_POL		4
#define MXC_CSPICON_PHA		0
#define MXC_CSPICON_SSPOL	12
#define MXC_SPI_BASE_ADDRESSES \
	ECSPI1_BASE_ADDR, \
	ECSPI2_BASE_ADDR, \
	ECSPI3_BASE_ADDR, \
	ECSPI4_BASE_ADDR, \
	ECSPI5_BASE_ADDR

struct iim_regs {
	u32	ctrl;
	u32	ctrl_set;
	u32     ctrl_clr;
	u32	ctrl_tog;
	u32	timing;
	u32     rsvd0[3];
	u32     data;
	u32     rsvd1[3];
	u32     read_ctrl;
	u32     rsvd2[3];
	u32     fuse_data;
	u32     rsvd3[3];
	u32     sticky;
	u32     rsvd4[3];
	u32     scs;
	u32     scs_set;
	u32     scs_clr;
	u32     scs_tog;
	u32     crc_addr;
	u32     rsvd5[3];
	u32     crc_value;
	u32     rsvd6[3];
	u32     version;
	u32     rsvd7[0xdb];

	struct fuse_bank {
		u32	fuse_regs[0x20];
	} bank[15];
};

struct fuse_bank4_regs {
	u32	sjc_resp_low;
	u32     rsvd0[3];
	u32     sjc_resp_high;
	u32     rsvd1[3];
	u32	mac_addr_low;
	u32     rsvd2[3];
	u32     mac_addr_high;
	u32	rsvd3[0x13];
};

struct aipstz_regs {
	u32	mprot0;
	u32	mprot1;
	u32	rsvd[0xe];
	u32	opacr0;
	u32	opacr1;
	u32	opacr2;
	u32	opacr3;
	u32	opacr4;
};

struct anatop_regs {
	u32	pll_sys;		/* 0x000 */
	u32	pll_sys_set;		/* 0x004 */
	u32	pll_sys_clr;		/* 0x008 */
	u32	pll_sys_tog;		/* 0x00c */
	u32	usb1_pll_480_ctrl;	/* 0x010 */
	u32	usb1_pll_480_ctrl_set;	/* 0x014 */
	u32	usb1_pll_480_ctrl_clr;	/* 0x018 */
	u32	usb1_pll_480_ctrl_tog;	/* 0x01c */
	u32	usb2_pll_480_ctrl;	/* 0x020 */
	u32	usb2_pll_480_ctrl_set;	/* 0x024 */
	u32	usb2_pll_480_ctrl_clr;	/* 0x028 */
	u32	usb2_pll_480_ctrl_tog;	/* 0x02c */
	u32	pll_528;		/* 0x030 */
	u32	pll_528_set;		/* 0x034 */
	u32	pll_528_clr;		/* 0x038 */
	u32	pll_528_tog;		/* 0x03c */
	u32	pll_528_ss;		/* 0x040 */
	u32	rsvd0[3];
	u32	pll_528_num;		/* 0x050 */
	u32	rsvd1[3];
	u32	pll_528_denom;		/* 0x060 */
	u32	rsvd2[3];
	u32	pll_audio;		/* 0x070 */
	u32	pll_audio_set;		/* 0x074 */
	u32	pll_audio_clr;		/* 0x078 */
	u32	pll_audio_tog;		/* 0x07c */
	u32	pll_audio_num;		/* 0x080 */
	u32	rsvd3[3];
	u32	pll_audio_denom;	/* 0x090 */
	u32	rsvd4[3];
	u32	pll_video;		/* 0x0a0 */
	u32	pll_video_set;		/* 0x0a4 */
	u32	pll_video_clr;		/* 0x0a8 */
	u32	pll_video_tog;		/* 0x0ac */
	u32	pll_video_num;		/* 0x0b0 */
	u32	rsvd5[3];
	u32	pll_video_denom;	/* 0x0c0 */
	u32	rsvd6[3];
	u32	pll_mlb;		/* 0x0d0 */
	u32	pll_mlb_set;		/* 0x0d4 */
	u32	pll_mlb_clr;		/* 0x0d8 */
	u32	pll_mlb_tog;		/* 0x0dc */
	u32	pll_enet;		/* 0x0e0 */
	u32	pll_enet_set;		/* 0x0e4 */
	u32	pll_enet_clr;		/* 0x0e8 */
	u32	pll_enet_tog;		/* 0x0ec */
	u32	pfd_480;		/* 0x0f0 */
	u32	pfd_480_set;		/* 0x0f4 */
	u32	pfd_480_clr;		/* 0x0f8 */
	u32	pfd_480_tog;		/* 0x0fc */
	u32	pfd_528;		/* 0x100 */
	u32	pfd_528_set;		/* 0x104 */
	u32	pfd_528_clr;		/* 0x108 */
	u32	pfd_528_tog;		/* 0x10c */
	u32	reg_1p1;		/* 0x110 */
	u32	reg_1p1_set;		/* 0x114 */
	u32	reg_1p1_clr;		/* 0x118 */
	u32	reg_1p1_tog;		/* 0x11c */
	u32	reg_3p0;		/* 0x120 */
	u32	reg_3p0_set;		/* 0x124 */
	u32	reg_3p0_clr;		/* 0x128 */
	u32	reg_3p0_tog;		/* 0x12c */
	u32	reg_2p5;		/* 0x130 */
	u32	reg_2p5_set;		/* 0x134 */
	u32	reg_2p5_clr;		/* 0x138 */
	u32	reg_2p5_tog;		/* 0x13c */
	u32	reg_core;		/* 0x140 */
	u32	reg_core_set;		/* 0x144 */
	u32	reg_core_clr;		/* 0x148 */
	u32	reg_core_tog;		/* 0x14c */
	u32	ana_misc0;		/* 0x150 */
	u32	ana_misc0_set;		/* 0x154 */
	u32	ana_misc0_clr;		/* 0x158 */
	u32	ana_misc0_tog;		/* 0x15c */
	u32	ana_misc1;		/* 0x160 */
	u32	ana_misc1_set;		/* 0x164 */
	u32	ana_misc1_clr;		/* 0x168 */
	u32	ana_misc1_tog;		/* 0x16c */
	u32	ana_misc2;		/* 0x170 */
	u32	ana_misc2_set;		/* 0x174 */
	u32	ana_misc2_clr;		/* 0x178 */
	u32	ana_misc2_tog;		/* 0x17c */
	u32	tempsense0;		/* 0x180 */
	u32	tempsense0_set;		/* 0x184 */
	u32	tempsense0_clr;		/* 0x188 */
	u32	tempsense0_tog;		/* 0x18c */
	u32	tempsense1;		/* 0x190 */
	u32	tempsense1_set;		/* 0x194 */
	u32	tempsense1_clr;		/* 0x198 */
	u32	tempsense1_tog;		/* 0x19c */
	u32	usb1_vbus_detect;	/* 0x1a0 */
	u32	usb1_vbus_detect_set;	/* 0x1a4 */
	u32	usb1_vbus_detect_clr;	/* 0x1a8 */
	u32	usb1_vbus_detect_tog;	/* 0x1ac */
	u32	usb1_chrg_detect;	/* 0x1b0 */
	u32	usb1_chrg_detect_set;	/* 0x1b4 */
	u32	usb1_chrg_detect_clr;	/* 0x1b8 */
	u32	usb1_chrg_detect_tog;	/* 0x1bc */
	u32	usb1_vbus_det_stat;	/* 0x1c0 */
	u32	usb1_vbus_det_stat_set;	/* 0x1c4 */
	u32	usb1_vbus_det_stat_clr;	/* 0x1c8 */
	u32	usb1_vbus_det_stat_tog;	/* 0x1cc */
	u32	usb1_chrg_det_stat;	/* 0x1d0 */
	u32	usb1_chrg_det_stat_set;	/* 0x1d4 */
	u32	usb1_chrg_det_stat_clr;	/* 0x1d8 */
	u32	usb1_chrg_det_stat_tog;	/* 0x1dc */
	u32	usb1_loopback;		/* 0x1e0 */
	u32	usb1_loopback_set;	/* 0x1e4 */
	u32	usb1_loopback_clr;	/* 0x1e8 */
	u32	usb1_loopback_tog;	/* 0x1ec */
	u32	usb1_misc;		/* 0x1f0 */
	u32	usb1_misc_set;		/* 0x1f4 */
	u32	usb1_misc_clr;		/* 0x1f8 */
	u32	usb1_misc_tog;		/* 0x1fc */
	u32	usb2_vbus_detect;	/* 0x200 */
	u32	usb2_vbus_detect_set;	/* 0x204 */
	u32	usb2_vbus_detect_clr;	/* 0x208 */
	u32	usb2_vbus_detect_tog;	/* 0x20c */
	u32	usb2_chrg_detect;	/* 0x210 */
	u32	usb2_chrg_detect_set;	/* 0x214 */
	u32	usb2_chrg_detect_clr;	/* 0x218 */
	u32	usb2_chrg_detect_tog;	/* 0x21c */
	u32	usb2_vbus_det_stat;	/* 0x220 */
	u32	usb2_vbus_det_stat_set;	/* 0x224 */
	u32	usb2_vbus_det_stat_clr;	/* 0x228 */
	u32	usb2_vbus_det_stat_tog;	/* 0x22c */
	u32	usb2_chrg_det_stat;	/* 0x230 */
	u32	usb2_chrg_det_stat_set;	/* 0x234 */
	u32	usb2_chrg_det_stat_clr;	/* 0x238 */
	u32	usb2_chrg_det_stat_tog;	/* 0x23c */
	u32	usb2_loopback;		/* 0x240 */
	u32	usb2_loopback_set;	/* 0x244 */
	u32	usb2_loopback_clr;	/* 0x248 */
	u32	usb2_loopback_tog;	/* 0x24c */
	u32	usb2_misc;		/* 0x250 */
	u32	usb2_misc_set;		/* 0x254 */
	u32	usb2_misc_clr;		/* 0x258 */
	u32	usb2_misc_tog;		/* 0x25c */
	u32	digprog;		/* 0x260 */
};

#define ANATOP_PFD_480_PFD0_FRAC_SHIFT		0
#define ANATOP_PFD_480_PFD0_FRAC_MASK		(0x3f<<ANATOP_PFD_480_PFD0_FRAC_SHIFT)
#define ANATOP_PFD_480_PFD0_STABLE_SHIFT	6
#define ANATOP_PFD_480_PFD0_STABLE_MASK		(1<<ANATOP_PFD_480_PFD0_STABLE_SHIFT)
#define ANATOP_PFD_480_PFD0_CLKGATE_SHIFT	7
#define ANATOP_PFD_480_PFD0_CLKGATE_MASK	(1<<ANATOP_PFD_480_PFD0_CLKGATE_SHIFT)
#define ANATOP_PFD_480_PFD1_FRAC_SHIFT		8
#define ANATOP_PFD_480_PFD1_FRAC_MASK		(0x3f<<ANATOP_PFD_480_PFD1_FRAC_SHIFT)
#define ANATOP_PFD_480_PFD1_STABLE_SHIFT	14
#define ANATOP_PFD_480_PFD1_STABLE_MASK		(1<<ANATOP_PFD_480_PFD1_STABLE_SHIFT)
#define ANATOP_PFD_480_PFD1_CLKGATE_SHIFT	15
#define ANATOP_PFD_480_PFD1_CLKGATE_MASK	(0x3f<<ANATOP_PFD_480_PFD1_CLKGATE_SHIFT)
#define ANATOP_PFD_480_PFD2_FRAC_SHIFT		16
#define ANATOP_PFD_480_PFD2_FRAC_MASK		(1<<ANATOP_PFD_480_PFD2_FRAC_SHIFT)
#define ANATOP_PFD_480_PFD2_STABLE_SHIFT	22
#define ANATOP_PFD_480_PFD2_STABLE_MASK	(1<<ANATOP_PFD_480_PFD2_STABLE_SHIFT)
#define ANATOP_PFD_480_PFD2_CLKGATE_SHIFT	23
#define ANATOP_PFD_480_PFD2_CLKGATE_MASK	(0x3f<<ANATOP_PFD_480_PFD2_CLKGATE_SHIFT)
#define ANATOP_PFD_480_PFD3_FRAC_SHIFT		24
#define ANATOP_PFD_480_PFD3_FRAC_MASK		(1<<ANATOP_PFD_480_PFD3_FRAC_SHIFT)
#define ANATOP_PFD_480_PFD3_STABLE_SHIFT	30
#define ANATOP_PFD_480_PFD3_STABLE_MASK		(1<<ANATOP_PFD_480_PFD3_STABLE_SHIFT)
#define ANATOP_PFD_480_PFD3_CLKGATE_SHIFT	31

struct iomuxc_base_regs {
	u32     gpr[14];        /* 0x000 */
	u32     obsrv[5];       /* 0x038 */
	u32     swmux_ctl[197]; /* 0x04c */
	u32     swpad_ctl[250]; /* 0x360 */
	u32     swgrp[26];      /* 0x748 */
	u32     daisy[104];     /* 0x7b0..94c */
};

struct src_regs {
	u32	scr;		/* 0x00 */
	u32	sbmr1;		/* 0x04 */
	u32	srsr;		/* 0x08 */
	u32	reserved1;	/* 0x0c */
	u32	reserved2;	/* 0x10 */
	u32	sisr;		/* 0x14 */
	u32	simr;		/* 0x18 */
	u32	sbmr2;		/* 0x1c */
	u32	gpr1;		/* 0x20 */
	u32	gpr2;		/* 0x24 */
	u32	gpr3;		/* 0x28 */
	u32	gpr4;		/* 0x2c */
	u32	gpr5;		/* 0x30 */
	u32	gpr6;		/* 0x34 */
	u32	gpr7;		/* 0x38 */
	u32	gpr8;		/* 0x3c */
	u32	gpr9;		/* 0x40 */
	u32	gpr10;		/* 0x44 */
};

#endif /* __ASSEMBLER__*/
#endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */
Commit	Line	Data
23608e23 JL	1	/*
	2	* Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13
	14	* You should have received a copy of the GNU General Public License along
	15	* with this program; if not, write to the Free Software Foundation, Inc.,
	16	* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
	17	*/
	18
	19	#ifndef __ASM_ARCH_MX6_IMX_REGS_H__
	20	#define __ASM_ARCH_MX6_IMX_REGS_H__
	21
8e99ecd7 BT	22	#define ARCH_MXC
8e99ecd7 BT	23
c415919d EN	24	#define CONFIG_SYS_CACHELINE_SIZE 32
c415919d EN	25
23608e23 JL	26	#define ROMCP_ARB_BASE_ADDR 0x00000000
	27	#define ROMCP_ARB_END_ADDR 0x000FFFFF
	28	#define CAAM_ARB_BASE_ADDR 0x00100000
	29	#define CAAM_ARB_END_ADDR 0x00103FFF
	30	#define APBH_DMA_ARB_BASE_ADDR 0x00110000
	31	#define APBH_DMA_ARB_END_ADDR 0x00117FFF
	32	#define HDMI_ARB_BASE_ADDR 0x00120000
	33	#define HDMI_ARB_END_ADDR 0x00128FFF
	34	#define GPU_3D_ARB_BASE_ADDR 0x00130000
	35	#define GPU_3D_ARB_END_ADDR 0x00133FFF
	36	#define GPU_2D_ARB_BASE_ADDR 0x00134000
	37	#define GPU_2D_ARB_END_ADDR 0x00137FFF
	38	#define DTCP_ARB_BASE_ADDR 0x00138000
	39	#define DTCP_ARB_END_ADDR 0x0013BFFF
	40
	41	/* GPV - PL301 configuration ports */
	42	#define GPV2_BASE_ADDR 0x00200000
	43	#define GPV3_BASE_ADDR 0x00300000
	44	#define GPV4_BASE_ADDR 0x00800000
	45	#define IRAM_BASE_ADDR 0x00900000
	46	#define SCU_BASE_ADDR 0x00A00000
	47	#define IC_INTERFACES_BASE_ADDR 0x00A00100
	48	#define GLOBAL_TIMER_BASE_ADDR 0x00A00200
	49	#define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600
	50	#define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000
	51	#define GPV0_BASE_ADDR 0x00B00000
	52	#define GPV1_BASE_ADDR 0x00C00000
	53	#define PCIE_ARB_BASE_ADDR 0x01000000
	54	#define PCIE_ARB_END_ADDR 0x01FFFFFF
	55
	56	#define AIPS1_ARB_BASE_ADDR 0x02000000
	57	#define AIPS1_ARB_END_ADDR 0x020FFFFF
	58	#define AIPS2_ARB_BASE_ADDR 0x02100000
	59	#define AIPS2_ARB_END_ADDR 0x021FFFFF
	60	#define SATA_ARB_BASE_ADDR 0x02200000
	61	#define SATA_ARB_END_ADDR 0x02203FFF
	62	#define OPENVG_ARB_BASE_ADDR 0x02204000
	63	#define OPENVG_ARB_END_ADDR 0x02207FFF
	64	#define HSI_ARB_BASE_ADDR 0x02208000
	65	#define HSI_ARB_END_ADDR 0x0220BFFF
	66	#define IPU1_ARB_BASE_ADDR 0x02400000
	67	#define IPU1_ARB_END_ADDR 0x027FFFFF
	68	#define IPU2_ARB_BASE_ADDR 0x02800000
	69	#define IPU2_ARB_END_ADDR 0x02BFFFFF
	70	#define WEIM_ARB_BASE_ADDR 0x08000000
	71	#define WEIM_ARB_END_ADDR 0x0FFFFFFF
	72
	73	#define MMDC0_ARB_BASE_ADDR 0x10000000
	74	#define MMDC0_ARB_END_ADDR 0x7FFFFFFF
	75	#define MMDC1_ARB_BASE_ADDR 0x80000000
	76	#define MMDC1_ARB_END_ADDR 0xFFFFFFFF
	77
05d4df1d FE	78	#define IPU_SOC_BASE_ADDR IPU1_ARB_BASE_ADDR
	79	#define IPU_SOC_OFFSET 0x00200000
	80
23608e23 JL	81	/* Defines for Blocks connected via AIPS (SkyBlue) */
	82	#define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
	83	#define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR
	84	#define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR
	85	#define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR
	86
	87	#define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000)
	88	#define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000)
	89	#define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000)
	90	#define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000)
	91	#define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000)
	92	#define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
	93	#define UART1_BASE (ATZ1_BASE_ADDR + 0x20000)
	94	#define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
	95	#define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
	96	#define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
	97	#define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
	98	#define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
	99	#define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000)
	100	#define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000)
	101	#define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000)
	102
	103	#define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000)
	104	#define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000)
	105	#define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000)
	106	#define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000)
	107	#define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000)
	108	#define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000)
	109	#define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000)
	110	#define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000)
	111	#define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000)
	112	#define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000)
	113	#define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000)
	114	#define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000)
	115	#define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000)
	116	#define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000)
	117	#define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
	118	#define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000)
	119	#define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000)
	120	#define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000)
3f467529 WG	121	#define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000)
	122	#define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000)
	123	#define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000)
23608e23	124	#define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000)
23608e23 JL	125	#define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000)
	126	#define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000)
	127	#define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000)
	128	#define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000)
	129	#define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000)
	130	#define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000)
	131	#define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
	132	#define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
	133	#define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
	134
	135	#define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000)
	136	#define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000)
	137	#define CAAM_BASE_ADDR (ATZ2_BASE_ADDR)
	138	#define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)
	139	#define USBOH3_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
	140	#define USBOH3_USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
	141	#define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
	142	#define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
	143	#define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
	144	#define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
	145	#define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
	146	#define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
	147	#define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000)
	148	#define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000)
	149	#define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000)
	150	#define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000)
	151	#define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000)
	152	#define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
	153	#define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000)
	154	#define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000)
	155	#define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000)
	156	#define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000)
	157	#define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
	158	#define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
	159	#define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000)
	160	#define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
	161	#define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
	162	#define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
	163	#define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
	164	#define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
	165	#define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000)
	166	#define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000)
	167	#define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000)
	168	#define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000)
	169	#define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
	170	#define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
	171
	172	#define CHIP_REV_1_0 0x10
	173	#define IRAM_SIZE 0x00040000
	174	#define IMX_IIM_BASE OCOTP_BASE_ADDR
28774cba	175	#define FEC_QUIRK_ENET_MAC
23608e23 JL	176
	177	#if !(defined(__KERNEL_STRICT_NAMES) \|\| defined(__ASSEMBLY__))
	178	#include <asm/types.h>
	179
be252b65	180	extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
23608e23 JL	181
	182	/* System Reset Controller (SRC) */
	183	struct src {
	184	u32 scr;
	185	u32 sbmr1;
	186	u32 srsr;
	187	u32 reserved1[2];
	188	u32 sisr;
	189	u32 simr;
	190	u32 sbmr2;
	191	u32 gpr1;
	192	u32 gpr2;
	193	u32 gpr3;
	194	u32 gpr4;
	195	u32 gpr5;
	196	u32 gpr6;
	197	u32 gpr7;
	198	u32 gpr8;
	199	u32 gpr9;
	200	u32 gpr10;
	201	};
	202
a83e1b7b EN	203	/* GPR3 bitfields */
	204	#define IOMUXC_GPR3_GPU_DBG_OFFSET 29
	205	#define IOMUXC_GPR3_GPU_DBG_MASK (3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
	206	#define IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET 28
	207	#define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET)
	208	#define IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET 27
	209	#define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET)
	210	#define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET 26
	211	#define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET)
	212	#define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET 25
	213	#define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET)
	214	#define IOMUXC_GPR3_OCRAM_CTL_OFFSET 21
	215	#define IOMUXC_GPR3_OCRAM_CTL_MASK (0xf<<IOMUXC_GPR3_OCRAM_CTL_OFFSET)
	216	#define IOMUXC_GPR3_OCRAM_STATUS_OFFSET 17
	217	#define IOMUXC_GPR3_OCRAM_STATUS_MASK (0xf<<IOMUXC_GPR3_OCRAM_STATUS_OFFSET)
	218	#define IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET 16
	219	#define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET)
	220	#define IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET 15
	221	#define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET)
	222	#define IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET 14
	223	#define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET)
	224	#define IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET 13
	225	#define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET)
	226	#define IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET 12
	227	#define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET)
	228	#define IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET 11
	229	#define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET)
	230	#define IOMUXC_GPR3_IPU_DIAG_OFFSET 10
	231	#define IOMUXC_GPR3_IPU_DIAG_MASK (1<<IOMUXC_GPR3_IPU_DIAG_OFFSET)
	232
	233	#define IOMUXC_GPR3_MUX_SRC_IPU1_DI0 0
	234	#define IOMUXC_GPR3_MUX_SRC_IPU1_DI1 1
	235	#define IOMUXC_GPR3_MUX_SRC_IPU2_DI0 2
	236	#define IOMUXC_GPR3_MUX_SRC_IPU2_DI1 3
	237
	238	#define IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET 8
	239	#define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET)
	240
	241	#define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET 6
	242	#define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)
	243
	244	#define IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET 4
	245	#define IOMUXC_GPR3_MIPI_MUX_CTL_MASK (3<<IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET)
	246
	247	#define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET 2
	248	#define IOMUXC_GPR3_HDMI_MUX_CTL_MASK (3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET)
	249
	250
d5c37c9c EN	251	/* ECSPI registers */
	252	struct cspi_regs {
	253	u32 rxdata;
	254	u32 txdata;
	255	u32 ctrl;
	256	u32 cfg;
	257	u32 intr;
	258	u32 dma;
	259	u32 stat;
	260	u32 period;
	261	};
	262
	263	/*
	264	* CSPI register definitions
	265	*/
	266	#define MXC_ECSPI
	267	#define MXC_CSPICTRL_EN (1 << 0)
	268	#define MXC_CSPICTRL_MODE (1 << 1)
	269	#define MXC_CSPICTRL_XCH (1 << 2)
	270	#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
	271	#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
	272	#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
	273	#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
	274	#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
	275	#define MXC_CSPICTRL_MAXBITS 0xfff
	276	#define MXC_CSPICTRL_TC (1 << 7)
	277	#define MXC_CSPICTRL_RXOVF (1 << 6)
	278	#define MXC_CSPIPERIOD_32KHZ (1 << 15)
	279	#define MAX_SPI_BYTES 32
	280
	281	/* Bit position inside CTRL register to be associated with SS */
	282	#define MXC_CSPICTRL_CHAN 18
	283
	284	/* Bit position inside CON register to be associated with SS */
	285	#define MXC_CSPICON_POL 4
	286	#define MXC_CSPICON_PHA 0
	287	#define MXC_CSPICON_SSPOL 12
	288	#define MXC_SPI_BASE_ADDRESSES \
	289	ECSPI1_BASE_ADDR, \
	290	ECSPI2_BASE_ADDR, \
	291	ECSPI3_BASE_ADDR, \
	292	ECSPI4_BASE_ADDR, \
	293	ECSPI5_BASE_ADDR
	294
23608e23 JL	295	struct iim_regs {
	296	u32 ctrl;
	297	u32 ctrl_set;
	298	u32 ctrl_clr;
	299	u32 ctrl_tog;
	300	u32 timing;
	301	u32 rsvd0[3];
	302	u32 data;
	303	u32 rsvd1[3];
	304	u32 read_ctrl;
	305	u32 rsvd2[3];
	306	u32 fuse_data;
	307	u32 rsvd3[3];
	308	u32 sticky;
	309	u32 rsvd4[3];
	310	u32 scs;
	311	u32 scs_set;
	312	u32 scs_clr;
	313	u32 scs_tog;
	314	u32 crc_addr;
	315	u32 rsvd5[3];
	316	u32 crc_value;
	317	u32 rsvd6[3];
	318	u32 version;
bd2e27c0	319	u32 rsvd7[0xdb];
23608e23 JL	320
	321	struct fuse_bank {
	322	u32 fuse_regs[0x20];
	323	} bank[15];
	324	};
	325
	326	struct fuse_bank4_regs {
	327	u32 sjc_resp_low;
	328	u32 rsvd0[3];
	329	u32 sjc_resp_high;
	330	u32 rsvd1[3];
	331	u32 mac_addr_low;
	332	u32 rsvd2[3];
	333	u32 mac_addr_high;
	334	u32 rsvd3[0x13];
	335	};
	336
f2f77458 JL	337	struct aipstz_regs {
	338	u32 mprot0;
	339	u32 mprot1;
	340	u32 rsvd[0xe];
	341	u32 opacr0;
	342	u32 opacr1;
	343	u32 opacr2;
	344	u32 opacr3;
	345	u32 opacr4;
	346	};
	347
a7683867 FE	348	struct anatop_regs {
	349	u32 pll_sys; /* 0x000 */
	350	u32 pll_sys_set; /* 0x004 */
	351	u32 pll_sys_clr; /* 0x008 */
	352	u32 pll_sys_tog; /* 0x00c */
	353	u32 usb1_pll_480_ctrl; /* 0x010 */
	354	u32 usb1_pll_480_ctrl_set; /* 0x014 */
	355	u32 usb1_pll_480_ctrl_clr; /* 0x018 */
	356	u32 usb1_pll_480_ctrl_tog; /* 0x01c */
	357	u32 usb2_pll_480_ctrl; /* 0x020 */
	358	u32 usb2_pll_480_ctrl_set; /* 0x024 */
	359	u32 usb2_pll_480_ctrl_clr; /* 0x028 */
	360	u32 usb2_pll_480_ctrl_tog; /* 0x02c */
	361	u32 pll_528; /* 0x030 */
	362	u32 pll_528_set; /* 0x034 */
	363	u32 pll_528_clr; /* 0x038 */
	364	u32 pll_528_tog; /* 0x03c */
	365	u32 pll_528_ss; /* 0x040 */
	366	u32 rsvd0[3];
	367	u32 pll_528_num; /* 0x050 */
	368	u32 rsvd1[3];
	369	u32 pll_528_denom; /* 0x060 */
	370	u32 rsvd2[3];
	371	u32 pll_audio; /* 0x070 */
	372	u32 pll_audio_set; /* 0x074 */
	373	u32 pll_audio_clr; /* 0x078 */
	374	u32 pll_audio_tog; /* 0x07c */
	375	u32 pll_audio_num; /* 0x080 */
	376	u32 rsvd3[3];
	377	u32 pll_audio_denom; /* 0x090 */
	378	u32 rsvd4[3];
	379	u32 pll_video; /* 0x0a0 */
	380	u32 pll_video_set; /* 0x0a4 */
	381	u32 pll_video_clr; /* 0x0a8 */
	382	u32 pll_video_tog; /* 0x0ac */
	383	u32 pll_video_num; /* 0x0b0 */
	384	u32 rsvd5[3];
	385	u32 pll_video_denom; /* 0x0c0 */
	386	u32 rsvd6[3];
	387	u32 pll_mlb; /* 0x0d0 */
	388	u32 pll_mlb_set; /* 0x0d4 */
	389	u32 pll_mlb_clr; /* 0x0d8 */
	390	u32 pll_mlb_tog; /* 0x0dc */
	391	u32 pll_enet; /* 0x0e0 */
	392	u32 pll_enet_set; /* 0x0e4 */
	393	u32 pll_enet_clr; /* 0x0e8 */
	394	u32 pll_enet_tog; /* 0x0ec */
	395	u32 pfd_480; /* 0x0f0 */
	396	u32 pfd_480_set; /* 0x0f4 */
	397	u32 pfd_480_clr; /* 0x0f8 */
	398	u32 pfd_480_tog; /* 0x0fc */
	399	u32 pfd_528; /* 0x100 */
	400	u32 pfd_528_set; /* 0x104 */
	401	u32 pfd_528_clr; /* 0x108 */
	402	u32 pfd_528_tog; /* 0x10c */
	403	u32 reg_1p1; /* 0x110 */
	404	u32 reg_1p1_set; /* 0x114 */
	405	u32 reg_1p1_clr; /* 0x118 */
	406	u32 reg_1p1_tog; /* 0x11c */
	407	u32 reg_3p0; /* 0x120 */
	408	u32 reg_3p0_set; /* 0x124 */
	409	u32 reg_3p0_clr; /* 0x128 */
	410	u32 reg_3p0_tog; /* 0x12c */
	411	u32 reg_2p5; /* 0x130 */
412	u32 reg_2p5_set; /* 0x134 */
413	u32 reg_2p5_clr; /* 0x138 */
414	u32 reg_2p5_tog; /* 0x13c */
415	u32 reg_core; /* 0x140 */
416	u32 reg_core_set; /* 0x144 */
417	u32 reg_core_clr; /* 0x148 */
418	u32 reg_core_tog; /* 0x14c */
419	u32 ana_misc0; /* 0x150 */
420	u32 ana_misc0_set; /* 0x154 */
421	u32 ana_misc0_clr; /* 0x158 */
422	u32 ana_misc0_tog; /* 0x15c */
423	u32 ana_misc1; /* 0x160 */
424	u32 ana_misc1_set; /* 0x164 */
425	u32 ana_misc1_clr; /* 0x168 */
426	u32 ana_misc1_tog; /* 0x16c */
427	u32 ana_misc2; /* 0x170 */
428	u32 ana_misc2_set; /* 0x174 */
429	u32 ana_misc2_clr; /* 0x178 */
430	u32 ana_misc2_tog; /* 0x17c */
431	u32 tempsense0; /* 0x180 */
432	u32 tempsense0_set; /* 0x184 */
433	u32 tempsense0_clr; /* 0x188 */
434	u32 tempsense0_tog; /* 0x18c */
435	u32 tempsense1; /* 0x190 */
436	u32 tempsense1_set; /* 0x194 */
437	u32 tempsense1_clr; /* 0x198 */
438	u32 tempsense1_tog; /* 0x19c */
439	u32 usb1_vbus_detect; /* 0x1a0 */
440	u32 usb1_vbus_detect_set; /* 0x1a4 */
441	u32 usb1_vbus_detect_clr; /* 0x1a8 */
442	u32 usb1_vbus_detect_tog; /* 0x1ac */
443	u32 usb1_chrg_detect; /* 0x1b0 */
444	u32 usb1_chrg_detect_set; /* 0x1b4 */
445	u32 usb1_chrg_detect_clr; /* 0x1b8 */
446	u32 usb1_chrg_detect_tog; /* 0x1bc */
447	u32 usb1_vbus_det_stat; /* 0x1c0 */
448	u32 usb1_vbus_det_stat_set; /* 0x1c4 */
449	u32 usb1_vbus_det_stat_clr; /* 0x1c8 */
450	u32 usb1_vbus_det_stat_tog; /* 0x1cc */
451	u32 usb1_chrg_det_stat; /* 0x1d0 */
452	u32 usb1_chrg_det_stat_set; /* 0x1d4 */
453	u32 usb1_chrg_det_stat_clr; /* 0x1d8 */
454	u32 usb1_chrg_det_stat_tog; /* 0x1dc */
455	u32 usb1_loopback; /* 0x1e0 */
456	u32 usb1_loopback_set; /* 0x1e4 */
457	u32 usb1_loopback_clr; /* 0x1e8 */
458	u32 usb1_loopback_tog; /* 0x1ec */
459	u32 usb1_misc; /* 0x1f0 */
460	u32 usb1_misc_set; /* 0x1f4 */
461	u32 usb1_misc_clr; /* 0x1f8 */
462	u32 usb1_misc_tog; /* 0x1fc */
463	u32 usb2_vbus_detect; /* 0x200 */
464	u32 usb2_vbus_detect_set; /* 0x204 */
465	u32 usb2_vbus_detect_clr; /* 0x208 */
466	u32 usb2_vbus_detect_tog; /* 0x20c */
467	u32 usb2_chrg_detect; /* 0x210 */
468	u32 usb2_chrg_detect_set; /* 0x214 */
469	u32 usb2_chrg_detect_clr; /* 0x218 */
470	u32 usb2_chrg_detect_tog; /* 0x21c */
471	u32 usb2_vbus_det_stat; /* 0x220 */
472	u32 usb2_vbus_det_stat_set; /* 0x224 */
473	u32 usb2_vbus_det_stat_clr; /* 0x228 */
474	u32 usb2_vbus_det_stat_tog; /* 0x22c */
475	u32 usb2_chrg_det_stat; /* 0x230 */
476	u32 usb2_chrg_det_stat_set; /* 0x234 */
477	u32 usb2_chrg_det_stat_clr; /* 0x238 */
478	u32 usb2_chrg_det_stat_tog; /* 0x23c */
479	u32 usb2_loopback; /* 0x240 */
480	u32 usb2_loopback_set; /* 0x244 */
481	u32 usb2_loopback_clr; /* 0x248 */
482	u32 usb2_loopback_tog; /* 0x24c */
483	u32 usb2_misc; /* 0x250 */
484	u32 usb2_misc_set; /* 0x254 */
485	u32 usb2_misc_clr; /* 0x258 */
486	u32 usb2_misc_tog; /* 0x25c */
487	u32 digprog; /* 0x260 */
488	};
489
e66ad6e7 EN	490	#define ANATOP_PFD_480_PFD0_FRAC_SHIFT 0
	491	#define ANATOP_PFD_480_PFD0_FRAC_MASK (0x3f<<ANATOP_PFD_480_PFD0_FRAC_SHIFT)
	492	#define ANATOP_PFD_480_PFD0_STABLE_SHIFT 6
	493	#define ANATOP_PFD_480_PFD0_STABLE_MASK (1<<ANATOP_PFD_480_PFD0_STABLE_SHIFT)
	494	#define ANATOP_PFD_480_PFD0_CLKGATE_SHIFT 7
	495	#define ANATOP_PFD_480_PFD0_CLKGATE_MASK (1<<ANATOP_PFD_480_PFD0_CLKGATE_SHIFT)
	496	#define ANATOP_PFD_480_PFD1_FRAC_SHIFT 8
	497	#define ANATOP_PFD_480_PFD1_FRAC_MASK (0x3f<<ANATOP_PFD_480_PFD1_FRAC_SHIFT)
	498	#define ANATOP_PFD_480_PFD1_STABLE_SHIFT 14
	499	#define ANATOP_PFD_480_PFD1_STABLE_MASK (1<<ANATOP_PFD_480_PFD1_STABLE_SHIFT)
	500	#define ANATOP_PFD_480_PFD1_CLKGATE_SHIFT 15
	501	#define ANATOP_PFD_480_PFD1_CLKGATE_MASK (0x3f<<ANATOP_PFD_480_PFD1_CLKGATE_SHIFT)
	502	#define ANATOP_PFD_480_PFD2_FRAC_SHIFT 16
	503	#define ANATOP_PFD_480_PFD2_FRAC_MASK (1<<ANATOP_PFD_480_PFD2_FRAC_SHIFT)
	504	#define ANATOP_PFD_480_PFD2_STABLE_SHIFT 22
	505	#define ANATOP_PFD_480_PFD2_STABLE_MASK (1<<ANATOP_PFD_480_PFD2_STABLE_SHIFT)
	506	#define ANATOP_PFD_480_PFD2_CLKGATE_SHIFT 23
	507	#define ANATOP_PFD_480_PFD2_CLKGATE_MASK (0x3f<<ANATOP_PFD_480_PFD2_CLKGATE_SHIFT)
	508	#define ANATOP_PFD_480_PFD3_FRAC_SHIFT 24
	509	#define ANATOP_PFD_480_PFD3_FRAC_MASK (1<<ANATOP_PFD_480_PFD3_FRAC_SHIFT)
	510	#define ANATOP_PFD_480_PFD3_STABLE_SHIFT 30
	511	#define ANATOP_PFD_480_PFD3_STABLE_MASK (1<<ANATOP_PFD_480_PFD3_STABLE_SHIFT)
	512	#define ANATOP_PFD_480_PFD3_CLKGATE_SHIFT 31
	513
64e7cdb5 EN	514	struct iomuxc_base_regs {
	515	u32 gpr[14]; /* 0x000 */
	516	u32 obsrv[5]; /* 0x038 */
	517	u32 swmux_ctl[197]; /* 0x04c */
	518	u32 swpad_ctl[250]; /* 0x360 */
	519	u32 swgrp[26]; /* 0x748 */
	520	u32 daisy[104]; /* 0x7b0..94c */
	521	};
	522
124a06d7 TK	523	struct src_regs {
	524	u32 scr; /* 0x00 */
	525	u32 sbmr1; /* 0x04 */
	526	u32 srsr; /* 0x08 */
	527	u32 reserved1; /* 0x0c */
	528	u32 reserved2; /* 0x10 */
	529	u32 sisr; /* 0x14 */
	530	u32 simr; /* 0x18 */
	531	u32 sbmr2; /* 0x1c */
	532	u32 gpr1; /* 0x20 */
	533	u32 gpr2; /* 0x24 */
	534	u32 gpr3; /* 0x28 */
	535	u32 gpr4; /* 0x2c */
	536	u32 gpr5; /* 0x30 */
	537	u32 gpr6; /* 0x34 */
	538	u32 gpr7; /* 0x38 */
	539	u32 gpr8; /* 0x3c */
	540	u32 gpr9; /* 0x40 */
	541	u32 gpr10; /* 0x44 */
	542	};
	543
23608e23 JL	544	#endif /* __ASSEMBLER__*/
23608e23 JL	545	#endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */