projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| b2d20161 MV |
1 | /* |
| 2 | * Freescale i.MX28 USB PHY Register Definitions | |
| 3 | * | |
| 4 | * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> | |
| 5 | * on behalf of DENX Software Engineering GmbH | |
| 6 | * | |
| 1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
| b2d20161 MV |
8 | */ |
| 9 | ||
| 10 | #ifndef __REGS_USBPHY_H__ | |
| 11 | #define __REGS_USBPHY_H__ | |
| 12 | ||
| 9c471142 | 13 | struct mxs_usbphy_regs { |
| ddcf13b1 OS |
14 | mxs_reg_32(hw_usbphy_pwd) |
| 15 | mxs_reg_32(hw_usbphy_tx) | |
| 16 | mxs_reg_32(hw_usbphy_rx) | |
| 17 | mxs_reg_32(hw_usbphy_ctrl) | |
| 18 | mxs_reg_32(hw_usbphy_status) | |
| 19 | mxs_reg_32(hw_usbphy_debug) | |
| 20 | mxs_reg_32(hw_usbphy_debug0_status) | |
| 21 | mxs_reg_32(hw_usbphy_debug1) | |
| 22 | mxs_reg_32(hw_usbphy_version) | |
| 23 | mxs_reg_32(hw_usbphy_ip) | |
| b2d20161 MV |
24 | }; |
| 25 | ||
| 26 | #define USBPHY_PWD_RXPWDRX (1 << 20) | |
| 27 | #define USBPHY_PWD_RXPWDDIFF (1 << 19) | |
| 28 | #define USBPHY_PWD_RXPWD1PT1 (1 << 18) | |
| 29 | #define USBPHY_PWD_RXPWDENV (1 << 17) | |
| 30 | #define USBPHY_PWD_TXPWDV2I (1 << 12) | |
| 31 | #define USBPHY_PWD_TXPWDIBIAS (1 << 11) | |
| 32 | #define USBPHY_PWD_TXPWDFS (1 << 10) | |
| 33 | ||
| 34 | #define USBPHY_TX_USBPHY_TX_EDGECTRL_OFFSET 26 | |
| 35 | #define USBPHY_TX_USBPHY_TX_EDGECTRL_MASK (0x7 << 26) | |
| 36 | #define USBPHY_TX_USBPHY_TX_SYNC_INVERT (1 << 25) | |
| 37 | #define USBPHY_TX_USBPHY_TX_SYNC_MUX (1 << 24) | |
| 38 | #define USBPHY_TX_TXENCAL45DP (1 << 21) | |
| 39 | #define USBPHY_TX_TXCAL45DP_OFFSET 16 | |
| 40 | #define USBPHY_TX_TXCAL45DP_MASK (0xf << 16) | |
| 41 | #define USBPHY_TX_TXENCAL45DM (1 << 13) | |
| 42 | #define USBPHY_TX_TXCAL45DM_OFFSET 8 | |
| 43 | #define USBPHY_TX_TXCAL45DM_MASK (0xf << 8) | |
| 44 | #define USBPHY_TX_D_CAL_OFFSET 0 | |
| 45 | #define USBPHY_TX_D_CAL_MASK 0xf | |
| 46 | ||
| 47 | #define USBPHY_RX_RXDBYPASS (1 << 22) | |
| 48 | #define USBPHY_RX_DISCONADJ_OFFSET 4 | |
| 49 | #define USBPHY_RX_DISCONADJ_MASK (0x7 << 4) | |
| 50 | #define USBPHY_RX_ENVADJ_OFFSET 0 | |
| 51 | #define USBPHY_RX_ENVADJ_MASK 0x7 | |
| 52 | ||
| 53 | #define USBPHY_CTRL_SFTRST (1 << 31) | |
| 54 | #define USBPHY_CTRL_CLKGATE (1 << 30) | |
| 55 | #define USBPHY_CTRL_UTMI_SUSPENDM (1 << 29) | |
| 56 | #define USBPHY_CTRL_HOST_FORCE_LS_SE0 (1 << 28) | |
| 57 | #define USBPHY_CTRL_ENAUTOSET_USBCLKS (1 << 26) | |
| 58 | #define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE (1 << 25) | |
| 59 | #define USBPHY_CTRL_FSDLL_RST_EN (1 << 24) | |
| 60 | #define USBPHY_CTRL_ENVBUSCHG_WKUP (1 << 23) | |
| 61 | #define USBPHY_CTRL_ENIDCHG_WKUP (1 << 22) | |
| 62 | #define USBPHY_CTRL_ENDPDMCHG_WKUP (1 << 21) | |
| 63 | #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD (1 << 20) | |
| 64 | #define USBPHY_CTRL_ENAUTOCLR_CLKGATE (1 << 19) | |
| 65 | #define USBPHY_CTRL_ENAUTO_PWRON_PLL (1 << 18) | |
| 66 | #define USBPHY_CTRL_WAKEUP_IRQ (1 << 17) | |
| 67 | #define USBPHY_CTRL_ENIRQWAKEUP (1 << 16) | |
| 68 | #define USBPHY_CTRL_ENUTMILEVEL3 (1 << 15) | |
| 69 | #define USBPHY_CTRL_ENUTMILEVEL2 (1 << 14) | |
| 70 | #define USBPHY_CTRL_DATA_ON_LRADC (1 << 13) | |
| 71 | #define USBPHY_CTRL_DEVPLUGIN_IRQ (1 << 12) | |
| 72 | #define USBPHY_CTRL_ENIRQDEVPLUGIN (1 << 11) | |
| 73 | #define USBPHY_CTRL_RESUME_IRQ (1 << 10) | |
| 74 | #define USBPHY_CTRL_ENIRQRESUMEDETECT (1 << 9) | |
| 75 | #define USBPHY_CTRL_RESUMEIRQSTICKY (1 << 8) | |
| 76 | #define USBPHY_CTRL_ENOTGIDDETECT (1 << 7) | |
| 77 | #define USBPHY_CTRL_DEVPLUGIN_POLARITY (1 << 5) | |
| 78 | #define USBPHY_CTRL_ENDEVPLUGINDETECT (1 << 4) | |
| 79 | #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ (1 << 3) | |
| 80 | #define USBPHY_CTRL_ENIRQHOSTDISCON (1 << 2) | |
| 81 | #define USBPHY_CTRL_ENHOSTDISCONDETECT (1 << 1) | |
| 82 | ||
| 83 | #define USBPHY_STATUS_RESUME_STATUS (1 << 10) | |
| 84 | #define USBPHY_STATUS_OTGID_STATUS (1 << 8) | |
| 85 | #define USBPHY_STATUS_DEVPLUGIN_STATUS (1 << 6) | |
| 86 | #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS (1 << 3) | |
| 87 | ||
| 88 | #define USBPHY_DEBUG_CLKGATE (1 << 30) | |
| 89 | #define USBPHY_DEBUG_HOST_RESUME_DEBUG (1 << 29) | |
| 90 | #define USBPHY_DEBUG_SQUELCHRESETLENGTH_OFFSET 25 | |
| 91 | #define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK (0xf << 25) | |
| 92 | #define USBPHY_DEBUG_ENSQUELCHRESET (1 << 24) | |
| 93 | #define USBPHY_DEBUG_SQUELCHRESETCOUNT_OFFSET 16 | |
| 94 | #define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK (0x1f << 16) | |
| 95 | #define USBPHY_DEBUG_ENTX2RXCOUNT (1 << 12) | |
| 96 | #define USBPHY_DEBUG_TX2RXCOUNT_OFFSET 8 | |
| 97 | #define USBPHY_DEBUG_TX2RXCOUNT_MASK (0xf << 8) | |
| 98 | #define USBPHY_DEBUG_ENHSTPULLDOWN_OFFSET 4 | |
| 99 | #define USBPHY_DEBUG_ENHSTPULLDOWN_MASK (0x3 << 4) | |
| 100 | #define USBPHY_DEBUG_HSTPULLDOWN_OFFSET 2 | |
| 101 | #define USBPHY_DEBUG_HSTPULLDOWN_MASK (0x3 << 2) | |
| 102 | #define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD (1 << 1) | |
| 103 | #define USBPHY_DEBUG_OTGIDPIDLOCK (1 << 0) | |
| 104 | ||
| 105 | #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_OFFSET 26 | |
| 106 | #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK (0x3f << 26) | |
| 107 | #define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_OFFSET 16 | |
| 108 | #define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_MASK (0x3ff << 16) | |
| 109 | #define USBPHY_DEBUG0_STATUS_LOOP_BACK_OFFSET 0 | |
| 110 | #define USBPHY_DEBUG0_STATUS_LOOP_BACK_MASK 0xffff | |
| 111 | ||
| 112 | #define USBPHY_DEBUG1_ENTAILADJVD_OFFSET 13 | |
| 113 | #define USBPHY_DEBUG1_ENTAILADJVD_MASK (0x3 << 13) | |
| 114 | #define USBPHY_DEBUG1_ENTX2TX (1 << 12) | |
| 115 | #define USBPHY_DEBUG1_DBG_ADDRESS_OFFSET 0 | |
| 116 | #define USBPHY_DEBUG1_DBG_ADDRESS_MASK 0xf | |
| 117 | ||
| 118 | #define USBPHY_VERSION_MAJOR_MASK (0xff << 24) | |
| 119 | #define USBPHY_VERSION_MAJOR_OFFSET 24 | |
| 120 | #define USBPHY_VERSION_MINOR_MASK (0xff << 16) | |
| 121 | #define USBPHY_VERSION_MINOR_OFFSET 16 | |
| 122 | #define USBPHY_VERSION_STEP_MASK 0xffff | |
| 123 | #define USBPHY_VERSION_STEP_OFFSET 0 | |
| 124 | ||
| 125 | #define USBPHY_IP_DIV_SEL_OFFSET 23 | |
| 126 | #define USBPHY_IP_DIV_SEL_MASK (0x3 << 23) | |
| 127 | #define USBPHY_IP_LFR_SEL_OFFSET 21 | |
| 128 | #define USBPHY_IP_LFR_SEL_MASK (0x3 << 21) | |
| 129 | #define USBPHY_IP_CP_SEL_OFFSET 19 | |
| 130 | #define USBPHY_IP_CP_SEL_MASK (0x3 << 19) | |
| 131 | #define USBPHY_IP_TSTI_TX_DP (1 << 18) | |
| 132 | #define USBPHY_IP_TSTI_TX_DM (1 << 17) | |
| 133 | #define USBPHY_IP_ANALOG_TESTMODE (1 << 16) | |
| 134 | #define USBPHY_IP_EN_USB_CLKS (1 << 2) | |
| 135 | #define USBPHY_IP_PLL_LOCKED (1 << 1) | |
| 136 | #define USBPHY_IP_PLL_POWER (1 << 0) | |
| 137 | ||
| 138 | #endif /* __REGS_USBPHY_H__ */ |