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2c803210 DB |
1 | /* |
2 | * (C) Copyright 2006-2008 | |
3 | * Texas Instruments, <www.ti.com> | |
4 | * Richard Woodruff <r-woodruff2@ti.com> | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
2c803210 DB |
7 | */ |
8 | #ifndef _CLOCKS_OMAP3_H_ | |
9 | #define _CLOCKS_OMAP3_H_ | |
10 | ||
11 | #define PLL_STOP 1 /* PER & IVA */ | |
12 | #define PLL_LOW_POWER_BYPASS 5 /* MPU, IVA & CORE */ | |
13 | #define PLL_FAST_RELOCK_BYPASS 6 /* CORE */ | |
14 | #define PLL_LOCK 7 /* MPU, IVA, CORE & PER */ | |
15 | ||
16 | /* | |
17 | * The following configurations are OPP and SysClk value independant | |
18 | * and hence are defined here. All the other DPLL related values are | |
19 | * tabulated in lowlevel_init.S. | |
20 | */ | |
21 | ||
22 | /* CORE DPLL */ | |
23 | #define CORE_M3X2 2 /* 332MHz : CM_CLKSEL1_EMU */ | |
24 | #define CORE_SSI_DIV 3 /* 221MHz : CM_CLKSEL_CORE */ | |
25 | #define CORE_FUSB_DIV 2 /* 41.5MHz: */ | |
26 | #define CORE_L4_DIV 2 /* 83MHz : L4 */ | |
27 | #define CORE_L3_DIV 2 /* 166MHz : L3 {DDR} */ | |
28 | #define GFX_DIV 2 /* 83MHz : CM_CLKSEL_GFX */ | |
f4dac3e1 | 29 | #define GFX_DIV_36X 5 /* 200MHz : CM_CLKSEL_GFX */ |
2c803210 DB |
30 | #define WKUP_RSM 2 /* 41.5MHz: CM_CLKSEL_WKUP */ |
31 | ||
32 | /* PER DPLL */ | |
33 | #define PER_M6X2 3 /* 288MHz: CM_CLKSEL1_EMU */ | |
34 | #define PER_M5X2 4 /* 216MHz: CM_CLKSEL_CAM */ | |
35 | #define PER_M4X2 2 /* 432MHz: CM_CLKSEL_DSS-dss1 */ | |
36 | #define PER_M3X2 16 /* 54MHz : CM_CLKSEL_DSS-tv */ | |
37 | ||
38 | #define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0A50)) | |
39 | ||
40 | /* MPU DPLL */ | |
41 | ||
42 | #define MPU_M_12_ES1 0x0FE | |
43 | #define MPU_N_12_ES1 0x07 | |
44 | #define MPU_FSEL_12_ES1 0x05 | |
45 | #define MPU_M2_12_ES1 0x01 | |
46 | ||
47 | #define MPU_M_12_ES2 0x0FA | |
48 | #define MPU_N_12_ES2 0x05 | |
49 | #define MPU_FSEL_12_ES2 0x07 | |
50 | #define MPU_M2_ES2 0x01 | |
51 | ||
52 | #define MPU_M_12 0x085 | |
53 | #define MPU_N_12 0x05 | |
54 | #define MPU_FSEL_12 0x07 | |
55 | #define MPU_M2_12 0x01 | |
56 | ||
57 | #define MPU_M_13_ES1 0x17D | |
58 | #define MPU_N_13_ES1 0x0C | |
59 | #define MPU_FSEL_13_ES1 0x03 | |
60 | #define MPU_M2_13_ES1 0x01 | |
61 | ||
c8e5ba80 | 62 | #define MPU_M_13_ES2 0x258 |
2c803210 DB |
63 | #define MPU_N_13_ES2 0x0C |
64 | #define MPU_FSEL_13_ES2 0x03 | |
65 | #define MPU_M2_13_ES2 0x01 | |
66 | ||
67 | #define MPU_M_13 0x10A | |
68 | #define MPU_N_13 0x0C | |
69 | #define MPU_FSEL_13 0x03 | |
70 | #define MPU_M2_13 0x01 | |
71 | ||
72 | #define MPU_M_19P2_ES1 0x179 | |
73 | #define MPU_N_19P2_ES1 0x12 | |
74 | #define MPU_FSEL_19P2_ES1 0x04 | |
75 | #define MPU_M2_19P2_ES1 0x01 | |
76 | ||
77 | #define MPU_M_19P2_ES2 0x271 | |
78 | #define MPU_N_19P2_ES2 0x17 | |
79 | #define MPU_FSEL_19P2_ES2 0x03 | |
80 | #define MPU_M2_19P2_ES2 0x01 | |
81 | ||
82 | #define MPU_M_19P2 0x14C | |
83 | #define MPU_N_19P2 0x17 | |
84 | #define MPU_FSEL_19P2 0x03 | |
85 | #define MPU_M2_19P2 0x01 | |
86 | ||
87 | #define MPU_M_26_ES1 0x17D | |
88 | #define MPU_N_26_ES1 0x19 | |
89 | #define MPU_FSEL_26_ES1 0x03 | |
90 | #define MPU_M2_26_ES1 0x01 | |
91 | ||
92 | #define MPU_M_26_ES2 0x0FA | |
93 | #define MPU_N_26_ES2 0x0C | |
94 | #define MPU_FSEL_26_ES2 0x07 | |
95 | #define MPU_M2_26_ES2 0x01 | |
96 | ||
97 | #define MPU_M_26 0x085 | |
98 | #define MPU_N_26 0x0C | |
99 | #define MPU_FSEL_26 0x07 | |
100 | #define MPU_M2_26 0x01 | |
101 | ||
102 | #define MPU_M_38P4_ES1 0x1FA | |
103 | #define MPU_N_38P4_ES1 0x32 | |
104 | #define MPU_FSEL_38P4_ES1 0x03 | |
105 | #define MPU_M2_38P4_ES1 0x01 | |
106 | ||
107 | #define MPU_M_38P4_ES2 0x271 | |
108 | #define MPU_N_38P4_ES2 0x2F | |
109 | #define MPU_FSEL_38P4_ES2 0x03 | |
110 | #define MPU_M2_38P4_ES2 0x01 | |
111 | ||
112 | #define MPU_M_38P4 0x14C | |
113 | #define MPU_N_38P4 0x2F | |
114 | #define MPU_FSEL_38P4 0x03 | |
115 | #define MPU_M2_38P4 0x01 | |
116 | ||
117 | /* IVA DPLL */ | |
118 | ||
119 | #define IVA_M_12_ES1 0x07D | |
120 | #define IVA_N_12_ES1 0x05 | |
121 | #define IVA_FSEL_12_ES1 0x07 | |
122 | #define IVA_M2_12_ES1 0x01 | |
123 | ||
124 | #define IVA_M_12_ES2 0x0B4 | |
125 | #define IVA_N_12_ES2 0x05 | |
126 | #define IVA_FSEL_12_ES2 0x07 | |
127 | #define IVA_M2_12_ES2 0x01 | |
128 | ||
129 | #define IVA_M_12 0x085 | |
130 | #define IVA_N_12 0x05 | |
131 | #define IVA_FSEL_12 0x07 | |
132 | #define IVA_M2_12 0x01 | |
133 | ||
134 | #define IVA_M_13_ES1 0x0FA | |
135 | #define IVA_N_13_ES1 0x0C | |
136 | #define IVA_FSEL_13_ES1 0x03 | |
137 | #define IVA_M2_13_ES1 0x01 | |
138 | ||
139 | #define IVA_M_13_ES2 0x168 | |
140 | #define IVA_N_13_ES2 0x0C | |
141 | #define IVA_FSEL_13_ES2 0x03 | |
142 | #define IVA_M2_13_ES2 0x01 | |
143 | ||
144 | #define IVA_M_13 0x10A | |
145 | #define IVA_N_13 0x0C | |
146 | #define IVA_FSEL_13 0x03 | |
147 | #define IVA_M2_13 0x01 | |
148 | ||
149 | #define IVA_M_19P2_ES1 0x082 | |
150 | #define IVA_N_19P2_ES1 0x09 | |
151 | #define IVA_FSEL_19P2_ES1 0x07 | |
152 | #define IVA_M2_19P2_ES1 0x01 | |
153 | ||
154 | #define IVA_M_19P2_ES2 0x0E1 | |
155 | #define IVA_N_19P2_ES2 0x0B | |
156 | #define IVA_FSEL_19P2_ES2 0x06 | |
157 | #define IVA_M2_19P2_ES2 0x01 | |
158 | ||
159 | #define IVA_M_19P2 0x14C | |
160 | #define IVA_N_19P2 0x17 | |
161 | #define IVA_FSEL_19P2 0x03 | |
162 | #define IVA_M2_19P2 0x01 | |
163 | ||
164 | #define IVA_M_26_ES1 0x07D | |
165 | #define IVA_N_26_ES1 0x0C | |
166 | #define IVA_FSEL_26_ES1 0x07 | |
167 | #define IVA_M2_26_ES1 0x01 | |
168 | ||
169 | #define IVA_M_26_ES2 0x0B4 | |
170 | #define IVA_N_26_ES2 0x0C | |
171 | #define IVA_FSEL_26_ES2 0x07 | |
172 | #define IVA_M2_26_ES2 0x01 | |
173 | ||
174 | #define IVA_M_26 0x085 | |
175 | #define IVA_N_26 0x0C | |
176 | #define IVA_FSEL_26 0x07 | |
177 | #define IVA_M2_26 0x01 | |
178 | ||
179 | #define IVA_M_38P4_ES1 0x13F | |
180 | #define IVA_N_38P4_ES1 0x30 | |
181 | #define IVA_FSEL_38P4_ES1 0x03 | |
182 | #define IVA_M2_38P4_ES1 0x01 | |
183 | ||
184 | #define IVA_M_38P4_ES2 0x0E1 | |
185 | #define IVA_N_38P4_ES2 0x17 | |
186 | #define IVA_FSEL_38P4_ES2 0x06 | |
187 | #define IVA_M2_38P4_ES2 0x01 | |
188 | ||
189 | #define IVA_M_38P4 0x14C | |
190 | #define IVA_N_38P4 0x2F | |
191 | #define IVA_FSEL_38P4 0x03 | |
192 | #define IVA_M2_38P4 0x01 | |
193 | ||
194 | /* CORE DPLL */ | |
195 | ||
196 | #define CORE_M_12 0xA6 | |
197 | #define CORE_N_12 0x05 | |
198 | #define CORE_FSEL_12 0x07 | |
199 | #define CORE_M2_12 0x01 /* M3 of 2 */ | |
200 | ||
201 | #define CORE_M_12_ES1 0x19F | |
202 | #define CORE_N_12_ES1 0x0E | |
203 | #define CORE_FSL_12_ES1 0x03 | |
204 | #define CORE_M2_12_ES1 0x1 /* M3 of 2 */ | |
205 | ||
206 | #define CORE_M_13 0x14C | |
207 | #define CORE_N_13 0x0C | |
208 | #define CORE_FSEL_13 0x03 | |
209 | #define CORE_M2_13 0x01 /* M3 of 2 */ | |
210 | ||
211 | #define CORE_M_13_ES1 0x1B2 | |
212 | #define CORE_N_13_ES1 0x10 | |
213 | #define CORE_FSL_13_ES1 0x03 | |
214 | #define CORE_M2_13_ES1 0x01 /* M3 of 2 */ | |
215 | ||
216 | #define CORE_M_19P2 0x19F | |
217 | #define CORE_N_19P2 0x17 | |
218 | #define CORE_FSEL_19P2 0x03 | |
219 | #define CORE_M2_19P2 0x01 /* M3 of 2 */ | |
220 | ||
221 | #define CORE_M_19P2_ES1 0x19F | |
222 | #define CORE_N_19P2_ES1 0x17 | |
223 | #define CORE_FSL_19P2_ES1 0x03 | |
224 | #define CORE_M2_19P2_ES1 0x01 /* M3 of 2 */ | |
225 | ||
226 | #define CORE_M_26 0xA6 | |
227 | #define CORE_N_26 0x0C | |
228 | #define CORE_FSEL_26 0x07 | |
229 | #define CORE_M2_26 0x01 /* M3 of 2 */ | |
230 | ||
231 | #define CORE_M_26_ES1 0x1B2 | |
232 | #define CORE_N_26_ES1 0x21 | |
233 | #define CORE_FSL_26_ES1 0x03 | |
234 | #define CORE_M2_26_ES1 0x01 /* M3 of 2 */ | |
235 | ||
236 | #define CORE_M_38P4 0x19F | |
237 | #define CORE_N_38P4 0x2F | |
238 | #define CORE_FSEL_38P4 0x03 | |
239 | #define CORE_M2_38P4 0x01 /* M3 of 2 */ | |
240 | ||
241 | #define CORE_M_38P4_ES1 0x19F | |
242 | #define CORE_N_38P4_ES1 0x2F | |
243 | #define CORE_FSL_38P4_ES1 0x03 | |
244 | #define CORE_M2_38P4_ES1 0x01 /* M3 of 2 */ | |
245 | ||
246 | /* PER DPLL */ | |
247 | ||
248 | #define PER_M_12 0xD8 | |
249 | #define PER_N_12 0x05 | |
250 | #define PER_FSEL_12 0x07 | |
251 | #define PER_M2_12 0x09 | |
252 | ||
253 | #define PER_M_13 0x1B0 | |
254 | #define PER_N_13 0x0C | |
255 | #define PER_FSEL_13 0x03 | |
256 | #define PER_M2_13 0x09 | |
257 | ||
258 | #define PER_M_19P2 0xE1 | |
259 | #define PER_N_19P2 0x09 | |
260 | #define PER_FSEL_19P2 0x07 | |
261 | #define PER_M2_19P2 0x09 | |
262 | ||
263 | #define PER_M_26 0xD8 | |
264 | #define PER_N_26 0x0C | |
265 | #define PER_FSEL_26 0x07 | |
266 | #define PER_M2_26 0x09 | |
267 | ||
268 | #define PER_M_38P4 0xE1 | |
269 | #define PER_N_38P4 0x13 | |
270 | #define PER_FSEL_38P4 0x07 | |
271 | #define PER_M2_38P4 0x09 | |
272 | ||
7b89795f AH |
273 | /* PER2 DPLL */ |
274 | #define PER2_M_12 0x78 | |
275 | #define PER2_N_12 0x0B | |
276 | #define PER2_FSEL_12 0x03 | |
277 | #define PER2_M2_12 0x01 | |
278 | ||
279 | #define PER2_M_13 0x78 | |
280 | #define PER2_N_13 0x0C | |
281 | #define PER2_FSEL_13 0x03 | |
282 | #define PER2_M2_13 0x01 | |
283 | ||
284 | #define PER2_M_19P2 0x2EE | |
285 | #define PER2_N_19P2 0x0B | |
286 | #define PER2_FSEL_19P2 0x06 | |
287 | #define PER2_M2_19P2 0x0A | |
288 | ||
289 | #define PER2_M_26 0x78 | |
290 | #define PER2_N_26 0x0C | |
291 | #define PER2_FSEL_26 0x03 | |
292 | #define PER2_M2_26 0x01 | |
293 | ||
294 | #define PER2_M_38P4 0x2EE | |
295 | #define PER2_N_38P4 0x0B | |
296 | #define PER2_FSEL_38P4 0x06 | |
297 | #define PER2_M2_38P4 0x0A | |
298 | ||
7c281c98 SS |
299 | /* 36XX PER DPLL */ |
300 | ||
301 | #define PER_36XX_M_12 0x1B0 | |
302 | #define PER_36XX_N_12 0x05 | |
303 | #define PER_36XX_FSEL_12 0x07 | |
304 | #define PER_36XX_M2_12 0x09 | |
305 | ||
306 | #define PER_36XX_M_13 0x360 | |
307 | #define PER_36XX_N_13 0x0C | |
308 | #define PER_36XX_FSEL_13 0x03 | |
309 | #define PER_36XX_M2_13 0x09 | |
310 | ||
311 | #define PER_36XX_M_19P2 0x1C2 | |
312 | #define PER_36XX_N_19P2 0x09 | |
313 | #define PER_36XX_FSEL_19P2 0x07 | |
314 | #define PER_36XX_M2_19P2 0x09 | |
315 | ||
316 | #define PER_36XX_M_26 0x1B0 | |
317 | #define PER_36XX_N_26 0x0C | |
318 | #define PER_36XX_FSEL_26 0x07 | |
319 | #define PER_36XX_M2_26 0x09 | |
320 | ||
321 | #define PER_36XX_M_38P4 0x1C2 | |
322 | #define PER_36XX_N_38P4 0x13 | |
323 | #define PER_36XX_FSEL_38P4 0x07 | |
324 | #define PER_36XX_M2_38P4 0x09 | |
325 | ||
2c803210 | 326 | #endif /* endif _CLOCKS_OMAP3_H_ */ |