projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 2c803210 DB |
1 | /* |
| 2 | * (C) Copyright 2006-2008 | |
| 3 | * Texas Instruments, <www.ti.com> | |
| 4 | * Syed Mohammed Khasim <x0khasim@ti.com> | |
| 5 | * | |
| 1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
| 2c803210 DB |
7 | */ |
| 8 | #ifndef _MUX_H_ | |
| 9 | #define _MUX_H_ | |
| 10 | ||
| 11 | /* | |
| 12 | * IEN - Input Enable | |
| 13 | * IDIS - Input Disable | |
| 14 | * PTD - Pull type Down | |
| 15 | * PTU - Pull type Up | |
| 16 | * DIS - Pull type selection is inactive | |
| 17 | * EN - Pull type selection is active | |
| 18 | * M0 - Mode 0 | |
| 19 | */ | |
| 20 | ||
| 21 | #define IEN (1 << 8) | |
| 22 | ||
| 23 | #define IDIS (0 << 8) | |
| 24 | #define PTU (1 << 4) | |
| 25 | #define PTD (0 << 4) | |
| 26 | #define EN (1 << 3) | |
| 27 | #define DIS (0 << 3) | |
| 28 | ||
| 29 | #define M0 0 | |
| 30 | #define M1 1 | |
| 31 | #define M2 2 | |
| 32 | #define M3 3 | |
| 33 | #define M4 4 | |
| 34 | #define M5 5 | |
| 35 | #define M6 6 | |
| 36 | #define M7 7 | |
| 37 | ||
| 38 | /* | |
| 39 | * To get the actual address the offset has to added | |
| 40 | * with OMAP34XX_CTRL_BASE to get the actual address | |
| 41 | */ | |
| 42 | ||
| 43 | /*SDRC*/ | |
| 44 | #define CONTROL_PADCONF_SDRC_D0 0x0030 | |
| 45 | #define CONTROL_PADCONF_SDRC_D1 0x0032 | |
| 46 | #define CONTROL_PADCONF_SDRC_D2 0x0034 | |
| 47 | #define CONTROL_PADCONF_SDRC_D3 0x0036 | |
| 48 | #define CONTROL_PADCONF_SDRC_D4 0x0038 | |
| 49 | #define CONTROL_PADCONF_SDRC_D5 0x003A | |
| 50 | #define CONTROL_PADCONF_SDRC_D6 0x003C | |
| 51 | #define CONTROL_PADCONF_SDRC_D7 0x003E | |
| 52 | #define CONTROL_PADCONF_SDRC_D8 0x0040 | |
| 53 | #define CONTROL_PADCONF_SDRC_D9 0x0042 | |
| 54 | #define CONTROL_PADCONF_SDRC_D10 0x0044 | |
| 55 | #define CONTROL_PADCONF_SDRC_D11 0x0046 | |
| 56 | #define CONTROL_PADCONF_SDRC_D12 0x0048 | |
| 57 | #define CONTROL_PADCONF_SDRC_D13 0x004A | |
| 58 | #define CONTROL_PADCONF_SDRC_D14 0x004C | |
| 59 | #define CONTROL_PADCONF_SDRC_D15 0x004E | |
| 60 | #define CONTROL_PADCONF_SDRC_D16 0x0050 | |
| 61 | #define CONTROL_PADCONF_SDRC_D17 0x0052 | |
| 62 | #define CONTROL_PADCONF_SDRC_D18 0x0054 | |
| 63 | #define CONTROL_PADCONF_SDRC_D19 0x0056 | |
| 64 | #define CONTROL_PADCONF_SDRC_D20 0x0058 | |
| 65 | #define CONTROL_PADCONF_SDRC_D21 0x005A | |
| 66 | #define CONTROL_PADCONF_SDRC_D22 0x005C | |
| 67 | #define CONTROL_PADCONF_SDRC_D23 0x005E | |
| 68 | #define CONTROL_PADCONF_SDRC_D24 0x0060 | |
| 69 | #define CONTROL_PADCONF_SDRC_D25 0x0062 | |
| 70 | #define CONTROL_PADCONF_SDRC_D26 0x0064 | |
| 71 | #define CONTROL_PADCONF_SDRC_D27 0x0066 | |
| 72 | #define CONTROL_PADCONF_SDRC_D28 0x0068 | |
| 73 | #define CONTROL_PADCONF_SDRC_D29 0x006A | |
| 74 | #define CONTROL_PADCONF_SDRC_D30 0x006C | |
| 75 | #define CONTROL_PADCONF_SDRC_D31 0x006E | |
| 76 | #define CONTROL_PADCONF_SDRC_CLK 0x0070 | |
| 77 | #define CONTROL_PADCONF_SDRC_DQS0 0x0072 | |
| 78 | #define CONTROL_PADCONF_SDRC_DQS1 0x0074 | |
| 79 | #define CONTROL_PADCONF_SDRC_DQS2 0x0076 | |
| 80 | #define CONTROL_PADCONF_SDRC_DQS3 0x0078 | |
| 81 | /*GPMC*/ | |
| 82 | #define CONTROL_PADCONF_GPMC_A1 0x007A | |
| 83 | #define CONTROL_PADCONF_GPMC_A2 0x007C | |
| 84 | #define CONTROL_PADCONF_GPMC_A3 0x007E | |
| 85 | #define CONTROL_PADCONF_GPMC_A4 0x0080 | |
| 86 | #define CONTROL_PADCONF_GPMC_A5 0x0082 | |
| 87 | #define CONTROL_PADCONF_GPMC_A6 0x0084 | |
| 88 | #define CONTROL_PADCONF_GPMC_A7 0x0086 | |
| 89 | #define CONTROL_PADCONF_GPMC_A8 0x0088 | |
| 90 | #define CONTROL_PADCONF_GPMC_A9 0x008A | |
| 91 | #define CONTROL_PADCONF_GPMC_A10 0x008C | |
| 92 | #define CONTROL_PADCONF_GPMC_D0 0x008E | |
| 93 | #define CONTROL_PADCONF_GPMC_D1 0x0090 | |
| 94 | #define CONTROL_PADCONF_GPMC_D2 0x0092 | |
| 95 | #define CONTROL_PADCONF_GPMC_D3 0x0094 | |
| 96 | #define CONTROL_PADCONF_GPMC_D4 0x0096 | |
| 97 | #define CONTROL_PADCONF_GPMC_D5 0x0098 | |
| 98 | #define CONTROL_PADCONF_GPMC_D6 0x009A | |
| 99 | #define CONTROL_PADCONF_GPMC_D7 0x009C | |
| 100 | #define CONTROL_PADCONF_GPMC_D8 0x009E | |
| 101 | #define CONTROL_PADCONF_GPMC_D9 0x00A0 | |
| 102 | #define CONTROL_PADCONF_GPMC_D10 0x00A2 | |
| 103 | #define CONTROL_PADCONF_GPMC_D11 0x00A4 | |
| 104 | #define CONTROL_PADCONF_GPMC_D12 0x00A6 | |
| 105 | #define CONTROL_PADCONF_GPMC_D13 0x00A8 | |
| 106 | #define CONTROL_PADCONF_GPMC_D14 0x00AA | |
| 107 | #define CONTROL_PADCONF_GPMC_D15 0x00AC | |
| 108 | #define CONTROL_PADCONF_GPMC_NCS0 0x00AE | |
| 109 | #define CONTROL_PADCONF_GPMC_NCS1 0x00B0 | |
| 110 | #define CONTROL_PADCONF_GPMC_NCS2 0x00B2 | |
| 111 | #define CONTROL_PADCONF_GPMC_NCS3 0x00B4 | |
| 112 | #define CONTROL_PADCONF_GPMC_NCS4 0x00B6 | |
| 113 | #define CONTROL_PADCONF_GPMC_NCS5 0x00B8 | |
| 114 | #define CONTROL_PADCONF_GPMC_NCS6 0x00BA | |
| 115 | #define CONTROL_PADCONF_GPMC_NCS7 0x00BC | |
| 116 | #define CONTROL_PADCONF_GPMC_CLK 0x00BE | |
| 117 | #define CONTROL_PADCONF_GPMC_NADV_ALE 0x00C0 | |
| 118 | #define CONTROL_PADCONF_GPMC_NOE 0x00C2 | |
| 119 | #define CONTROL_PADCONF_GPMC_NWE 0x00C4 | |
| 120 | #define CONTROL_PADCONF_GPMC_NBE0_CLE 0x00C6 | |
| 121 | #define CONTROL_PADCONF_GPMC_NBE1 0x00C8 | |
| 122 | #define CONTROL_PADCONF_GPMC_NWP 0x00CA | |
| 123 | #define CONTROL_PADCONF_GPMC_WAIT0 0x00CC | |
| 124 | #define CONTROL_PADCONF_GPMC_WAIT1 0x00CE | |
| 125 | #define CONTROL_PADCONF_GPMC_WAIT2 0x00D0 | |
| 126 | #define CONTROL_PADCONF_GPMC_WAIT3 0x00D2 | |
| 127 | /*DSS*/ | |
| 128 | #define CONTROL_PADCONF_DSS_PCLK 0x00D4 | |
| 129 | #define CONTROL_PADCONF_DSS_HSYNC 0x00D6 | |
| 130 | #define CONTROL_PADCONF_DSS_VSYNC 0x00D8 | |
| 131 | #define CONTROL_PADCONF_DSS_ACBIAS 0x00DA | |
| 132 | #define CONTROL_PADCONF_DSS_DATA0 0x00DC | |
| 133 | #define CONTROL_PADCONF_DSS_DATA1 0x00DE | |
| 134 | #define CONTROL_PADCONF_DSS_DATA2 0x00E0 | |
| 135 | #define CONTROL_PADCONF_DSS_DATA3 0x00E2 | |
| 136 | #define CONTROL_PADCONF_DSS_DATA4 0x00E4 | |
| 137 | #define CONTROL_PADCONF_DSS_DATA5 0x00E6 | |
| 138 | #define CONTROL_PADCONF_DSS_DATA6 0x00E8 | |
| 139 | #define CONTROL_PADCONF_DSS_DATA7 0x00EA | |
| 140 | #define CONTROL_PADCONF_DSS_DATA8 0x00EC | |
| 141 | #define CONTROL_PADCONF_DSS_DATA9 0x00EE | |
| 142 | #define CONTROL_PADCONF_DSS_DATA10 0x00F0 | |
| 143 | #define CONTROL_PADCONF_DSS_DATA11 0x00F2 | |
| 144 | #define CONTROL_PADCONF_DSS_DATA12 0x00F4 | |
| 145 | #define CONTROL_PADCONF_DSS_DATA13 0x00F6 | |
| 146 | #define CONTROL_PADCONF_DSS_DATA14 0x00F8 | |
| 147 | #define CONTROL_PADCONF_DSS_DATA15 0x00FA | |
| 148 | #define CONTROL_PADCONF_DSS_DATA16 0x00FC | |
| 149 | #define CONTROL_PADCONF_DSS_DATA17 0x00FE | |
| 150 | #define CONTROL_PADCONF_DSS_DATA18 0x0100 | |
| 151 | #define CONTROL_PADCONF_DSS_DATA19 0x0102 | |
| 152 | #define CONTROL_PADCONF_DSS_DATA20 0x0104 | |
| 153 | #define CONTROL_PADCONF_DSS_DATA21 0x0106 | |
| 154 | #define CONTROL_PADCONF_DSS_DATA22 0x0108 | |
| 155 | #define CONTROL_PADCONF_DSS_DATA23 0x010A | |
| 156 | /*CAMERA*/ | |
| 157 | #define CONTROL_PADCONF_CAM_HS 0x010C | |
| 158 | #define CONTROL_PADCONF_CAM_VS 0x010E | |
| 159 | #define CONTROL_PADCONF_CAM_XCLKA 0x0110 | |
| 160 | #define CONTROL_PADCONF_CAM_PCLK 0x0112 | |
| 161 | #define CONTROL_PADCONF_CAM_FLD 0x0114 | |
| 162 | #define CONTROL_PADCONF_CAM_D0 0x0116 | |
| 163 | #define CONTROL_PADCONF_CAM_D1 0x0118 | |
| 164 | #define CONTROL_PADCONF_CAM_D2 0x011A | |
| 165 | #define CONTROL_PADCONF_CAM_D3 0x011C | |
| 166 | #define CONTROL_PADCONF_CAM_D4 0x011E | |
| 167 | #define CONTROL_PADCONF_CAM_D5 0x0120 | |
| 168 | #define CONTROL_PADCONF_CAM_D6 0x0122 | |
| 169 | #define CONTROL_PADCONF_CAM_D7 0x0124 | |
| 170 | #define CONTROL_PADCONF_CAM_D8 0x0126 | |
| 171 | #define CONTROL_PADCONF_CAM_D9 0x0128 | |
| 172 | #define CONTROL_PADCONF_CAM_D10 0x012A | |
| 173 | #define CONTROL_PADCONF_CAM_D11 0x012C | |
| 174 | #define CONTROL_PADCONF_CAM_XCLKB 0x012E | |
| 175 | #define CONTROL_PADCONF_CAM_WEN 0x0130 | |
| 176 | #define CONTROL_PADCONF_CAM_STROBE 0x0132 | |
| 177 | #define CONTROL_PADCONF_CSI2_DX0 0x0134 | |
| 178 | #define CONTROL_PADCONF_CSI2_DY0 0x0136 | |
| 179 | #define CONTROL_PADCONF_CSI2_DX1 0x0138 | |
| 180 | #define CONTROL_PADCONF_CSI2_DY1 0x013A | |
| 181 | /*Audio Interface */ | |
| 182 | #define CONTROL_PADCONF_MCBSP2_FSX 0x013C | |
| 183 | #define CONTROL_PADCONF_MCBSP2_CLKX 0x013E | |
| 184 | #define CONTROL_PADCONF_MCBSP2_DR 0x0140 | |
| 185 | #define CONTROL_PADCONF_MCBSP2_DX 0x0142 | |
| 186 | #define CONTROL_PADCONF_MMC1_CLK 0x0144 | |
| 187 | #define CONTROL_PADCONF_MMC1_CMD 0x0146 | |
| 188 | #define CONTROL_PADCONF_MMC1_DAT0 0x0148 | |
| 189 | #define CONTROL_PADCONF_MMC1_DAT1 0x014A | |
| 190 | #define CONTROL_PADCONF_MMC1_DAT2 0x014C | |
| 191 | #define CONTROL_PADCONF_MMC1_DAT3 0x014E | |
| 192 | #define CONTROL_PADCONF_MMC1_DAT4 0x0150 | |
| 193 | #define CONTROL_PADCONF_MMC1_DAT5 0x0152 | |
| 194 | #define CONTROL_PADCONF_MMC1_DAT6 0x0154 | |
| 195 | #define CONTROL_PADCONF_MMC1_DAT7 0x0156 | |
| 196 | /*Wireless LAN */ | |
| 197 | #define CONTROL_PADCONF_MMC2_CLK 0x0158 | |
| 198 | #define CONTROL_PADCONF_MMC2_CMD 0x015A | |
| 199 | #define CONTROL_PADCONF_MMC2_DAT0 0x015C | |
| 200 | #define CONTROL_PADCONF_MMC2_DAT1 0x015E | |
| 201 | #define CONTROL_PADCONF_MMC2_DAT2 0x0160 | |
| 202 | #define CONTROL_PADCONF_MMC2_DAT3 0x0162 | |
| 203 | #define CONTROL_PADCONF_MMC2_DAT4 0x0164 | |
| 204 | #define CONTROL_PADCONF_MMC2_DAT5 0x0166 | |
| 205 | #define CONTROL_PADCONF_MMC2_DAT6 0x0168 | |
| 206 | #define CONTROL_PADCONF_MMC2_DAT7 0x016A | |
| 207 | /*Bluetooth*/ | |
| 208 | #define CONTROL_PADCONF_MCBSP3_DX 0x016C | |
| 209 | #define CONTROL_PADCONF_MCBSP3_DR 0x016E | |
| 210 | #define CONTROL_PADCONF_MCBSP3_CLKX 0x0170 | |
| 211 | #define CONTROL_PADCONF_MCBSP3_FSX 0x0172 | |
| 212 | #define CONTROL_PADCONF_UART2_CTS 0x0174 | |
| 213 | #define CONTROL_PADCONF_UART2_RTS 0x0176 | |
| 214 | #define CONTROL_PADCONF_UART2_TX 0x0178 | |
| 215 | #define CONTROL_PADCONF_UART2_RX 0x017A | |
| 216 | /*Modem Interface */ | |
| 217 | #define CONTROL_PADCONF_UART1_TX 0x017C | |
| 218 | #define CONTROL_PADCONF_UART1_RTS 0x017E | |
| 219 | #define CONTROL_PADCONF_UART1_CTS 0x0180 | |
| 220 | #define CONTROL_PADCONF_UART1_RX 0x0182 | |
| 221 | #define CONTROL_PADCONF_MCBSP4_CLKX 0x0184 | |
| 222 | #define CONTROL_PADCONF_MCBSP4_DR 0x0186 | |
| 223 | #define CONTROL_PADCONF_MCBSP4_DX 0x0188 | |
| 224 | #define CONTROL_PADCONF_MCBSP4_FSX 0x018A | |
| 225 | #define CONTROL_PADCONF_MCBSP1_CLKR 0x018C | |
| 226 | #define CONTROL_PADCONF_MCBSP1_FSR 0x018E | |
| 227 | #define CONTROL_PADCONF_MCBSP1_DX 0x0190 | |
| 228 | #define CONTROL_PADCONF_MCBSP1_DR 0x0192 | |
| 229 | #define CONTROL_PADCONF_MCBSP_CLKS 0x0194 | |
| 230 | #define CONTROL_PADCONF_MCBSP1_FSX 0x0196 | |
| 231 | #define CONTROL_PADCONF_MCBSP1_CLKX 0x0198 | |
| 232 | /*Serial Interface*/ | |
| 233 | #define CONTROL_PADCONF_UART3_CTS_RCTX 0x019A | |
| 234 | #define CONTROL_PADCONF_UART3_RTS_SD 0x019C | |
| 235 | #define CONTROL_PADCONF_UART3_RX_IRRX 0x019E | |
| 236 | #define CONTROL_PADCONF_UART3_TX_IRTX 0x01A0 | |
| 237 | #define CONTROL_PADCONF_HSUSB0_CLK 0x01A2 | |
| 238 | #define CONTROL_PADCONF_HSUSB0_STP 0x01A4 | |
| 239 | #define CONTROL_PADCONF_HSUSB0_DIR 0x01A6 | |
| 240 | #define CONTROL_PADCONF_HSUSB0_NXT 0x01A8 | |
| 241 | #define CONTROL_PADCONF_HSUSB0_DATA0 0x01AA | |
| 242 | #define CONTROL_PADCONF_HSUSB0_DATA1 0x01AC | |
| 243 | #define CONTROL_PADCONF_HSUSB0_DATA2 0x01AE | |
| 244 | #define CONTROL_PADCONF_HSUSB0_DATA3 0x01B0 | |
| 245 | #define CONTROL_PADCONF_HSUSB0_DATA4 0x01B2 | |
| 246 | #define CONTROL_PADCONF_HSUSB0_DATA5 0x01B4 | |
| 247 | #define CONTROL_PADCONF_HSUSB0_DATA6 0x01B6 | |
| 248 | #define CONTROL_PADCONF_HSUSB0_DATA7 0x01B8 | |
| 249 | #define CONTROL_PADCONF_I2C1_SCL 0x01BA | |
| 250 | #define CONTROL_PADCONF_I2C1_SDA 0x01BC | |
| 251 | #define CONTROL_PADCONF_I2C2_SCL 0x01BE | |
| 252 | #define CONTROL_PADCONF_I2C2_SDA 0x01C0 | |
| 253 | #define CONTROL_PADCONF_I2C3_SCL 0x01C2 | |
| 254 | #define CONTROL_PADCONF_I2C3_SDA 0x01C4 | |
| 255 | #define CONTROL_PADCONF_I2C4_SCL 0x0A00 | |
| 256 | #define CONTROL_PADCONF_I2C4_SDA 0x0A02 | |
| 257 | #define CONTROL_PADCONF_HDQ_SIO 0x01C6 | |
| 258 | #define CONTROL_PADCONF_MCSPI1_CLK 0x01C8 | |
| 259 | #define CONTROL_PADCONF_MCSPI1_SIMO 0x01CA | |
| 260 | #define CONTROL_PADCONF_MCSPI1_SOMI 0x01CC | |
| 261 | #define CONTROL_PADCONF_MCSPI1_CS0 0x01CE | |
| 262 | #define CONTROL_PADCONF_MCSPI1_CS1 0x01D0 | |
| 263 | #define CONTROL_PADCONF_MCSPI1_CS2 0x01D2 | |
| 264 | #define CONTROL_PADCONF_MCSPI1_CS3 0x01D4 | |
| 265 | #define CONTROL_PADCONF_MCSPI2_CLK 0x01D6 | |
| 266 | #define CONTROL_PADCONF_MCSPI2_SIMO 0x01D8 | |
| 267 | #define CONTROL_PADCONF_MCSPI2_SOMI 0x01DA | |
| 268 | #define CONTROL_PADCONF_MCSPI2_CS0 0x01DC | |
| 269 | #define CONTROL_PADCONF_MCSPI2_CS1 0x01DE | |
| 270 | /*Control and debug */ | |
| 271 | #define CONTROL_PADCONF_SYS_32K 0x0A04 | |
| 272 | #define CONTROL_PADCONF_SYS_CLKREQ 0x0A06 | |
| 273 | #define CONTROL_PADCONF_SYS_NIRQ 0x01E0 | |
| 274 | #define CONTROL_PADCONF_SYS_BOOT0 0x0A0A | |
| 275 | #define CONTROL_PADCONF_SYS_BOOT1 0x0A0C | |
| 276 | #define CONTROL_PADCONF_SYS_BOOT2 0x0A0E | |
| 277 | #define CONTROL_PADCONF_SYS_BOOT3 0x0A10 | |
| 278 | #define CONTROL_PADCONF_SYS_BOOT4 0x0A12 | |
| 279 | #define CONTROL_PADCONF_SYS_BOOT5 0x0A14 | |
| 280 | #define CONTROL_PADCONF_SYS_BOOT6 0x0A16 | |
| 281 | #define CONTROL_PADCONF_SYS_OFF_MODE 0x0A18 | |
| 282 | #define CONTROL_PADCONF_SYS_CLKOUT1 0x0A1A | |
| 283 | #define CONTROL_PADCONF_SYS_CLKOUT2 0x01E2 | |
| 284 | #define CONTROL_PADCONF_JTAG_nTRST 0x0A1C | |
| 285 | #define CONTROL_PADCONF_JTAG_TCK 0x0A1E | |
| 286 | #define CONTROL_PADCONF_JTAG_TMS 0x0A20 | |
| 287 | #define CONTROL_PADCONF_JTAG_TDI 0x0A22 | |
| 288 | #define CONTROL_PADCONF_JTAG_EMU0 0x0A24 | |
| 289 | #define CONTROL_PADCONF_JTAG_EMU1 0x0A26 | |
| 290 | #define CONTROL_PADCONF_ETK_CLK 0x0A28 | |
| 291 | #define CONTROL_PADCONF_ETK_CTL 0x0A2A | |
| 292 | #define CONTROL_PADCONF_ETK_D0 0x0A2C | |
| 293 | #define CONTROL_PADCONF_ETK_D1 0x0A2E | |
| 294 | #define CONTROL_PADCONF_ETK_D2 0x0A30 | |
| 295 | #define CONTROL_PADCONF_ETK_D3 0x0A32 | |
| 296 | #define CONTROL_PADCONF_ETK_D4 0x0A34 | |
| 297 | #define CONTROL_PADCONF_ETK_D5 0x0A36 | |
| 298 | #define CONTROL_PADCONF_ETK_D6 0x0A38 | |
| 299 | #define CONTROL_PADCONF_ETK_D7 0x0A3A | |
| 300 | #define CONTROL_PADCONF_ETK_D8 0x0A3C | |
| 301 | #define CONTROL_PADCONF_ETK_D9 0x0A3E | |
| 302 | #define CONTROL_PADCONF_ETK_D10 0x0A40 | |
| 303 | #define CONTROL_PADCONF_ETK_D11 0x0A42 | |
| 304 | #define CONTROL_PADCONF_ETK_D12 0x0A44 | |
| 305 | #define CONTROL_PADCONF_ETK_D13 0x0A46 | |
| 306 | #define CONTROL_PADCONF_ETK_D14 0x0A48 | |
| 307 | #define CONTROL_PADCONF_ETK_D15 0x0A4A | |
| 308 | #define CONTROL_PADCONF_ETK_CLK_ES2 0x05D8 | |
| 309 | #define CONTROL_PADCONF_ETK_CTL_ES2 0x05DA | |
| 310 | #define CONTROL_PADCONF_ETK_D0_ES2 0x05DC | |
| 311 | #define CONTROL_PADCONF_ETK_D1_ES2 0x05DE | |
| 312 | #define CONTROL_PADCONF_ETK_D2_ES2 0x05E0 | |
| 313 | #define CONTROL_PADCONF_ETK_D3_ES2 0x05E2 | |
| 314 | #define CONTROL_PADCONF_ETK_D4_ES2 0x05E4 | |
| 315 | #define CONTROL_PADCONF_ETK_D5_ES2 0x05E6 | |
| 316 | #define CONTROL_PADCONF_ETK_D6_ES2 0x05E8 | |
| 317 | #define CONTROL_PADCONF_ETK_D7_ES2 0x05EA | |
| 318 | #define CONTROL_PADCONF_ETK_D8_ES2 0x05EC | |
| 319 | #define CONTROL_PADCONF_ETK_D9_ES2 0x05EE | |
| 320 | #define CONTROL_PADCONF_ETK_D10_ES2 0x05F0 | |
| 321 | #define CONTROL_PADCONF_ETK_D11_ES2 0x05F2 | |
| 322 | #define CONTROL_PADCONF_ETK_D12_ES2 0x05F4 | |
| 323 | #define CONTROL_PADCONF_ETK_D13_ES2 0x05F6 | |
| 324 | #define CONTROL_PADCONF_ETK_D14_ES2 0x05F8 | |
| 325 | #define CONTROL_PADCONF_ETK_D15_ES2 0x05FA | |
| 326 | /*Die to Die */ | |
| 327 | #define CONTROL_PADCONF_D2D_MCAD0 0x01E4 | |
| 328 | #define CONTROL_PADCONF_D2D_MCAD1 0x01E6 | |
| 329 | #define CONTROL_PADCONF_D2D_MCAD2 0x01E8 | |
| 330 | #define CONTROL_PADCONF_D2D_MCAD3 0x01EA | |
| 331 | #define CONTROL_PADCONF_D2D_MCAD4 0x01EC | |
| 332 | #define CONTROL_PADCONF_D2D_MCAD5 0x01EE | |
| 333 | #define CONTROL_PADCONF_D2D_MCAD6 0x01F0 | |
| 334 | #define CONTROL_PADCONF_D2D_MCAD7 0x01F2 | |
| 335 | #define CONTROL_PADCONF_D2D_MCAD8 0x01F4 | |
| 336 | #define CONTROL_PADCONF_D2D_MCAD9 0x01F6 | |
| 337 | #define CONTROL_PADCONF_D2D_MCAD10 0x01F8 | |
| 338 | #define CONTROL_PADCONF_D2D_MCAD11 0x01FA | |
| 339 | #define CONTROL_PADCONF_D2D_MCAD12 0x01FC | |
| 340 | #define CONTROL_PADCONF_D2D_MCAD13 0x01FE | |
| 341 | #define CONTROL_PADCONF_D2D_MCAD14 0x0200 | |
| 342 | #define CONTROL_PADCONF_D2D_MCAD15 0x0202 | |
| 343 | #define CONTROL_PADCONF_D2D_MCAD16 0x0204 | |
| 344 | #define CONTROL_PADCONF_D2D_MCAD17 0x0206 | |
| 345 | #define CONTROL_PADCONF_D2D_MCAD18 0x0208 | |
| 346 | #define CONTROL_PADCONF_D2D_MCAD19 0x020A | |
| 347 | #define CONTROL_PADCONF_D2D_MCAD20 0x020C | |
| 348 | #define CONTROL_PADCONF_D2D_MCAD21 0x020E | |
| 349 | #define CONTROL_PADCONF_D2D_MCAD22 0x0210 | |
| 350 | #define CONTROL_PADCONF_D2D_MCAD23 0x0212 | |
| 351 | #define CONTROL_PADCONF_D2D_MCAD24 0x0214 | |
| 352 | #define CONTROL_PADCONF_D2D_MCAD25 0x0216 | |
| 353 | #define CONTROL_PADCONF_D2D_MCAD26 0x0218 | |
| 354 | #define CONTROL_PADCONF_D2D_MCAD27 0x021A | |
| 355 | #define CONTROL_PADCONF_D2D_MCAD28 0x021C | |
| 356 | #define CONTROL_PADCONF_D2D_MCAD29 0x021E | |
| 357 | #define CONTROL_PADCONF_D2D_MCAD30 0x0220 | |
| 358 | #define CONTROL_PADCONF_D2D_MCAD31 0x0222 | |
| 359 | #define CONTROL_PADCONF_D2D_MCAD32 0x0224 | |
| 360 | #define CONTROL_PADCONF_D2D_MCAD33 0x0226 | |
| 361 | #define CONTROL_PADCONF_D2D_MCAD34 0x0228 | |
| 362 | #define CONTROL_PADCONF_D2D_MCAD35 0x022A | |
| 363 | #define CONTROL_PADCONF_D2D_MCAD36 0x022C | |
| 364 | #define CONTROL_PADCONF_D2D_CLK26MI 0x022E | |
| 365 | #define CONTROL_PADCONF_D2D_NRESPWRON 0x0230 | |
| 366 | #define CONTROL_PADCONF_D2D_NRESWARM 0x0232 | |
| 367 | #define CONTROL_PADCONF_D2D_ARM9NIRQ 0x0234 | |
| 368 | #define CONTROL_PADCONF_D2D_UMA2P6FIQ 0x0236 | |
| 369 | #define CONTROL_PADCONF_D2D_SPINT 0x0238 | |
| 370 | #define CONTROL_PADCONF_D2D_FRINT 0x023A | |
| 371 | #define CONTROL_PADCONF_D2D_DMAREQ0 0x023C | |
| 372 | #define CONTROL_PADCONF_D2D_DMAREQ1 0x023E | |
| 373 | #define CONTROL_PADCONF_D2D_DMAREQ2 0x0240 | |
| 374 | #define CONTROL_PADCONF_D2D_DMAREQ3 0x0242 | |
| 375 | #define CONTROL_PADCONF_D2D_N3GTRST 0x0244 | |
| 376 | #define CONTROL_PADCONF_D2D_N3GTDI 0x0246 | |
| 377 | #define CONTROL_PADCONF_D2D_N3GTDO 0x0248 | |
| 378 | #define CONTROL_PADCONF_D2D_N3GTMS 0x024A | |
| 379 | #define CONTROL_PADCONF_D2D_N3GTCK 0x024C | |
| 380 | #define CONTROL_PADCONF_D2D_N3GRTCK 0x024E | |
| 381 | #define CONTROL_PADCONF_D2D_MSTDBY 0x0250 | |
| 382 | #define CONTROL_PADCONF_D2D_SWAKEUP 0x0A4C | |
| 383 | #define CONTROL_PADCONF_D2D_IDLEREQ 0x0252 | |
| 384 | #define CONTROL_PADCONF_D2D_IDLEACK 0x0254 | |
| 385 | #define CONTROL_PADCONF_D2D_MWRITE 0x0256 | |
| 386 | #define CONTROL_PADCONF_D2D_SWRITE 0x0258 | |
| 387 | #define CONTROL_PADCONF_D2D_MREAD 0x025A | |
| 388 | #define CONTROL_PADCONF_D2D_SREAD 0x025C | |
| 389 | #define CONTROL_PADCONF_D2D_MBUSFLAG 0x025E | |
| 390 | #define CONTROL_PADCONF_D2D_SBUSFLAG 0x0260 | |
| 391 | #define CONTROL_PADCONF_SDRC_CKE0 0x0262 | |
| 392 | #define CONTROL_PADCONF_SDRC_CKE1 0x0264 | |
| 393 | ||
| ad2a7909 IY |
394 | /* AM3517 specific mux configuration */ |
| 395 | #define CONTROL_PADCONF_SYS_NRESWARM 0x0A08 | |
| 396 | /* CCDC */ | |
| 397 | #define CONTROL_PADCONF_CCDC_PCLK 0x01E4 | |
| 398 | #define CONTROL_PADCONF_CCDC_FIELD 0x01E6 | |
| 399 | #define CONTROL_PADCONF_CCDC_HD 0x01E8 | |
| 400 | #define CONTROL_PADCONF_CCDC_VD 0x01EA | |
| 401 | #define CONTROL_PADCONF_CCDC_WEN 0x01EC | |
| 402 | #define CONTROL_PADCONF_CCDC_DATA0 0x01EE | |
| 403 | #define CONTROL_PADCONF_CCDC_DATA1 0x01F0 | |
| 404 | #define CONTROL_PADCONF_CCDC_DATA2 0x01F2 | |
| 405 | #define CONTROL_PADCONF_CCDC_DATA3 0x01F4 | |
| 406 | #define CONTROL_PADCONF_CCDC_DATA4 0x01F6 | |
| 407 | #define CONTROL_PADCONF_CCDC_DATA5 0x01F8 | |
| 408 | #define CONTROL_PADCONF_CCDC_DATA6 0x01FA | |
| 409 | #define CONTROL_PADCONF_CCDC_DATA7 0x01FC | |
| 410 | /* RMII */ | |
| 411 | #define CONTROL_PADCONF_RMII_MDIO_DATA 0x01FE | |
| 412 | #define CONTROL_PADCONF_RMII_MDIO_CLK 0x0200 | |
| 413 | #define CONTROL_PADCONF_RMII_RXD0 0x0202 | |
| 414 | #define CONTROL_PADCONF_RMII_RXD1 0x0204 | |
| 415 | #define CONTROL_PADCONF_RMII_CRS_DV 0x0206 | |
| 416 | #define CONTROL_PADCONF_RMII_RXER 0x0208 | |
| 417 | #define CONTROL_PADCONF_RMII_TXD0 0x020A | |
| 418 | #define CONTROL_PADCONF_RMII_TXD1 0x020C | |
| 419 | #define CONTROL_PADCONF_RMII_TXEN 0x020E | |
| 420 | #define CONTROL_PADCONF_RMII_50MHZ_CLK 0x0210 | |
| 421 | #define CONTROL_PADCONF_USB0_DRVBUS 0x0212 | |
| 422 | /* CAN */ | |
| 423 | #define CONTROL_PADCONF_HECC1_TXD 0x0214 | |
| 424 | #define CONTROL_PADCONF_HECC1_RXD 0x0216 | |
| 425 | ||
| 426 | #define CONTROL_PADCONF_SYS_BOOT7 0x0218 | |
| 427 | #define CONTROL_PADCONF_SDRC_DQS0N 0x021A | |
| 428 | #define CONTROL_PADCONF_SDRC_DQS1N 0x021C | |
| 429 | #define CONTROL_PADCONF_SDRC_DQS2N 0x021E | |
| 430 | #define CONTROL_PADCONF_SDRC_DQS3N 0x0220 | |
| 431 | #define CONTROL_PADCONF_STRBEN_DLY0 0x0222 | |
| 432 | #define CONTROL_PADCONF_STRBEN_DLY1 0x0224 | |
| 433 | #define CONTROL_PADCONF_SYS_BOOT8 0x0226 | |
| 434 | ||
| 10cd73bf GI |
435 | /* AM/DM37xx specific */ |
| 436 | #define CONTROL_PADCONF_GPIO127 0x0A54 | |
| 437 | #define CONTROL_PADCONF_GPIO126 0x0A56 | |
| 438 | #define CONTROL_PADCONF_GPIO128 0x0A58 | |
| 439 | #define CONTROL_PADCONF_GPIO129 0x0A5A | |
| 440 | ||
| 4aaf0641 AVEM |
441 | /* AM/DM37xx specific: gpio_127, gpio_127 and gpio_129 require configuration |
| 442 | * of the extended drain cells */ | |
| 443 | #define OMAP34XX_CTRL_WKUP_CTRL (OMAP34XX_CTRL_BASE + 0x0A5C) | |
| 444 | #define OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ (1<<6) | |
| 445 | ||
| 2c803210 DB |
446 | #define MUX_VAL(OFFSET,VALUE)\ |
| 447 | writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); | |
| 448 | ||
| 449 | #define CP(x) (CONTROL_PADCONF_##x) | |
| 450 | ||
| 451 | #endif |