[people/ms/u-boot.git] / arch / arm / include / asm / arch-omap4 / omap4.h

/*
 * (C) Copyright 2010
 * Texas Instruments, <www.ti.com>
 *
 * Authors:
 *	Aneesh V <aneesh@ti.com>
 *
 * Derived from OMAP3 work by
 *	Richard Woodruff <r-woodruff2@ti.com>
 *	Syed Mohammed Khasim <x0khasim@ti.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef _OMAP4_H_
#define _OMAP4_H_

#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>
#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */

/*
 * L4 Peripherals - L4 Wakeup and L4 Core now
 */
#define OMAP44XX_L4_CORE_BASE	0x4A000000
#define OMAP44XX_L4_WKUP_BASE	0x4A300000
#define OMAP44XX_L4_PER_BASE	0x48000000

#define OMAP44XX_DRAM_ADDR_SPACE_START	0x80000000
#define OMAP44XX_DRAM_ADDR_SPACE_END	0xD0000000


/* CONTROL */
#define CTRL_BASE		(OMAP44XX_L4_CORE_BASE + 0x2000)
#define CONTROL_PADCONF_CORE	(OMAP44XX_L4_CORE_BASE + 0x100000)
#define CONTROL_PADCONF_WKUP	(OMAP44XX_L4_CORE_BASE + 0x31E000)

/* LPDDR2 IO regs */
#define LPDDR2_IO_REGS_BASE	0x4A100638

#define CONTROL_EFUSE_2		0x4A100704

/* CONTROL_ID_CODE */
#define CONTROL_ID_CODE		0x4A002204

#define OMAP4_CONTROL_ID_CODE_ES1_0	0x0B85202F
#define OMAP4_CONTROL_ID_CODE_ES2_0	0x1B85202F
#define OMAP4_CONTROL_ID_CODE_ES2_1	0x3B95C02F
#define OMAP4_CONTROL_ID_CODE_ES2_2	0x4B95C02F
#define OMAP4_CONTROL_ID_CODE_ES2_3	0x6B95C02F

/* UART */
#define UART1_BASE		(OMAP44XX_L4_PER_BASE + 0x6a000)
#define UART2_BASE		(OMAP44XX_L4_PER_BASE + 0x6c000)
#define UART3_BASE		(OMAP44XX_L4_PER_BASE + 0x20000)

/* General Purpose Timers */
#define GPT1_BASE		(OMAP44XX_L4_WKUP_BASE + 0x18000)
#define GPT2_BASE		(OMAP44XX_L4_PER_BASE  + 0x32000)
#define GPT3_BASE		(OMAP44XX_L4_PER_BASE  + 0x34000)

/* Watchdog Timer2 - MPU watchdog */
#define WDT2_BASE		(OMAP44XX_L4_WKUP_BASE + 0x14000)

/* 32KTIMER */
#define SYNC_32KTIMER_BASE	(OMAP44XX_L4_WKUP_BASE + 0x4000)

/* GPMC */
#define OMAP44XX_GPMC_BASE	0x50000000

/*
 * Hardware Register Details
 */

/* Watchdog Timer */
#define WD_UNLOCK1		0xAAAA
#define WD_UNLOCK2		0x5555

/* GP Timer */
#define TCLR_ST			(0x1 << 0)
#define TCLR_AR			(0x1 << 1)
#define TCLR_PRE		(0x1 << 5)

/*
 * PRCM
 */

/* PRM */
#define PRM_BASE		0x4A306000
#define PRM_DEVICE_BASE		(PRM_BASE + 0x1B00)

#define PRM_RSTCTRL		PRM_DEVICE_BASE
#define PRM_RSTCTRL_RESET	0x01

#ifndef __ASSEMBLY__

struct s32ktimer {
	unsigned char res[0x10];
	unsigned int s32k_cr;	/* 0x10 */
};

#endif /* __ASSEMBLY__ */

/*
 * Non-secure SRAM Addresses
 * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
 * at 0x40304000(EMU base) so that our code works for both EMU and GP
 */
#define NON_SECURE_SRAM_START	0x40304000
#define NON_SECURE_SRAM_END	0x4030E000	/* Not inclusive */
/* base address for indirect vectors (internal boot mode) */
#define SRAM_ROM_VECT_BASE	0x4030D000
/* Temporary SRAM stack used while low level init is done */
#define LOW_LEVEL_SRAM_STACK		NON_SECURE_SRAM_END
#define SRAM_SCRATCH_SPACE_ADDR		NON_SECURE_SRAM_START
/* SRAM scratch space entries */
#define OMAP4_SRAM_SCRATCH_OMAP4_REV	SRAM_SCRATCH_SPACE_ADDR
#define OMAP4_SRAM_SCRATCH_EMIF_SIZE	(SRAM_SCRATCH_SPACE_ADDR + 0x4)
#define OMAP4_SRAM_SCRATCH_EMIF_T_NUM	(SRAM_SCRATCH_SPACE_ADDR + 0xC)
#define OMAP4_SRAM_SCRATCH_EMIF_T_DEN	(SRAM_SCRATCH_SPACE_ADDR + 0x10)
#define OMAP4_SRAM_SCRATCH_SPACE_END	(SRAM_SCRATCH_SPACE_ADDR + 0x14)

/* Silicon revisions */
#define OMAP4430_SILICON_ID_INVALID	0xFFFFFFFF
#define OMAP4430_ES1_0	0x44300100
#define OMAP4430_ES2_0	0x44300200
#define OMAP4430_ES2_1	0x44300210
#define OMAP4430_ES2_2	0x44300220
#define OMAP4430_ES2_3	0x44300230
#define OMAP4460_ES1_0	0x44600100

/* ROM code defines */
/* Boot device */
#define BOOT_DEVICE_MASK	0xFF
#define BOOT_DEVICE_OFFSET	0x8
#define DEV_DESC_PTR_OFFSET	0x4
#define DEV_DATA_PTR_OFFSET	0x18
#define BOOT_MODE_OFFSET	0x8

#endif
Commit	Line	Data
d34efc76 SS	1	/*
	2	* (C) Copyright 2010
	3	* Texas Instruments, <www.ti.com>
	4	*
	5	* Authors:
	6	* Aneesh V <aneesh@ti.com>
	7	*
	8	* Derived from OMAP3 work by
	9	* Richard Woodruff <r-woodruff2@ti.com>
	10	* Syed Mohammed Khasim <x0khasim@ti.com>
	11	*
	12	* See file CREDITS for list of people who contributed to this
	13	* project.
	14	*
	15	* This program is free software; you can redistribute it and/or
	16	* modify it under the terms of the GNU General Public License as
	17	* published by the Free Software Foundation; either version 2 of
	18	* the License, or (at your option) any later version.
	19	*
	20	* This program is distributed in the hope that it will be useful,
	21	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	22	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	23	* GNU General Public License for more details.
	24	*
	25	* You should have received a copy of the GNU General Public License
	26	* along with this program; if not, write to the Free Software
	27	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	28	* MA 02111-1307 USA
	29	*/
	30
	31	#ifndef _OMAP4_H_
	32	#define _OMAP4_H_
	33
	34	#if !(defined(__KERNEL_STRICT_NAMES) \|\| defined(__ASSEMBLY__))
	35	#include <asm/types.h>
	36	#endif /* !(__KERNEL_STRICT_NAMES \|\| __ASSEMBLY__) */
	37
	38	/*
	39	* L4 Peripherals - L4 Wakeup and L4 Core now
	40	*/
	41	#define OMAP44XX_L4_CORE_BASE 0x4A000000
	42	#define OMAP44XX_L4_WKUP_BASE 0x4A300000
	43	#define OMAP44XX_L4_PER_BASE 0x48000000
	44
7ca3f9c5 A	45	#define OMAP44XX_DRAM_ADDR_SPACE_START 0x80000000
	46	#define OMAP44XX_DRAM_ADDR_SPACE_END 0xD0000000
	47
	48
d34efc76 SS	49	/* CONTROL */
d34efc76 SS	50	#define CTRL_BASE (OMAP44XX_L4_CORE_BASE + 0x2000)
2ad853c3 SS	51	#define CONTROL_PADCONF_CORE (OMAP44XX_L4_CORE_BASE + 0x100000)
2ad853c3 SS	52	#define CONTROL_PADCONF_WKUP (OMAP44XX_L4_CORE_BASE + 0x31E000)
d34efc76	53
2ae610f0 A	54	/* LPDDR2 IO regs */
	55	#define LPDDR2_IO_REGS_BASE 0x4A100638
	56
	57	#define CONTROL_EFUSE_2 0x4A100704
	58
ad577c8a A	59	/* CONTROL_ID_CODE */
	60	#define CONTROL_ID_CODE 0x4A002204
	61
	62	#define OMAP4_CONTROL_ID_CODE_ES1_0 0x0B85202F
	63	#define OMAP4_CONTROL_ID_CODE_ES2_0 0x1B85202F
	64	#define OMAP4_CONTROL_ID_CODE_ES2_1 0x3B95C02F
	65	#define OMAP4_CONTROL_ID_CODE_ES2_2 0x4B95C02F
	66	#define OMAP4_CONTROL_ID_CODE_ES2_3 0x6B95C02F
	67
d34efc76 SS	68	/* UART */
	69	#define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000)
	70	#define UART2_BASE (OMAP44XX_L4_PER_BASE + 0x6c000)
	71	#define UART3_BASE (OMAP44XX_L4_PER_BASE + 0x20000)
	72
	73	/* General Purpose Timers */
	74	#define GPT1_BASE (OMAP44XX_L4_WKUP_BASE + 0x18000)
	75	#define GPT2_BASE (OMAP44XX_L4_PER_BASE + 0x32000)
	76	#define GPT3_BASE (OMAP44XX_L4_PER_BASE + 0x34000)
	77
	78	/* Watchdog Timer2 - MPU watchdog */
	79	#define WDT2_BASE (OMAP44XX_L4_WKUP_BASE + 0x14000)
	80
	81	/* 32KTIMER */
	82	#define SYNC_32KTIMER_BASE (OMAP44XX_L4_WKUP_BASE + 0x4000)
	83
	84	/* GPMC */
27952014	85	#define OMAP44XX_GPMC_BASE 0x50000000
d34efc76 SS	86
	87	/*
	88	* Hardware Register Details
	89	*/
	90
	91	/* Watchdog Timer */
	92	#define WD_UNLOCK1 0xAAAA
	93	#define WD_UNLOCK2 0x5555
	94
	95	/* GP Timer */
	96	#define TCLR_ST (0x1 << 0)
	97	#define TCLR_AR (0x1 << 1)
	98	#define TCLR_PRE (0x1 << 5)
	99
	100	/*
	101	* PRCM
	102	*/
	103
	104	/* PRM */
	105	#define PRM_BASE 0x4A306000
	106	#define PRM_DEVICE_BASE (PRM_BASE + 0x1B00)
	107
	108	#define PRM_RSTCTRL PRM_DEVICE_BASE
543431b6	109	#define PRM_RSTCTRL_RESET 0x01
d34efc76 SS	110
	111	#ifndef __ASSEMBLY__
	112
	113	struct s32ktimer {
	114	unsigned char res[0x10];
	115	unsigned int s32k_cr; /* 0x10 */
	116	};
	117
	118	#endif /* __ASSEMBLY__ */
	119
	120	/*
	121	* Non-secure SRAM Addresses
	122	* Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
	123	* at 0x40304000(EMU base) so that our code works for both EMU and GP
	124	*/
	125	#define NON_SECURE_SRAM_START 0x40304000
	126	#define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */
	127	/* base address for indirect vectors (internal boot mode) */
	128	#define SRAM_ROM_VECT_BASE 0x4030D000
	129	/* Temporary SRAM stack used while low level init is done */
ad577c8a A	130	#define LOW_LEVEL_SRAM_STACK NON_SECURE_SRAM_END
	131	#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START
	132	/* SRAM scratch space entries */
	133	#define OMAP4_SRAM_SCRATCH_OMAP4_REV SRAM_SCRATCH_SPACE_ADDR
095aea29 A	134	#define OMAP4_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4)
	135	#define OMAP4_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC)
	136	#define OMAP4_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10)
	137	#define OMAP4_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x14)
ad577c8a A	138
	139	/* Silicon revisions */
	140	#define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF
	141	#define OMAP4430_ES1_0 0x44300100
	142	#define OMAP4430_ES2_0 0x44300200
	143	#define OMAP4430_ES2_1 0x44300210
	144	#define OMAP4430_ES2_2 0x44300220
	145	#define OMAP4430_ES2_3 0x44300230
5ab12a9e	146	#define OMAP4460_ES1_0 0x44600100
d34efc76	147
8cf686e1 A	148	/* ROM code defines */
	149	/* Boot device */
	150	#define BOOT_DEVICE_MASK 0xFF
	151	#define BOOT_DEVICE_OFFSET 0x8
	152	#define DEV_DESC_PTR_OFFSET 0x4
	153	#define DEV_DATA_PTR_OFFSET 0x18
	154	#define BOOT_MODE_OFFSET 0x8
	155
d34efc76	156	#endif