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d34efc76 SS |
1 | /* |
2 | * (C) Copyright 2010 | |
3 | * Texas Instruments, <www.ti.com> | |
4 | * | |
5 | * Authors: | |
6 | * Aneesh V <aneesh@ti.com> | |
7 | * | |
8 | * Derived from OMAP3 work by | |
9 | * Richard Woodruff <r-woodruff2@ti.com> | |
10 | * Syed Mohammed Khasim <x0khasim@ti.com> | |
11 | * | |
12 | * See file CREDITS for list of people who contributed to this | |
13 | * project. | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License as | |
17 | * published by the Free Software Foundation; either version 2 of | |
18 | * the License, or (at your option) any later version. | |
19 | * | |
20 | * This program is distributed in the hope that it will be useful, | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | * | |
25 | * You should have received a copy of the GNU General Public License | |
26 | * along with this program; if not, write to the Free Software | |
27 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
28 | * MA 02111-1307 USA | |
29 | */ | |
30 | ||
31 | #ifndef _OMAP4_H_ | |
32 | #define _OMAP4_H_ | |
33 | ||
34 | #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) | |
35 | #include <asm/types.h> | |
36 | #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ | |
37 | ||
38 | /* | |
39 | * L4 Peripherals - L4 Wakeup and L4 Core now | |
40 | */ | |
41 | #define OMAP44XX_L4_CORE_BASE 0x4A000000 | |
42 | #define OMAP44XX_L4_WKUP_BASE 0x4A300000 | |
43 | #define OMAP44XX_L4_PER_BASE 0x48000000 | |
44 | ||
7ca3f9c5 A |
45 | #define OMAP44XX_DRAM_ADDR_SPACE_START 0x80000000 |
46 | #define OMAP44XX_DRAM_ADDR_SPACE_END 0xD0000000 | |
47 | ||
48 | ||
d34efc76 SS |
49 | /* CONTROL */ |
50 | #define CTRL_BASE (OMAP44XX_L4_CORE_BASE + 0x2000) | |
2ad853c3 SS |
51 | #define CONTROL_PADCONF_CORE (OMAP44XX_L4_CORE_BASE + 0x100000) |
52 | #define CONTROL_PADCONF_WKUP (OMAP44XX_L4_CORE_BASE + 0x31E000) | |
d34efc76 | 53 | |
2ae610f0 A |
54 | /* LPDDR2 IO regs */ |
55 | #define LPDDR2_IO_REGS_BASE 0x4A100638 | |
56 | ||
57 | #define CONTROL_EFUSE_2 0x4A100704 | |
58 | ||
ad577c8a A |
59 | /* CONTROL_ID_CODE */ |
60 | #define CONTROL_ID_CODE 0x4A002204 | |
61 | ||
62 | #define OMAP4_CONTROL_ID_CODE_ES1_0 0x0B85202F | |
63 | #define OMAP4_CONTROL_ID_CODE_ES2_0 0x1B85202F | |
64 | #define OMAP4_CONTROL_ID_CODE_ES2_1 0x3B95C02F | |
65 | #define OMAP4_CONTROL_ID_CODE_ES2_2 0x4B95C02F | |
66 | #define OMAP4_CONTROL_ID_CODE_ES2_3 0x6B95C02F | |
67 | ||
d34efc76 SS |
68 | /* UART */ |
69 | #define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000) | |
70 | #define UART2_BASE (OMAP44XX_L4_PER_BASE + 0x6c000) | |
71 | #define UART3_BASE (OMAP44XX_L4_PER_BASE + 0x20000) | |
72 | ||
73 | /* General Purpose Timers */ | |
74 | #define GPT1_BASE (OMAP44XX_L4_WKUP_BASE + 0x18000) | |
75 | #define GPT2_BASE (OMAP44XX_L4_PER_BASE + 0x32000) | |
76 | #define GPT3_BASE (OMAP44XX_L4_PER_BASE + 0x34000) | |
77 | ||
78 | /* Watchdog Timer2 - MPU watchdog */ | |
79 | #define WDT2_BASE (OMAP44XX_L4_WKUP_BASE + 0x14000) | |
80 | ||
81 | /* 32KTIMER */ | |
82 | #define SYNC_32KTIMER_BASE (OMAP44XX_L4_WKUP_BASE + 0x4000) | |
83 | ||
84 | /* GPMC */ | |
27952014 | 85 | #define OMAP44XX_GPMC_BASE 0x50000000 |
d34efc76 | 86 | |
7ca3f9c5 A |
87 | /* DMM */ |
88 | #define OMAP44XX_DMM_BASE 0x4E000000 | |
89 | #define DMM_LISA_MAP_BASE (OMAP44XX_DMM_BASE + 0x40) | |
90 | #define DMM_LISA_MAP_SYS_SIZE_MASK (7 << 20) | |
91 | #define DMM_LISA_MAP_SYS_SIZE_SHIFT 20 | |
92 | #define DMM_LISA_MAP_SYS_ADDR_MASK (0xFF << 24) | |
d34efc76 SS |
93 | /* |
94 | * Hardware Register Details | |
95 | */ | |
96 | ||
97 | /* Watchdog Timer */ | |
98 | #define WD_UNLOCK1 0xAAAA | |
99 | #define WD_UNLOCK2 0x5555 | |
100 | ||
101 | /* GP Timer */ | |
102 | #define TCLR_ST (0x1 << 0) | |
103 | #define TCLR_AR (0x1 << 1) | |
104 | #define TCLR_PRE (0x1 << 5) | |
105 | ||
106 | /* | |
107 | * PRCM | |
108 | */ | |
109 | ||
110 | /* PRM */ | |
111 | #define PRM_BASE 0x4A306000 | |
112 | #define PRM_DEVICE_BASE (PRM_BASE + 0x1B00) | |
113 | ||
114 | #define PRM_RSTCTRL PRM_DEVICE_BASE | |
543431b6 | 115 | #define PRM_RSTCTRL_RESET 0x01 |
d34efc76 SS |
116 | |
117 | #ifndef __ASSEMBLY__ | |
118 | ||
119 | struct s32ktimer { | |
120 | unsigned char res[0x10]; | |
121 | unsigned int s32k_cr; /* 0x10 */ | |
122 | }; | |
123 | ||
124 | #endif /* __ASSEMBLY__ */ | |
125 | ||
126 | /* | |
127 | * Non-secure SRAM Addresses | |
128 | * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE | |
129 | * at 0x40304000(EMU base) so that our code works for both EMU and GP | |
130 | */ | |
131 | #define NON_SECURE_SRAM_START 0x40304000 | |
132 | #define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */ | |
133 | /* base address for indirect vectors (internal boot mode) */ | |
134 | #define SRAM_ROM_VECT_BASE 0x4030D000 | |
135 | /* Temporary SRAM stack used while low level init is done */ | |
ad577c8a A |
136 | #define LOW_LEVEL_SRAM_STACK NON_SECURE_SRAM_END |
137 | #define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START | |
138 | /* SRAM scratch space entries */ | |
139 | #define OMAP4_SRAM_SCRATCH_OMAP4_REV SRAM_SCRATCH_SPACE_ADDR | |
140 | ||
141 | /* Silicon revisions */ | |
142 | #define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF | |
143 | #define OMAP4430_ES1_0 0x44300100 | |
144 | #define OMAP4430_ES2_0 0x44300200 | |
145 | #define OMAP4430_ES2_1 0x44300210 | |
146 | #define OMAP4430_ES2_2 0x44300220 | |
147 | #define OMAP4430_ES2_3 0x44300230 | |
d34efc76 SS |
148 | |
149 | #endif |