projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 2e5ba489 S |
1 | /* |
| 2 | * (C) Copyright 2010 | |
| 3 | * Texas Instruments, <www.ti.com> | |
| 4 | * | |
| 5 | * Aneesh V <aneesh@ti.com> | |
| 6 | * Sricharan R <r.sricharan@ti.com> | |
| 7 | * | |
| 1a459660 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
| 2e5ba489 S |
9 | */ |
| 10 | #ifndef _CLOCKS_OMAP5_H_ | |
| 11 | #define _CLOCKS_OMAP5_H_ | |
| 12 | #include <common.h> | |
| 01b753ff | 13 | #include <asm/omap_common.h> |
| 2e5ba489 S |
14 | |
| 15 | /* | |
| 16 | * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per | |
| 17 | * loop, allow for a minimum of 2 ms wait (in reality the wait will be | |
| 18 | * much more than that) | |
| 19 | */ | |
| 20 | #define LDELAY 1000000 | |
| 21 | ||
| 753bae8c LV |
22 | /* CM_DLL_CTRL */ |
| 23 | #define CM_DLL_CTRL_OVERRIDE_SHIFT 0 | |
| 24 | #define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0) | |
| 25 | #define CM_DLL_CTRL_NO_OVERRIDE 0 | |
| 26 | ||
| 2e5ba489 S |
27 | /* CM_CLKMODE_DPLL */ |
| 28 | #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 | |
| 29 | #define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) | |
| 30 | #define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10 | |
| 31 | #define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10) | |
| 32 | #define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9 | |
| 33 | #define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9) | |
| 34 | #define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8 | |
| 35 | #define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8) | |
| 36 | #define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5 | |
| 37 | #define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5) | |
| 38 | #define CM_CLKMODE_DPLL_EN_SHIFT 0 | |
| 39 | #define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0) | |
| 40 | ||
| 41 | #define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0 | |
| 42 | #define CM_CLKMODE_DPLL_DPLL_EN_MASK 7 | |
| 43 | ||
| 44 | #define DPLL_EN_STOP 1 | |
| 45 | #define DPLL_EN_MN_BYPASS 4 | |
| 46 | #define DPLL_EN_LOW_POWER_BYPASS 5 | |
| 47 | #define DPLL_EN_FAST_RELOCK_BYPASS 6 | |
| 48 | #define DPLL_EN_LOCK 7 | |
| 49 | ||
| 50 | /* CM_IDLEST_DPLL fields */ | |
| 51 | #define ST_DPLL_CLK_MASK 1 | |
| 52 | ||
| 5f14d919 S |
53 | /* SGX */ |
| 54 | #define CLKSEL_GPU_HYD_GCLK_MASK (1 << 25) | |
| 55 | #define CLKSEL_GPU_CORE_GCLK_MASK (1 << 24) | |
| 56 | ||
| 2e5ba489 S |
57 | /* CM_CLKSEL_DPLL */ |
| 58 | #define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24 | |
| 59 | #define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24) | |
| 60 | #define CM_CLKSEL_DPLL_M_SHIFT 8 | |
| 61 | #define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8) | |
| 62 | #define CM_CLKSEL_DPLL_N_SHIFT 0 | |
| 63 | #define CM_CLKSEL_DPLL_N_MASK 0x7F | |
| 64 | #define CM_CLKSEL_DCC_EN_SHIFT 22 | |
| 65 | #define CM_CLKSEL_DCC_EN_MASK (1 << 22) | |
| 66 | ||
| 2e5ba489 | 67 | /* CM_SYS_CLKSEL */ |
| 97405d84 | 68 | #define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 |
| 2e5ba489 S |
69 | |
| 70 | /* CM_CLKSEL_CORE */ | |
| 71 | #define CLKSEL_CORE_SHIFT 0 | |
| 72 | #define CLKSEL_L3_SHIFT 4 | |
| 73 | #define CLKSEL_L4_SHIFT 8 | |
| 74 | ||
| 75 | #define CLKSEL_CORE_X2_DIV_1 0 | |
| 76 | #define CLKSEL_L3_CORE_DIV_2 1 | |
| 77 | #define CLKSEL_L4_L3_DIV_2 1 | |
| 78 | ||
| 79 | /* CM_ABE_PLL_REF_CLKSEL */ | |
| 80 | #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0 | |
| 81 | #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK 1 | |
| 82 | #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0 | |
| 83 | #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1 | |
| 84 | ||
| 97405d84 LV |
85 | /* CM_CLKSEL_ABE_PLL_SYS */ |
| 86 | #define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_SHIFT 0 | |
| 87 | #define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK 1 | |
| 88 | #define CM_ABE_PLL_SYS_CLKSEL_SYSCLK1 0 | |
| 89 | #define CM_ABE_PLL_SYS_CLKSEL_SYSCLK2 1 | |
| 90 | ||
| 2e5ba489 S |
91 | /* CM_BYPCLK_DPLL_IVA */ |
| 92 | #define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0 | |
| 93 | #define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3 | |
| 94 | ||
| 95 | #define DPLL_IVA_CLKSEL_CORE_X2_DIV_2 1 | |
| 96 | ||
| 97 | /* CM_SHADOW_FREQ_CONFIG1 */ | |
| 98 | #define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1 | |
| 99 | #define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4 | |
| 100 | #define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8 | |
| 101 | ||
| 102 | #define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8 | |
| 103 | #define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8) | |
| 104 | ||
| 105 | #define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11 | |
| 106 | #define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11) | |
| 107 | ||
| 108 | /*CM_<clock_domain>__CLKCTRL */ | |
| 109 | #define CD_CLKCTRL_CLKTRCTRL_SHIFT 0 | |
| 110 | #define CD_CLKCTRL_CLKTRCTRL_MASK 3 | |
| 111 | ||
| 112 | #define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0 | |
| 113 | #define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1 | |
| 114 | #define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2 | |
| 115 | #define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3 | |
| 116 | ||
| 117 | ||
| 118 | /* CM_<clock_domain>_<module>_CLKCTRL */ | |
| 119 | #define MODULE_CLKCTRL_MODULEMODE_SHIFT 0 | |
| 120 | #define MODULE_CLKCTRL_MODULEMODE_MASK 3 | |
| 121 | #define MODULE_CLKCTRL_IDLEST_SHIFT 16 | |
| 122 | #define MODULE_CLKCTRL_IDLEST_MASK (3 << 16) | |
| 123 | ||
| 124 | #define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0 | |
| 125 | #define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1 | |
| 126 | #define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2 | |
| 127 | ||
| 128 | #define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0 | |
| 129 | #define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1 | |
| 130 | #define MODULE_CLKCTRL_IDLEST_IDLE 2 | |
| 131 | #define MODULE_CLKCTRL_IDLEST_DISABLED 3 | |
| 132 | ||
| 133 | /* CM_L4PER_GPIO4_CLKCTRL */ | |
| 134 | #define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8) | |
| 135 | ||
| 136 | /* CM_L3INIT_HSMMCn_CLKCTRL */ | |
| 137 | #define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24) | |
| 5f14d919 | 138 | #define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (1 << 25) |
| 2e5ba489 S |
139 | |
| 140 | /* CM_WKUP_GPTIMER1_CLKCTRL */ | |
| 141 | #define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24) | |
| 142 | ||
| 143 | /* CM_CAM_ISS_CLKCTRL */ | |
| 144 | #define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8) | |
| 145 | ||
| 146 | /* CM_DSS_DSS_CLKCTRL */ | |
| 147 | #define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00 | |
| 148 | ||
| 149 | /* CM_L3INIT_USBPHY_CLKCTRL */ | |
| 150 | #define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK 8 | |
| 151 | ||
| 152 | /* CM_MPU_MPU_CLKCTRL */ | |
| 153 | #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24 | |
| 47abc3df S |
154 | #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (3 << 24) |
| 155 | #define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 26 | |
| 156 | #define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 26) | |
| 2e5ba489 | 157 | |
| 5f14d919 S |
158 | /* CM_WKUPAON_SCRM_CLKCTRL */ |
| 159 | #define OPTFCLKEN_SCRM_PER_SHIFT 9 | |
| 160 | #define OPTFCLKEN_SCRM_PER_MASK (1 << 9) | |
| 161 | #define OPTFCLKEN_SCRM_CORE_SHIFT 8 | |
| 162 | #define OPTFCLKEN_SCRM_CORE_MASK (1 << 8) | |
| 163 | ||
| d4d986ee LV |
164 | /* CM_COREAON_IO_SRCOMP_CLKCTRL */ |
| 165 | #define OPTFCLKEN_SRCOMP_FCLK_SHIFT 8 | |
| 166 | #define OPTFCLKEN_SRCOMP_FCLK_MASK (1 << 8) | |
| 167 | ||
| 0b1b60c7 LV |
168 | /* PRM_RSTTIME */ |
| 169 | #define RSTTIME1_SHIFT 0 | |
| 170 | #define RSTTIME1_MASK (0x3ff << 0) | |
| 171 | ||
| 2e5ba489 | 172 | /* Clock frequencies */ |
| 2e5ba489 | 173 | #define OMAP_SYS_CLK_IND_38_4_MHZ 6 |
| 2e5ba489 | 174 | |
| 2e5ba489 S |
175 | /* PRM_VC_VAL_BYPASS */ |
| 176 | #define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400 | |
| 177 | ||
| 2e5ba489 S |
178 | /* SMPS */ |
| 179 | #define SMPS_I2C_SLAVE_ADDR 0x12 | |
| 8de17f46 S |
180 | #define SMPS_REG_ADDR_12_MPU 0x23 |
| 181 | #define SMPS_REG_ADDR_45_IVA 0x2B | |
| 182 | #define SMPS_REG_ADDR_8_CORE 0x37 | |
| 2e5ba489 | 183 | |
| 8de17f46 | 184 | /* PALMAS VOLTAGE SETTINGS in mv for OPP_NOMINAL */ |
| 47abc3df S |
185 | /* ES1.0 settings */ |
| 186 | #define VDD_MPU 1040 | |
| 187 | #define VDD_MM 1040 | |
| 8de17f46 | 188 | #define VDD_CORE 1040 |
| 47abc3df S |
189 | |
| 190 | #define VDD_MPU_LOW 890 | |
| 191 | #define VDD_MM_LOW 890 | |
| 192 | #define VDD_CORE_LOW 890 | |
| 193 | ||
| 194 | /* ES2.0 settings */ | |
| 195 | #define VDD_MPU_ES2 1060 | |
| 196 | #define VDD_MM_ES2 1025 | |
| 197 | #define VDD_CORE_ES2 1040 | |
| 198 | ||
| 199 | #define VDD_MPU_ES2_HIGH 1250 | |
| 200 | #define VDD_MM_ES2_OD 1120 | |
| 201 | ||
| 202 | #define VDD_MPU_ES2_LOW 880 | |
| 203 | #define VDD_MM_ES2_LOW 880 | |
| 8de17f46 | 204 | |
| 63fc0c77 LV |
205 | /* TPS659038 Voltage settings in mv for OPP_NOMINAL */ |
| 206 | #define VDD_MPU_DRA752 1090 | |
| 207 | #define VDD_EVE_DRA752 1060 | |
| 208 | #define VDD_GPU_DRA752 1060 | |
| 209 | #define VDD_CORE_DRA752 1030 | |
| 210 | #define VDD_IVA_DRA752 1060 | |
| 211 | ||
| 18c9d55a NM |
212 | /* Efuse register offsets for DRA7xx platform */ |
| 213 | #define DRA752_EFUSE_BASE 0x4A002000 | |
| 214 | #define DRA752_EFUSE_REGBITS 16 | |
| 215 | /* STD_FUSE_OPP_VMIN_IVA_2 */ | |
| 216 | #define STD_FUSE_OPP_VMIN_IVA_NOM (DRA752_EFUSE_BASE + 0x05CC) | |
| 217 | /* STD_FUSE_OPP_VMIN_IVA_3 */ | |
| 218 | #define STD_FUSE_OPP_VMIN_IVA_OD (DRA752_EFUSE_BASE + 0x05D0) | |
| 219 | /* STD_FUSE_OPP_VMIN_IVA_4 */ | |
| 220 | #define STD_FUSE_OPP_VMIN_IVA_HIGH (DRA752_EFUSE_BASE + 0x05D4) | |
| 221 | /* STD_FUSE_OPP_VMIN_DSPEVE_2 */ | |
| 222 | #define STD_FUSE_OPP_VMIN_DSPEVE_NOM (DRA752_EFUSE_BASE + 0x05E0) | |
| 223 | /* STD_FUSE_OPP_VMIN_DSPEVE_3 */ | |
| 224 | #define STD_FUSE_OPP_VMIN_DSPEVE_OD (DRA752_EFUSE_BASE + 0x05E4) | |
| 225 | /* STD_FUSE_OPP_VMIN_DSPEVE_4 */ | |
| 226 | #define STD_FUSE_OPP_VMIN_DSPEVE_HIGH (DRA752_EFUSE_BASE + 0x05E8) | |
| 227 | /* STD_FUSE_OPP_VMIN_CORE_2 */ | |
| 228 | #define STD_FUSE_OPP_VMIN_CORE_NOM (DRA752_EFUSE_BASE + 0x05F4) | |
| 229 | /* STD_FUSE_OPP_VMIN_GPU_2 */ | |
| 230 | #define STD_FUSE_OPP_VMIN_GPU_NOM (DRA752_EFUSE_BASE + 0x1B08) | |
| 231 | /* STD_FUSE_OPP_VMIN_GPU_3 */ | |
| 232 | #define STD_FUSE_OPP_VMIN_GPU_OD (DRA752_EFUSE_BASE + 0x1B0C) | |
| 233 | /* STD_FUSE_OPP_VMIN_GPU_4 */ | |
| 234 | #define STD_FUSE_OPP_VMIN_GPU_HIGH (DRA752_EFUSE_BASE + 0x1B10) | |
| 235 | /* STD_FUSE_OPP_VMIN_MPU_2 */ | |
| 236 | #define STD_FUSE_OPP_VMIN_MPU_NOM (DRA752_EFUSE_BASE + 0x1B20) | |
| 237 | /* STD_FUSE_OPP_VMIN_MPU_3 */ | |
| 238 | #define STD_FUSE_OPP_VMIN_MPU_OD (DRA752_EFUSE_BASE + 0x1B24) | |
| 239 | /* STD_FUSE_OPP_VMIN_MPU_4 */ | |
| 240 | #define STD_FUSE_OPP_VMIN_MPU_HIGH (DRA752_EFUSE_BASE + 0x1B28) | |
| 241 | ||
| 8de17f46 S |
242 | /* Standard offset is 0.5v expressed in uv */ |
| 243 | #define PALMAS_SMPS_BASE_VOLT_UV 500000 | |
| 2e5ba489 | 244 | |
| 63fc0c77 LV |
245 | /* TPS659038 */ |
| 246 | #define TPS659038_I2C_SLAVE_ADDR 0x58 | |
| 247 | #define TPS659038_REG_ADDR_SMPS12_MPU 0x23 | |
| 248 | #define TPS659038_REG_ADDR_SMPS45_EVE 0x2B | |
| 249 | #define TPS659038_REG_ADDR_SMPS6_GPU 0x2F | |
| 250 | #define TPS659038_REG_ADDR_SMPS7_CORE 0x33 | |
| 251 | #define TPS659038_REG_ADDR_SMPS8_IVA 0x37 | |
| 252 | ||
| 2e5ba489 S |
253 | /* TPS */ |
| 254 | #define TPS62361_I2C_SLAVE_ADDR 0x60 | |
| 255 | #define TPS62361_REG_ADDR_SET0 0x0 | |
| 256 | #define TPS62361_REG_ADDR_SET1 0x1 | |
| 257 | #define TPS62361_REG_ADDR_SET2 0x2 | |
| 258 | #define TPS62361_REG_ADDR_SET3 0x3 | |
| 259 | #define TPS62361_REG_ADDR_CTRL 0x4 | |
| 260 | #define TPS62361_REG_ADDR_TEMP 0x5 | |
| 261 | #define TPS62361_REG_ADDR_RMP_CTRL 0x6 | |
| 262 | #define TPS62361_REG_ADDR_CHIP_ID 0x8 | |
| 263 | #define TPS62361_REG_ADDR_CHIP_ID_2 0x9 | |
| 264 | ||
| 265 | #define TPS62361_BASE_VOLT_MV 500 | |
| 266 | #define TPS62361_VSEL0_GPIO 7 | |
| 267 | ||
| ee28edac LP |
268 | /* Defines for DPLL setup */ |
| 269 | #define DPLL_LOCKED_FREQ_TOLERANCE_0 0 | |
| 270 | #define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ 500 | |
| 271 | #define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ 1000 | |
| 272 | ||
| 2e5ba489 S |
273 | #define DPLL_NO_LOCK 0 |
| 274 | #define DPLL_LOCK 1 | |
| 275 | ||
| 0b1b60c7 LV |
276 | /* |
| 277 | * MAX value for PRM_RSTTIME[9:0]RSTTIME1 stored is 0x3ff. | |
| 278 | * 0x3ff is in the no of FUNC_32K_CLK cycles. Converting cycles | |
| 279 | * into microsec and passing the value. | |
| 280 | */ | |
| 281 | #define CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC 31219 | |
| f9b814a8 S |
282 | |
| 283 | #ifdef CONFIG_DRA7XX | |
| 284 | #define V_OSCK 20000000 /* Clock output from T2 */ | |
| 285 | #else | |
| 286 | #define V_OSCK 19200000 /* Clock output from T2 */ | |
| 287 | #endif | |
| 288 | ||
| 289 | #define V_SCLK V_OSCK | |
| ee28edac LP |
290 | |
| 291 | /* AUXCLKx reg fields */ | |
| 292 | #define AUXCLK_ENABLE_MASK (1 << 8) | |
| 293 | #define AUXCLK_SRCSELECT_SHIFT 1 | |
| 294 | #define AUXCLK_SRCSELECT_MASK (3 << 1) | |
| 295 | #define AUXCLK_CLKDIV_SHIFT 16 | |
| 296 | #define AUXCLK_CLKDIV_MASK (0xF << 16) | |
| 297 | ||
| 298 | #define AUXCLK_SRCSELECT_SYS_CLK 0 | |
| 299 | #define AUXCLK_SRCSELECT_CORE_DPLL 1 | |
| 300 | #define AUXCLK_SRCSELECT_PER_DPLL 2 | |
| 301 | #define AUXCLK_SRCSELECT_ALTERNATE 3 | |
| 302 | ||
| 2e5ba489 | 303 | #endif /* _CLOCKS_OMAP5_H_ */ |