[people/ms/u-boot.git] / arch / arm / include / asm / arch-omap5 / clock.h

/*
 * (C) Copyright 2010
 * Texas Instruments, <www.ti.com>
 *
 *	Aneesh V <aneesh@ti.com>
 *	Sricharan R <r.sricharan@ti.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#ifndef _CLOCKS_OMAP5_H_
#define _CLOCKS_OMAP5_H_
#include <common.h>
#include <asm/omap_common.h>

/*
 * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per
 * loop, allow for a minimum of 2 ms wait (in reality the wait will be
 * much more than that)
 */
#define LDELAY		1000000

/* CM_DLL_CTRL */
#define CM_DLL_CTRL_OVERRIDE_SHIFT		0
#define CM_DLL_CTRL_OVERRIDE_MASK		(1 << 0)
#define CM_DLL_CTRL_NO_OVERRIDE			0

/* CM_CLKMODE_DPLL */
#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT		11
#define CM_CLKMODE_DPLL_REGM4XEN_MASK		(1 << 11)
#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT		10
#define CM_CLKMODE_DPLL_LPMODE_EN_MASK		(1 << 10)
#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT	9
#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK	(1 << 9)
#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT	8
#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK	(1 << 8)
#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT		5
#define CM_CLKMODE_DPLL_RAMP_RATE_MASK		(0x7 << 5)
#define CM_CLKMODE_DPLL_EN_SHIFT		0
#define CM_CLKMODE_DPLL_EN_MASK			(0x7 << 0)

#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT		0
#define CM_CLKMODE_DPLL_DPLL_EN_MASK		7

#define DPLL_EN_STOP			1
#define DPLL_EN_MN_BYPASS		4
#define DPLL_EN_LOW_POWER_BYPASS	5
#define DPLL_EN_FAST_RELOCK_BYPASS	6
#define DPLL_EN_LOCK			7

/* CM_IDLEST_DPLL fields */
#define ST_DPLL_CLK_MASK		1

/* SGX */
#define CLKSEL_GPU_HYD_GCLK_MASK		(1 << 25)
#define CLKSEL_GPU_CORE_GCLK_MASK		(1 << 24)

/* CM_CLKSEL_DPLL */
#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT	24
#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK		(0xFF << 24)
#define CM_CLKSEL_DPLL_M_SHIFT			8
#define CM_CLKSEL_DPLL_M_MASK			(0x7FF << 8)
#define CM_CLKSEL_DPLL_N_SHIFT			0
#define CM_CLKSEL_DPLL_N_MASK			0x7F
#define CM_CLKSEL_DCC_EN_SHIFT			22
#define CM_CLKSEL_DCC_EN_MASK			(1 << 22)

/* CM_SYS_CLKSEL */
#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK  7

/* CM_CLKSEL_CORE */
#define CLKSEL_CORE_SHIFT	0
#define CLKSEL_L3_SHIFT		4
#define CLKSEL_L4_SHIFT		8

#define CLKSEL_CORE_X2_DIV_1	0
#define CLKSEL_L3_CORE_DIV_2	1
#define CLKSEL_L4_L3_DIV_2	1

/* CM_ABE_PLL_REF_CLKSEL */
#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT	0
#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK	1
#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK	0
#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK	1

/* CM_CLKSEL_ABE_PLL_SYS */
#define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_SHIFT	0
#define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK	1
#define CM_ABE_PLL_SYS_CLKSEL_SYSCLK1		0
#define CM_ABE_PLL_SYS_CLKSEL_SYSCLK2		1

/* CM_BYPCLK_DPLL_IVA */
#define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT		0
#define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK		3

#define DPLL_IVA_CLKSEL_CORE_X2_DIV_2		1

/* CM_SHADOW_FREQ_CONFIG1 */
#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK	1
#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK	4
#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK	8

#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT	8
#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK	(7 << 8)

#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT	11
#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK		(0x1F << 11)

/*CM_<clock_domain>__CLKCTRL */
#define CD_CLKCTRL_CLKTRCTRL_SHIFT		0
#define CD_CLKCTRL_CLKTRCTRL_MASK		3

#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP		0
#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP		1
#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP		2
#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO		3


/* CM_<clock_domain>_<module>_CLKCTRL */
#define MODULE_CLKCTRL_MODULEMODE_SHIFT		0
#define MODULE_CLKCTRL_MODULEMODE_MASK		3
#define MODULE_CLKCTRL_IDLEST_SHIFT		16
#define MODULE_CLKCTRL_IDLEST_MASK		(3 << 16)

#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE		0
#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO		1
#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN	2

#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL	0
#define MODULE_CLKCTRL_IDLEST_TRANSITIONING	1
#define MODULE_CLKCTRL_IDLEST_IDLE		2
#define MODULE_CLKCTRL_IDLEST_DISABLED		3

/* CM_L4PER_GPIO4_CLKCTRL */
#define GPIO4_CLKCTRL_OPTFCLKEN_MASK		(1 << 8)

/* CM_L3INIT_HSMMCn_CLKCTRL */
#define HSMMC_CLKCTRL_CLKSEL_MASK		(1 << 24)
#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK		(1 << 25)

/* CM_L3INIT_SATA_CLKCTRL */
#define SATA_CLKCTRL_OPTFCLKEN_MASK		(1 << 8)

/* CM_WKUP_GPTIMER1_CLKCTRL */
#define GPTIMER1_CLKCTRL_CLKSEL_MASK		(1 << 24)

/* CM_CAM_ISS_CLKCTRL */
#define ISS_CLKCTRL_OPTFCLKEN_MASK		(1 << 8)

/* CM_DSS_DSS_CLKCTRL */
#define DSS_CLKCTRL_OPTFCLKEN_MASK		0xF00

/* CM_L3INIT_USBPHY_CLKCTRL */
#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK	8

/* CM_L3INIT_USB_HOST_HS_CLKCTRL */
#define OPTFCLKEN_FUNC48M_CLK			(1 << 15)
#define OPTFCLKEN_HSIC480M_P2_CLK		(1 << 14)
#define OPTFCLKEN_HSIC480M_P1_CLK		(1 << 13)
#define OPTFCLKEN_HSIC60M_P2_CLK		(1 << 12)
#define OPTFCLKEN_HSIC60M_P1_CLK		(1 << 11)
#define OPTFCLKEN_UTMI_P3_CLK			(1 << 10)
#define OPTFCLKEN_UTMI_P2_CLK			(1 << 9)
#define OPTFCLKEN_UTMI_P1_CLK			(1 << 8)
#define OPTFCLKEN_HSIC480M_P3_CLK		(1 << 7)
#define OPTFCLKEN_HSIC60M_P3_CLK		(1 << 6)

/* CM_L3INIT_USB_TLL_HS_CLKCTRL */
#define OPTFCLKEN_USB_CH0_CLK_ENABLE	(1 << 8)
#define OPTFCLKEN_USB_CH1_CLK_ENABLE	(1 << 9)
#define OPTFCLKEN_USB_CH2_CLK_ENABLE	(1 << 10)

/* CM_COREAON_USB_PHY_CORE_CLKCTRL */
#define USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K	(1 << 8)

/* CM_L3INIT_USB_OTG_SS_CLKCTRL */
#define OTG_SS_CLKCTRL_MODULEMODE_HW	(1 << 0)
#define OPTFCLKEN_REFCLK960M			(1 << 8)

/* CM_L3INIT_OCP2SCP1_CLKCTRL */
#define OCP2SCP1_CLKCTRL_MODULEMODE_HW	(1 << 0)

/* CM_MPU_MPU_CLKCTRL */
#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT	24
#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK	(3 << 24)
#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT	26
#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK	(1 << 26)

/* CM_WKUPAON_SCRM_CLKCTRL */
#define OPTFCLKEN_SCRM_PER_SHIFT		9
#define OPTFCLKEN_SCRM_PER_MASK			(1 << 9)
#define OPTFCLKEN_SCRM_CORE_SHIFT		8
#define OPTFCLKEN_SCRM_CORE_MASK		(1 << 8)

/* CM_COREAON_IO_SRCOMP_CLKCTRL */
#define OPTFCLKEN_SRCOMP_FCLK_SHIFT		8
#define OPTFCLKEN_SRCOMP_FCLK_MASK		(1 << 8)

/* PRM_RSTTIME */
#define RSTTIME1_SHIFT				0
#define RSTTIME1_MASK				(0x3ff << 0)

/* Clock frequencies */
#define OMAP_SYS_CLK_IND_38_4_MHZ	6

/* PRM_VC_VAL_BYPASS */
#define PRM_VC_I2C_CHANNEL_FREQ_KHZ	400

/* CTRL_CORE_SRCOMP_NORTH_SIDE */
#define USB2PHY_DISCHGDET	(1 << 29)
#define USB2PHY_AUTORESUME_EN (1 << 30)

/* SMPS */
#define SMPS_I2C_SLAVE_ADDR	0x12
#define SMPS_REG_ADDR_12_MPU	0x23
#define SMPS_REG_ADDR_45_IVA	0x2B
#define SMPS_REG_ADDR_8_CORE	0x37

/* PALMAS VOLTAGE SETTINGS in mv for OPP_NOMINAL */
/* ES1.0 settings */
#define VDD_MPU		1040
#define VDD_MM		1040
#define VDD_CORE	1040

#define VDD_MPU_LOW	890
#define VDD_MM_LOW	890
#define VDD_CORE_LOW	890

/* ES2.0 settings */
#define VDD_MPU_ES2	1060
#define VDD_MM_ES2	1025
#define VDD_CORE_ES2	1040

#define VDD_MPU_ES2_HIGH 1250
#define VDD_MM_ES2_OD  1120

#define VDD_MPU_ES2_LOW 880
#define VDD_MM_ES2_LOW 880

/* TPS659038 Voltage settings in mv for OPP_NOMINAL */
#define VDD_MPU_DRA752		1090
#define VDD_EVE_DRA752		1060
#define VDD_GPU_DRA752		1060
#define VDD_CORE_DRA752		1030
#define VDD_IVA_DRA752		1060

/* Efuse register offsets for DRA7xx platform */
#define DRA752_EFUSE_BASE	0x4A002000
#define DRA752_EFUSE_REGBITS	16
/* STD_FUSE_OPP_VMIN_IVA_2 */
#define STD_FUSE_OPP_VMIN_IVA_NOM	(DRA752_EFUSE_BASE + 0x05CC)
/* STD_FUSE_OPP_VMIN_IVA_3 */
#define STD_FUSE_OPP_VMIN_IVA_OD	(DRA752_EFUSE_BASE + 0x05D0)
/* STD_FUSE_OPP_VMIN_IVA_4 */
#define STD_FUSE_OPP_VMIN_IVA_HIGH	(DRA752_EFUSE_BASE + 0x05D4)
/* STD_FUSE_OPP_VMIN_DSPEVE_2 */
#define STD_FUSE_OPP_VMIN_DSPEVE_NOM	(DRA752_EFUSE_BASE + 0x05E0)
/* STD_FUSE_OPP_VMIN_DSPEVE_3 */
#define STD_FUSE_OPP_VMIN_DSPEVE_OD	(DRA752_EFUSE_BASE + 0x05E4)
/* STD_FUSE_OPP_VMIN_DSPEVE_4 */
#define STD_FUSE_OPP_VMIN_DSPEVE_HIGH	(DRA752_EFUSE_BASE + 0x05E8)
/* STD_FUSE_OPP_VMIN_CORE_2 */
#define STD_FUSE_OPP_VMIN_CORE_NOM	(DRA752_EFUSE_BASE + 0x05F4)
/* STD_FUSE_OPP_VMIN_GPU_2 */
#define STD_FUSE_OPP_VMIN_GPU_NOM	(DRA752_EFUSE_BASE + 0x1B08)
/* STD_FUSE_OPP_VMIN_GPU_3 */
#define STD_FUSE_OPP_VMIN_GPU_OD	(DRA752_EFUSE_BASE + 0x1B0C)
/* STD_FUSE_OPP_VMIN_GPU_4 */
#define STD_FUSE_OPP_VMIN_GPU_HIGH	(DRA752_EFUSE_BASE + 0x1B10)
/* STD_FUSE_OPP_VMIN_MPU_2 */
#define STD_FUSE_OPP_VMIN_MPU_NOM	(DRA752_EFUSE_BASE + 0x1B20)
/* STD_FUSE_OPP_VMIN_MPU_3 */
#define STD_FUSE_OPP_VMIN_MPU_OD	(DRA752_EFUSE_BASE + 0x1B24)
/* STD_FUSE_OPP_VMIN_MPU_4 */
#define STD_FUSE_OPP_VMIN_MPU_HIGH	(DRA752_EFUSE_BASE + 0x1B28)

/* Standard offset is 0.5v expressed in uv */
#define PALMAS_SMPS_BASE_VOLT_UV 500000

/* TPS659038 */
#define TPS659038_I2C_SLAVE_ADDR		0x58
#define TPS659038_REG_ADDR_SMPS12_MPU		0x23
#define TPS659038_REG_ADDR_SMPS45_EVE		0x2B
#define TPS659038_REG_ADDR_SMPS6_GPU		0x2F
#define TPS659038_REG_ADDR_SMPS7_CORE		0x33
#define TPS659038_REG_ADDR_SMPS8_IVA		0x37

/* TPS */
#define TPS62361_I2C_SLAVE_ADDR		0x60
#define TPS62361_REG_ADDR_SET0		0x0
#define TPS62361_REG_ADDR_SET1		0x1
#define TPS62361_REG_ADDR_SET2		0x2
#define TPS62361_REG_ADDR_SET3		0x3
#define TPS62361_REG_ADDR_CTRL		0x4
#define TPS62361_REG_ADDR_TEMP		0x5
#define TPS62361_REG_ADDR_RMP_CTRL	0x6
#define TPS62361_REG_ADDR_CHIP_ID	0x8
#define TPS62361_REG_ADDR_CHIP_ID_2	0x9

#define TPS62361_BASE_VOLT_MV	500
#define TPS62361_VSEL0_GPIO	7

/* Defines for DPLL setup */
#define DPLL_LOCKED_FREQ_TOLERANCE_0		0
#define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ	500
#define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ	1000

#define DPLL_NO_LOCK	0
#define DPLL_LOCK	1

/*
 * MAX value for PRM_RSTTIME[9:0]RSTTIME1 stored is 0x3ff.
 * 0x3ff is in the no of FUNC_32K_CLK cycles. Converting cycles
 * into microsec and passing the value.
 */
#define CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC	31219

#ifdef CONFIG_DRA7XX
#define V_OSCK			20000000	/* Clock output from T2 */
#else
#define V_OSCK			19200000	/* Clock output from T2 */
#endif

#define V_SCLK	V_OSCK

/* AUXCLKx reg fields */
#define AUXCLK_ENABLE_MASK		(1 << 8)
#define AUXCLK_SRCSELECT_SHIFT		1
#define AUXCLK_SRCSELECT_MASK		(3 << 1)
#define AUXCLK_CLKDIV_SHIFT		16
#define AUXCLK_CLKDIV_MASK		(0xF << 16)

#define AUXCLK_SRCSELECT_SYS_CLK	0
#define AUXCLK_SRCSELECT_CORE_DPLL	1
#define AUXCLK_SRCSELECT_PER_DPLL	2
#define AUXCLK_SRCSELECT_ALTERNATE	3

#endif /* _CLOCKS_OMAP5_H_ */
Commit	Line	Data
2e5ba489 S	1	/*
	2	* (C) Copyright 2010
	3	* Texas Instruments, <www.ti.com>
	4	*
	5	* Aneesh V <aneesh@ti.com>
	6	* Sricharan R <r.sricharan@ti.com>
	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
2e5ba489 S	9	*/
	10	#ifndef _CLOCKS_OMAP5_H_
	11	#define _CLOCKS_OMAP5_H_
	12	#include <common.h>
01b753ff	13	#include <asm/omap_common.h>
2e5ba489 S	14
	15	/*
	16	* Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per
	17	* loop, allow for a minimum of 2 ms wait (in reality the wait will be
	18	* much more than that)
	19	*/
	20	#define LDELAY 1000000
	21
753bae8c LV	22	/* CM_DLL_CTRL */
	23	#define CM_DLL_CTRL_OVERRIDE_SHIFT 0
	24	#define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0)
	25	#define CM_DLL_CTRL_NO_OVERRIDE 0
	26
2e5ba489 S	27	/* CM_CLKMODE_DPLL */
	28	#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11
	29	#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11)
	30	#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10
	31	#define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10)
	32	#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9
	33	#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9)
	34	#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8
	35	#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
	36	#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5
	37	#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5)
	38	#define CM_CLKMODE_DPLL_EN_SHIFT 0
	39	#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0)
	40
	41	#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0
	42	#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7
	43
	44	#define DPLL_EN_STOP 1
	45	#define DPLL_EN_MN_BYPASS 4
	46	#define DPLL_EN_LOW_POWER_BYPASS 5
	47	#define DPLL_EN_FAST_RELOCK_BYPASS 6
	48	#define DPLL_EN_LOCK 7
	49
	50	/* CM_IDLEST_DPLL fields */
	51	#define ST_DPLL_CLK_MASK 1
	52
5f14d919 S	53	/* SGX */
	54	#define CLKSEL_GPU_HYD_GCLK_MASK (1 << 25)
	55	#define CLKSEL_GPU_CORE_GCLK_MASK (1 << 24)
	56
2e5ba489 S	57	/* CM_CLKSEL_DPLL */
	58	#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24
	59	#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24)
	60	#define CM_CLKSEL_DPLL_M_SHIFT 8
	61	#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8)
	62	#define CM_CLKSEL_DPLL_N_SHIFT 0
	63	#define CM_CLKSEL_DPLL_N_MASK 0x7F
	64	#define CM_CLKSEL_DCC_EN_SHIFT 22
	65	#define CM_CLKSEL_DCC_EN_MASK (1 << 22)
	66
2e5ba489	67	/* CM_SYS_CLKSEL */
97405d84	68	#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7
2e5ba489 S	69
	70	/* CM_CLKSEL_CORE */
	71	#define CLKSEL_CORE_SHIFT 0
	72	#define CLKSEL_L3_SHIFT 4
	73	#define CLKSEL_L4_SHIFT 8
	74
	75	#define CLKSEL_CORE_X2_DIV_1 0
	76	#define CLKSEL_L3_CORE_DIV_2 1
	77	#define CLKSEL_L4_L3_DIV_2 1
	78
	79	/* CM_ABE_PLL_REF_CLKSEL */
	80	#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0
	81	#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK 1
	82	#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0
	83	#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1
	84
97405d84 LV	85	/* CM_CLKSEL_ABE_PLL_SYS */
	86	#define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_SHIFT 0
	87	#define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK 1
	88	#define CM_ABE_PLL_SYS_CLKSEL_SYSCLK1 0
	89	#define CM_ABE_PLL_SYS_CLKSEL_SYSCLK2 1
	90
2e5ba489 S	91	/* CM_BYPCLK_DPLL_IVA */
	92	#define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0
	93	#define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3
	94
	95	#define DPLL_IVA_CLKSEL_CORE_X2_DIV_2 1
	96
	97	/* CM_SHADOW_FREQ_CONFIG1 */
	98	#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1
	99	#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4
	100	#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8
	101
	102	#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8
	103	#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8)
	104
	105	#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11
	106	#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11)
	107
	108	/CM_<clock_domain>__CLKCTRL /
	109	#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0
	110	#define CD_CLKCTRL_CLKTRCTRL_MASK 3
	111
	112	#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0
	113	#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1
	114	#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2
	115	#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3
	116
	117
	118	/* CM_<clock_domain>_<module>_CLKCTRL */
	119	#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0
	120	#define MODULE_CLKCTRL_MODULEMODE_MASK 3
	121	#define MODULE_CLKCTRL_IDLEST_SHIFT 16
	122	#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16)
	123
	124	#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0
	125	#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1
	126	#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2
	127
	128	#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0
	129	#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1
	130	#define MODULE_CLKCTRL_IDLEST_IDLE 2
	131	#define MODULE_CLKCTRL_IDLEST_DISABLED 3
	132
	133	/* CM_L4PER_GPIO4_CLKCTRL */
	134	#define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
	135
	136	/* CM_L3INIT_HSMMCn_CLKCTRL */
	137	#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24)
5f14d919	138	#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (1 << 25)
2e5ba489	139
8ffcf74b RQ	140	/* CM_L3INIT_SATA_CLKCTRL */
	141	#define SATA_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
	142
2e5ba489 S	143	/* CM_WKUP_GPTIMER1_CLKCTRL */
	144	#define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24)
	145
	146	/* CM_CAM_ISS_CLKCTRL */
	147	#define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
	148
	149	/* CM_DSS_DSS_CLKCTRL */
	150	#define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00
	151
	152	/* CM_L3INIT_USBPHY_CLKCTRL */
	153	#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK 8
	154
d3d037ae DM	155	/* CM_L3INIT_USB_HOST_HS_CLKCTRL */
	156	#define OPTFCLKEN_FUNC48M_CLK (1 << 15)
	157	#define OPTFCLKEN_HSIC480M_P2_CLK (1 << 14)
	158	#define OPTFCLKEN_HSIC480M_P1_CLK (1 << 13)
	159	#define OPTFCLKEN_HSIC60M_P2_CLK (1 << 12)
	160	#define OPTFCLKEN_HSIC60M_P1_CLK (1 << 11)
	161	#define OPTFCLKEN_UTMI_P3_CLK (1 << 10)
	162	#define OPTFCLKEN_UTMI_P2_CLK (1 << 9)
	163	#define OPTFCLKEN_UTMI_P1_CLK (1 << 8)
	164	#define OPTFCLKEN_HSIC480M_P3_CLK (1 << 7)
	165	#define OPTFCLKEN_HSIC60M_P3_CLK (1 << 6)
	166
	167	/* CM_L3INIT_USB_TLL_HS_CLKCTRL */
	168	#define OPTFCLKEN_USB_CH0_CLK_ENABLE (1 << 8)
	169	#define OPTFCLKEN_USB_CH1_CLK_ENABLE (1 << 9)
	170	#define OPTFCLKEN_USB_CH2_CLK_ENABLE (1 << 10)
	171
d861a333 DM	172	/* CM_COREAON_USB_PHY_CORE_CLKCTRL */
	173	#define USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K (1 << 8)
	174
	175	/* CM_L3INIT_USB_OTG_SS_CLKCTRL */
	176	#define OTG_SS_CLKCTRL_MODULEMODE_HW (1 << 0)
	177	#define OPTFCLKEN_REFCLK960M (1 << 8)
	178
	179	/* CM_L3INIT_OCP2SCP1_CLKCTRL */
	180	#define OCP2SCP1_CLKCTRL_MODULEMODE_HW (1 << 0)
	181
2e5ba489 S	182	/* CM_MPU_MPU_CLKCTRL */
2e5ba489 S	183	#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24
47abc3df S	184	#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (3 << 24)
	185	#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 26
	186	#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 26)
2e5ba489	187
5f14d919 S	188	/* CM_WKUPAON_SCRM_CLKCTRL */
	189	#define OPTFCLKEN_SCRM_PER_SHIFT 9
	190	#define OPTFCLKEN_SCRM_PER_MASK (1 << 9)
	191	#define OPTFCLKEN_SCRM_CORE_SHIFT 8
	192	#define OPTFCLKEN_SCRM_CORE_MASK (1 << 8)
	193
d4d986ee LV	194	/* CM_COREAON_IO_SRCOMP_CLKCTRL */
	195	#define OPTFCLKEN_SRCOMP_FCLK_SHIFT 8
	196	#define OPTFCLKEN_SRCOMP_FCLK_MASK (1 << 8)
	197
0b1b60c7 LV	198	/* PRM_RSTTIME */
	199	#define RSTTIME1_SHIFT 0
	200	#define RSTTIME1_MASK (0x3ff << 0)
	201
2e5ba489	202	/* Clock frequencies */
2e5ba489	203	#define OMAP_SYS_CLK_IND_38_4_MHZ 6
2e5ba489	204
2e5ba489 S	205	/* PRM_VC_VAL_BYPASS */
	206	#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400
	207
834e91af DM	208	/* CTRL_CORE_SRCOMP_NORTH_SIDE */
	209	#define USB2PHY_DISCHGDET (1 << 29)
	210	#define USB2PHY_AUTORESUME_EN (1 << 30)
	211
2e5ba489 S	212	/* SMPS */
2e5ba489 S	213	#define SMPS_I2C_SLAVE_ADDR 0x12
8de17f46 S	214	#define SMPS_REG_ADDR_12_MPU 0x23
	215	#define SMPS_REG_ADDR_45_IVA 0x2B
	216	#define SMPS_REG_ADDR_8_CORE 0x37
2e5ba489	217
8de17f46	218	/* PALMAS VOLTAGE SETTINGS in mv for OPP_NOMINAL */
47abc3df S	219	/* ES1.0 settings */
	220	#define VDD_MPU 1040
	221	#define VDD_MM 1040
8de17f46	222	#define VDD_CORE 1040
47abc3df S	223
	224	#define VDD_MPU_LOW 890
	225	#define VDD_MM_LOW 890
	226	#define VDD_CORE_LOW 890
	227
	228	/* ES2.0 settings */
	229	#define VDD_MPU_ES2 1060
	230	#define VDD_MM_ES2 1025
	231	#define VDD_CORE_ES2 1040
	232
	233	#define VDD_MPU_ES2_HIGH 1250
	234	#define VDD_MM_ES2_OD 1120
	235
	236	#define VDD_MPU_ES2_LOW 880
	237	#define VDD_MM_ES2_LOW 880
8de17f46	238
63fc0c77 LV	239	/* TPS659038 Voltage settings in mv for OPP_NOMINAL */
	240	#define VDD_MPU_DRA752 1090
	241	#define VDD_EVE_DRA752 1060
	242	#define VDD_GPU_DRA752 1060
	243	#define VDD_CORE_DRA752 1030
	244	#define VDD_IVA_DRA752 1060
	245
18c9d55a NM	246	/* Efuse register offsets for DRA7xx platform */
	247	#define DRA752_EFUSE_BASE 0x4A002000
	248	#define DRA752_EFUSE_REGBITS 16
	249	/* STD_FUSE_OPP_VMIN_IVA_2 */
	250	#define STD_FUSE_OPP_VMIN_IVA_NOM (DRA752_EFUSE_BASE + 0x05CC)
	251	/* STD_FUSE_OPP_VMIN_IVA_3 */
	252	#define STD_FUSE_OPP_VMIN_IVA_OD (DRA752_EFUSE_BASE + 0x05D0)
	253	/* STD_FUSE_OPP_VMIN_IVA_4 */
	254	#define STD_FUSE_OPP_VMIN_IVA_HIGH (DRA752_EFUSE_BASE + 0x05D4)
	255	/* STD_FUSE_OPP_VMIN_DSPEVE_2 */
	256	#define STD_FUSE_OPP_VMIN_DSPEVE_NOM (DRA752_EFUSE_BASE + 0x05E0)
	257	/* STD_FUSE_OPP_VMIN_DSPEVE_3 */
	258	#define STD_FUSE_OPP_VMIN_DSPEVE_OD (DRA752_EFUSE_BASE + 0x05E4)
	259	/* STD_FUSE_OPP_VMIN_DSPEVE_4 */
	260	#define STD_FUSE_OPP_VMIN_DSPEVE_HIGH (DRA752_EFUSE_BASE + 0x05E8)
	261	/* STD_FUSE_OPP_VMIN_CORE_2 */
	262	#define STD_FUSE_OPP_VMIN_CORE_NOM (DRA752_EFUSE_BASE + 0x05F4)
	263	/* STD_FUSE_OPP_VMIN_GPU_2 */
	264	#define STD_FUSE_OPP_VMIN_GPU_NOM (DRA752_EFUSE_BASE + 0x1B08)
	265	/* STD_FUSE_OPP_VMIN_GPU_3 */
	266	#define STD_FUSE_OPP_VMIN_GPU_OD (DRA752_EFUSE_BASE + 0x1B0C)
	267	/* STD_FUSE_OPP_VMIN_GPU_4 */
	268	#define STD_FUSE_OPP_VMIN_GPU_HIGH (DRA752_EFUSE_BASE + 0x1B10)
	269	/* STD_FUSE_OPP_VMIN_MPU_2 */
	270	#define STD_FUSE_OPP_VMIN_MPU_NOM (DRA752_EFUSE_BASE + 0x1B20)
	271	/* STD_FUSE_OPP_VMIN_MPU_3 */
	272	#define STD_FUSE_OPP_VMIN_MPU_OD (DRA752_EFUSE_BASE + 0x1B24)
	273	/* STD_FUSE_OPP_VMIN_MPU_4 */
	274	#define STD_FUSE_OPP_VMIN_MPU_HIGH (DRA752_EFUSE_BASE + 0x1B28)
	275
8de17f46 S	276	/* Standard offset is 0.5v expressed in uv */
8de17f46 S	277	#define PALMAS_SMPS_BASE_VOLT_UV 500000
2e5ba489	278
63fc0c77 LV	279	/* TPS659038 */
	280	#define TPS659038_I2C_SLAVE_ADDR 0x58
	281	#define TPS659038_REG_ADDR_SMPS12_MPU 0x23
	282	#define TPS659038_REG_ADDR_SMPS45_EVE 0x2B
	283	#define TPS659038_REG_ADDR_SMPS6_GPU 0x2F
	284	#define TPS659038_REG_ADDR_SMPS7_CORE 0x33
	285	#define TPS659038_REG_ADDR_SMPS8_IVA 0x37
	286
2e5ba489 S	287	/* TPS */
	288	#define TPS62361_I2C_SLAVE_ADDR 0x60
	289	#define TPS62361_REG_ADDR_SET0 0x0
	290	#define TPS62361_REG_ADDR_SET1 0x1
	291	#define TPS62361_REG_ADDR_SET2 0x2
	292	#define TPS62361_REG_ADDR_SET3 0x3
	293	#define TPS62361_REG_ADDR_CTRL 0x4
	294	#define TPS62361_REG_ADDR_TEMP 0x5
	295	#define TPS62361_REG_ADDR_RMP_CTRL 0x6
	296	#define TPS62361_REG_ADDR_CHIP_ID 0x8
	297	#define TPS62361_REG_ADDR_CHIP_ID_2 0x9
	298
	299	#define TPS62361_BASE_VOLT_MV 500
	300	#define TPS62361_VSEL0_GPIO 7
	301
ee28edac LP	302	/* Defines for DPLL setup */
	303	#define DPLL_LOCKED_FREQ_TOLERANCE_0 0
	304	#define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ 500
	305	#define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ 1000
	306
2e5ba489 S	307	#define DPLL_NO_LOCK 0
	308	#define DPLL_LOCK 1
	309
0b1b60c7 LV	310	/*
	311	* MAX value for PRM_RSTTIME[9:0]RSTTIME1 stored is 0x3ff.
	312	* 0x3ff is in the no of FUNC_32K_CLK cycles. Converting cycles
	313	* into microsec and passing the value.
	314	*/
	315	#define CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC 31219
f9b814a8 S	316
	317	#ifdef CONFIG_DRA7XX
	318	#define V_OSCK 20000000 /* Clock output from T2 */
	319	#else
	320	#define V_OSCK 19200000 /* Clock output from T2 */
	321	#endif
	322
	323	#define V_SCLK V_OSCK
ee28edac LP	324
	325	/* AUXCLKx reg fields */
	326	#define AUXCLK_ENABLE_MASK (1 << 8)
	327	#define AUXCLK_SRCSELECT_SHIFT 1
	328	#define AUXCLK_SRCSELECT_MASK (3 << 1)
	329	#define AUXCLK_CLKDIV_SHIFT 16
	330	#define AUXCLK_CLKDIV_MASK (0xF << 16)
	331
	332	#define AUXCLK_SRCSELECT_SYS_CLK 0
	333	#define AUXCLK_SRCSELECT_CORE_DPLL 1
	334	#define AUXCLK_SRCSELECT_PER_DPLL 2
	335	#define AUXCLK_SRCSELECT_ALTERNATE 3
	336
2e5ba489	337	#endif /* _CLOCKS_OMAP5_H_ */