[people/ms/u-boot.git] / arch / arm / include / asm / arch-omap5 / clocks.h

/*
 * (C) Copyright 2010
 * Texas Instruments, <www.ti.com>
 *
 *	Aneesh V <aneesh@ti.com>
 *	Sricharan R <r.sricharan@ti.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
#ifndef _CLOCKS_OMAP5_H_
#define _CLOCKS_OMAP5_H_
#include <common.h>
#include <asm/omap_common.h>

/*
 * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per
 * loop, allow for a minimum of 2 ms wait (in reality the wait will be
 * much more than that)
 */
#define LDELAY		1000000

#define CM_CLKMODE_DPLL_CORE		(OMAP54XX_L4_CORE_BASE + 0x4120)
#define CM_CLKMODE_DPLL_PER		(OMAP54XX_L4_CORE_BASE + 0x8140)
#define CM_CLKMODE_DPLL_MPU		(OMAP54XX_L4_CORE_BASE + 0x4160)
#define CM_CLKSEL_CORE			(OMAP54XX_L4_CORE_BASE + 0x4100)

/* DPLL register offsets */
#define CM_CLKMODE_DPLL		0
#define CM_IDLEST_DPLL		0x4
#define CM_AUTOIDLE_DPLL	0x8
#define CM_CLKSEL_DPLL		0xC

#define DPLL_CLKOUT_DIV_MASK	0x1F /* post-divider mask */

/* CM_DLL_CTRL */
#define CM_DLL_CTRL_OVERRIDE_SHIFT		0
#define CM_DLL_CTRL_OVERRIDE_MASK		(1 << 0)
#define CM_DLL_CTRL_NO_OVERRIDE			0

/* CM_CLKMODE_DPLL */
#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT		11
#define CM_CLKMODE_DPLL_REGM4XEN_MASK		(1 << 11)
#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT		10
#define CM_CLKMODE_DPLL_LPMODE_EN_MASK		(1 << 10)
#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT	9
#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK	(1 << 9)
#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT	8
#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK	(1 << 8)
#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT		5
#define CM_CLKMODE_DPLL_RAMP_RATE_MASK		(0x7 << 5)
#define CM_CLKMODE_DPLL_EN_SHIFT		0
#define CM_CLKMODE_DPLL_EN_MASK			(0x7 << 0)

#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT		0
#define CM_CLKMODE_DPLL_DPLL_EN_MASK		7

#define DPLL_EN_STOP			1
#define DPLL_EN_MN_BYPASS		4
#define DPLL_EN_LOW_POWER_BYPASS	5
#define DPLL_EN_FAST_RELOCK_BYPASS	6
#define DPLL_EN_LOCK			7

/* CM_IDLEST_DPLL fields */
#define ST_DPLL_CLK_MASK		1

/* SGX */
#define CLKSEL_GPU_HYD_GCLK_MASK		(1 << 25)
#define CLKSEL_GPU_CORE_GCLK_MASK		(1 << 24)

/* CM_CLKSEL_DPLL */
#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT	24
#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK		(0xFF << 24)
#define CM_CLKSEL_DPLL_M_SHIFT			8
#define CM_CLKSEL_DPLL_M_MASK			(0x7FF << 8)
#define CM_CLKSEL_DPLL_N_SHIFT			0
#define CM_CLKSEL_DPLL_N_MASK			0x7F
#define CM_CLKSEL_DCC_EN_SHIFT			22
#define CM_CLKSEL_DCC_EN_MASK			(1 << 22)

#define OMAP4_DPLL_MAX_N	127

/* CM_SYS_CLKSEL */
#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK	7

/* CM_CLKSEL_CORE */
#define CLKSEL_CORE_SHIFT	0
#define CLKSEL_L3_SHIFT		4
#define CLKSEL_L4_SHIFT		8

#define CLKSEL_CORE_X2_DIV_1	0
#define CLKSEL_L3_CORE_DIV_2	1
#define CLKSEL_L4_L3_DIV_2	1

/* CM_ABE_PLL_REF_CLKSEL */
#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT	0
#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK	1
#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK	0
#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK	1

/* CM_BYPCLK_DPLL_IVA */
#define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT		0
#define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK		3

#define DPLL_IVA_CLKSEL_CORE_X2_DIV_2		1

/* CM_SHADOW_FREQ_CONFIG1 */
#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK	1
#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK	4
#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK	8

#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT	8
#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK	(7 << 8)

#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT	11
#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK		(0x1F << 11)

/*CM_<clock_domain>__CLKCTRL */
#define CD_CLKCTRL_CLKTRCTRL_SHIFT		0
#define CD_CLKCTRL_CLKTRCTRL_MASK		3

#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP		0
#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP		1
#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP		2
#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO		3


/* CM_<clock_domain>_<module>_CLKCTRL */
#define MODULE_CLKCTRL_MODULEMODE_SHIFT		0
#define MODULE_CLKCTRL_MODULEMODE_MASK		3
#define MODULE_CLKCTRL_IDLEST_SHIFT		16
#define MODULE_CLKCTRL_IDLEST_MASK		(3 << 16)

#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE		0
#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO		1
#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN	2

#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL	0
#define MODULE_CLKCTRL_IDLEST_TRANSITIONING	1
#define MODULE_CLKCTRL_IDLEST_IDLE		2
#define MODULE_CLKCTRL_IDLEST_DISABLED		3

/* CM_L4PER_GPIO4_CLKCTRL */
#define GPIO4_CLKCTRL_OPTFCLKEN_MASK		(1 << 8)

/* CM_L3INIT_HSMMCn_CLKCTRL */
#define HSMMC_CLKCTRL_CLKSEL_MASK		(1 << 24)
#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK		(1 << 25)

/* CM_WKUP_GPTIMER1_CLKCTRL */
#define GPTIMER1_CLKCTRL_CLKSEL_MASK		(1 << 24)

/* CM_CAM_ISS_CLKCTRL */
#define ISS_CLKCTRL_OPTFCLKEN_MASK		(1 << 8)

/* CM_DSS_DSS_CLKCTRL */
#define DSS_CLKCTRL_OPTFCLKEN_MASK		0xF00

/* CM_L3INIT_USBPHY_CLKCTRL */
#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK	8

/* CM_MPU_MPU_CLKCTRL */
#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT	24
#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK	(3 << 24)
#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT	26
#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK	(1 << 26)

/* CM_WKUPAON_SCRM_CLKCTRL */
#define OPTFCLKEN_SCRM_PER_SHIFT		9
#define OPTFCLKEN_SCRM_PER_MASK			(1 << 9)
#define OPTFCLKEN_SCRM_CORE_SHIFT		8
#define OPTFCLKEN_SCRM_CORE_MASK		(1 << 8)

/* Clock frequencies */
#define OMAP_SYS_CLK_FREQ_38_4_MHZ	38400000
#define OMAP_SYS_CLK_IND_38_4_MHZ	6
#define OMAP_32K_CLK_FREQ		32768

/* PRM_VC_VAL_BYPASS */
#define PRM_VC_I2C_CHANNEL_FREQ_KHZ	400

/* SMPS */
#define SMPS_I2C_SLAVE_ADDR	0x12
#define SMPS_REG_ADDR_12_MPU	0x23
#define SMPS_REG_ADDR_45_IVA	0x2B
#define SMPS_REG_ADDR_8_CORE	0x37

/* PALMAS VOLTAGE SETTINGS in mv for OPP_NOMINAL */
/* ES1.0 settings */
#define VDD_MPU		1040
#define VDD_MM		1040
#define VDD_CORE	1040

#define VDD_MPU_LOW	890
#define VDD_MM_LOW	890
#define VDD_CORE_LOW	890

/* ES2.0 settings */
#define VDD_MPU_ES2	1060
#define VDD_MM_ES2	1025
#define VDD_CORE_ES2	1040

#define VDD_MPU_ES2_HIGH 1250
#define VDD_MM_ES2_OD  1120

#define VDD_MPU_ES2_LOW 880
#define VDD_MM_ES2_LOW 880

/* Standard offset is 0.5v expressed in uv */
#define PALMAS_SMPS_BASE_VOLT_UV 500000

/* TPS */
#define TPS62361_I2C_SLAVE_ADDR		0x60
#define TPS62361_REG_ADDR_SET0		0x0
#define TPS62361_REG_ADDR_SET1		0x1
#define TPS62361_REG_ADDR_SET2		0x2
#define TPS62361_REG_ADDR_SET3		0x3
#define TPS62361_REG_ADDR_CTRL		0x4
#define TPS62361_REG_ADDR_TEMP		0x5
#define TPS62361_REG_ADDR_RMP_CTRL	0x6
#define TPS62361_REG_ADDR_CHIP_ID	0x8
#define TPS62361_REG_ADDR_CHIP_ID_2	0x9

#define TPS62361_BASE_VOLT_MV	500
#define TPS62361_VSEL0_GPIO	7

/* Defines for DPLL setup */
#define DPLL_LOCKED_FREQ_TOLERANCE_0		0
#define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ	500
#define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ	1000

#define DPLL_NO_LOCK	0
#define DPLL_LOCK	1

#endif /* _CLOCKS_OMAP5_H_ */
Commit	Line	Data
2e5ba489 S	1	/*
	2	* (C) Copyright 2010
	3	* Texas Instruments, <www.ti.com>
	4	*
	5	* Aneesh V <aneesh@ti.com>
	6	* Sricharan R <r.sricharan@ti.com>
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26	#ifndef _CLOCKS_OMAP5_H_
	27	#define _CLOCKS_OMAP5_H_
	28	#include <common.h>
01b753ff	29	#include <asm/omap_common.h>
2e5ba489 S	30
	31	/*
	32	* Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per
	33	* loop, allow for a minimum of 2 ms wait (in reality the wait will be
	34	* much more than that)
	35	*/
	36	#define LDELAY 1000000
	37
	38	#define CM_CLKMODE_DPLL_CORE (OMAP54XX_L4_CORE_BASE + 0x4120)
	39	#define CM_CLKMODE_DPLL_PER (OMAP54XX_L4_CORE_BASE + 0x8140)
	40	#define CM_CLKMODE_DPLL_MPU (OMAP54XX_L4_CORE_BASE + 0x4160)
	41	#define CM_CLKSEL_CORE (OMAP54XX_L4_CORE_BASE + 0x4100)
	42
2e5ba489 S	43	/* DPLL register offsets */
	44	#define CM_CLKMODE_DPLL 0
	45	#define CM_IDLEST_DPLL 0x4
	46	#define CM_AUTOIDLE_DPLL 0x8
	47	#define CM_CLKSEL_DPLL 0xC
	48
	49	#define DPLL_CLKOUT_DIV_MASK 0x1F /* post-divider mask */
	50
753bae8c LV	51	/* CM_DLL_CTRL */
	52	#define CM_DLL_CTRL_OVERRIDE_SHIFT 0
	53	#define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0)
	54	#define CM_DLL_CTRL_NO_OVERRIDE 0
	55
2e5ba489 S	56	/* CM_CLKMODE_DPLL */
	57	#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11
	58	#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11)
	59	#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10
	60	#define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10)
	61	#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9
	62	#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9)
	63	#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8
	64	#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
	65	#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5
	66	#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5)
	67	#define CM_CLKMODE_DPLL_EN_SHIFT 0
	68	#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0)
	69
	70	#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0
	71	#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7
	72
	73	#define DPLL_EN_STOP 1
	74	#define DPLL_EN_MN_BYPASS 4
	75	#define DPLL_EN_LOW_POWER_BYPASS 5
	76	#define DPLL_EN_FAST_RELOCK_BYPASS 6
	77	#define DPLL_EN_LOCK 7
	78
	79	/* CM_IDLEST_DPLL fields */
	80	#define ST_DPLL_CLK_MASK 1
	81
5f14d919 S	82	/* SGX */
	83	#define CLKSEL_GPU_HYD_GCLK_MASK (1 << 25)
	84	#define CLKSEL_GPU_CORE_GCLK_MASK (1 << 24)
	85
2e5ba489 S	86	/* CM_CLKSEL_DPLL */
	87	#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24
	88	#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24)
	89	#define CM_CLKSEL_DPLL_M_SHIFT 8
	90	#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8)
	91	#define CM_CLKSEL_DPLL_N_SHIFT 0
	92	#define CM_CLKSEL_DPLL_N_MASK 0x7F
	93	#define CM_CLKSEL_DCC_EN_SHIFT 22
	94	#define CM_CLKSEL_DCC_EN_MASK (1 << 22)
	95
	96	#define OMAP4_DPLL_MAX_N 127
	97
	98	/* CM_SYS_CLKSEL */
	99	#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7
	100
	101	/* CM_CLKSEL_CORE */
	102	#define CLKSEL_CORE_SHIFT 0
	103	#define CLKSEL_L3_SHIFT 4
	104	#define CLKSEL_L4_SHIFT 8
	105
	106	#define CLKSEL_CORE_X2_DIV_1 0
	107	#define CLKSEL_L3_CORE_DIV_2 1
	108	#define CLKSEL_L4_L3_DIV_2 1
	109
	110	/* CM_ABE_PLL_REF_CLKSEL */
	111	#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0
	112	#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK 1
	113	#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0
	114	#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1
	115
	116	/* CM_BYPCLK_DPLL_IVA */
	117	#define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0
	118	#define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3
	119
	120	#define DPLL_IVA_CLKSEL_CORE_X2_DIV_2 1
	121
	122	/* CM_SHADOW_FREQ_CONFIG1 */
	123	#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1
	124	#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4
	125	#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8
	126
	127	#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8
	128	#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8)
	129
	130	#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11
	131	#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11)
	132
	133	/CM_<clock_domain>__CLKCTRL /
	134	#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0
	135	#define CD_CLKCTRL_CLKTRCTRL_MASK 3
	136
	137	#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0
	138	#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1
	139	#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2
	140	#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3
	141
	142
	143	/* CM_<clock_domain>_<module>_CLKCTRL */
	144	#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0
	145	#define MODULE_CLKCTRL_MODULEMODE_MASK 3
	146	#define MODULE_CLKCTRL_IDLEST_SHIFT 16
	147	#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16)
	148
	149	#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0
150	#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1
151	#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2
152
153	#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0
154	#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1
155	#define MODULE_CLKCTRL_IDLEST_IDLE 2
156	#define MODULE_CLKCTRL_IDLEST_DISABLED 3
157
158	/* CM_L4PER_GPIO4_CLKCTRL */
159	#define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
160
161	/* CM_L3INIT_HSMMCn_CLKCTRL */
162	#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24)
5f14d919	163	#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (1 << 25)
2e5ba489 S	164
	165	/* CM_WKUP_GPTIMER1_CLKCTRL */
	166	#define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24)
	167
	168	/* CM_CAM_ISS_CLKCTRL */
	169	#define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
	170
	171	/* CM_DSS_DSS_CLKCTRL */
	172	#define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00
	173
	174	/* CM_L3INIT_USBPHY_CLKCTRL */
	175	#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK 8
	176
	177	/* CM_MPU_MPU_CLKCTRL */
	178	#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24
47abc3df S	179	#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (3 << 24)
	180	#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 26
	181	#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 26)
2e5ba489	182
5f14d919 S	183	/* CM_WKUPAON_SCRM_CLKCTRL */
	184	#define OPTFCLKEN_SCRM_PER_SHIFT 9
	185	#define OPTFCLKEN_SCRM_PER_MASK (1 << 9)
	186	#define OPTFCLKEN_SCRM_CORE_SHIFT 8
	187	#define OPTFCLKEN_SCRM_CORE_MASK (1 << 8)
	188
2e5ba489 S	189	/* Clock frequencies */
	190	#define OMAP_SYS_CLK_FREQ_38_4_MHZ 38400000
	191	#define OMAP_SYS_CLK_IND_38_4_MHZ 6
	192	#define OMAP_32K_CLK_FREQ 32768
	193
2e5ba489 S	194	/* PRM_VC_VAL_BYPASS */
	195	#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400
	196
2e5ba489 S	197	/* SMPS */
2e5ba489 S	198	#define SMPS_I2C_SLAVE_ADDR 0x12
8de17f46 S	199	#define SMPS_REG_ADDR_12_MPU 0x23
	200	#define SMPS_REG_ADDR_45_IVA 0x2B
	201	#define SMPS_REG_ADDR_8_CORE 0x37
2e5ba489	202
8de17f46	203	/* PALMAS VOLTAGE SETTINGS in mv for OPP_NOMINAL */
47abc3df S	204	/* ES1.0 settings */
	205	#define VDD_MPU 1040
	206	#define VDD_MM 1040
8de17f46	207	#define VDD_CORE 1040
47abc3df S	208
	209	#define VDD_MPU_LOW 890
	210	#define VDD_MM_LOW 890
	211	#define VDD_CORE_LOW 890
	212
	213	/* ES2.0 settings */
	214	#define VDD_MPU_ES2 1060
	215	#define VDD_MM_ES2 1025
	216	#define VDD_CORE_ES2 1040
	217
	218	#define VDD_MPU_ES2_HIGH 1250
	219	#define VDD_MM_ES2_OD 1120
	220
	221	#define VDD_MPU_ES2_LOW 880
	222	#define VDD_MM_ES2_LOW 880
8de17f46 S	223
	224	/* Standard offset is 0.5v expressed in uv */
	225	#define PALMAS_SMPS_BASE_VOLT_UV 500000
2e5ba489 S	226
	227	/* TPS */
	228	#define TPS62361_I2C_SLAVE_ADDR 0x60
	229	#define TPS62361_REG_ADDR_SET0 0x0
	230	#define TPS62361_REG_ADDR_SET1 0x1
	231	#define TPS62361_REG_ADDR_SET2 0x2
	232	#define TPS62361_REG_ADDR_SET3 0x3
	233	#define TPS62361_REG_ADDR_CTRL 0x4
	234	#define TPS62361_REG_ADDR_TEMP 0x5
	235	#define TPS62361_REG_ADDR_RMP_CTRL 0x6
	236	#define TPS62361_REG_ADDR_CHIP_ID 0x8
	237	#define TPS62361_REG_ADDR_CHIP_ID_2 0x9
	238
	239	#define TPS62361_BASE_VOLT_MV 500
	240	#define TPS62361_VSEL0_GPIO 7
	241
	242	/* Defines for DPLL setup */
	243	#define DPLL_LOCKED_FREQ_TOLERANCE_0 0
	244	#define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ 500
	245	#define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ 1000
	246
	247	#define DPLL_NO_LOCK 0
	248	#define DPLL_LOCK 1
	249
2e5ba489	250	#endif /* _CLOCKS_OMAP5_H_ */