[people/ms/u-boot.git] / arch / arm / include / asm / arch-omap5 / cpu.h

/*
 * (C) Copyright 2006-2010
 * Texas Instruments, <www.ti.com>
 *
 *	Aneesh V <aneesh@ti.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _CPU_H
#define _CPU_H

#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>
#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */

#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
struct gptimer {
	u32 tidr;		/* 0x00 r */
	u8 res1[0xc];
	u32 tiocp_cfg;		/* 0x10 rw */
	u8 res2[0x10];
	u32 tisr_raw;		/* 0x24 r */
	u32 tisr;		/* 0x28 rw */
	u32 tier;		/* 0x2c rw */
	u32 ticr;		/* 0x30 rw */
	u32 twer;		/* 0x34 rw */
	u32 tclr;		/* 0x38 rw */
	u32 tcrr;		/* 0x3c rw */
	u32 tldr;		/* 0x40 rw */
	u32 ttgr;		/* 0x44 rw */
	u32 twpc;		/* 0x48 r */
	u32 tmar;		/* 0x4c rw */
	u32 tcar1;		/* 0x50 r */
	u32 tcicr;		/* 0x54 rw */
	u32 tcar2;		/* 0x58 r */
};
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL_STRICT_NAMES */

/* enable sys_clk NO-prescale /1 */
#define GPT_EN			((0x0 << 2) | (0x1 << 1) | (0x1 << 0))

/* Watchdog */
#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
struct watchdog {
	u8 res1[0x34];
	u32 wwps;		/* 0x34 r */
	u8 res2[0x10];
	u32 wspr;		/* 0x48 rw */
};
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL_STRICT_NAMES */

#define BIT(x)				(1 << (x))

#define WD_UNLOCK1		0xAAAA
#define WD_UNLOCK2		0x5555

#define TCLR_ST			(0x1 << 0)
#define TCLR_AR			(0x1 << 1)
#define TCLR_PRE		(0x1 << 5)

/* GPMC BASE */
#define GPMC_BASE		(OMAP54XX_GPMC_BASE)

/* I2C base */
#define I2C_BASE1		(OMAP54XX_L4_PER_BASE + 0x70000)
#define I2C_BASE2		(OMAP54XX_L4_PER_BASE + 0x72000)
#define I2C_BASE3		(OMAP54XX_L4_PER_BASE + 0x60000)
#define I2C_BASE4		(OMAP54XX_L4_PER_BASE + 0x7A000)
#define I2C_BASE5		(OMAP54XX_L4_PER_BASE + 0x7C000)

/* MUSB base */
#define MUSB_BASE		(OMAP54XX_L4_CORE_BASE + 0xAB000)

/* OMAP4 GPIO registers */
#define OMAP_GPIO_REVISION		0x0000
#define OMAP_GPIO_SYSCONFIG		0x0010
#define OMAP_GPIO_SYSSTATUS		0x0114
#define OMAP_GPIO_IRQSTATUS1		0x0118
#define OMAP_GPIO_IRQSTATUS2		0x0128
#define OMAP_GPIO_IRQENABLE2		0x012c
#define OMAP_GPIO_IRQENABLE1		0x011c
#define OMAP_GPIO_WAKE_EN		0x0120
#define OMAP_GPIO_CTRL			0x0130
#define OMAP_GPIO_OE			0x0134
#define OMAP_GPIO_DATAIN		0x0138
#define OMAP_GPIO_DATAOUT		0x013c
#define OMAP_GPIO_LEVELDETECT0		0x0140
#define OMAP_GPIO_LEVELDETECT1		0x0144
#define OMAP_GPIO_RISINGDETECT		0x0148
#define OMAP_GPIO_FALLINGDETECT		0x014c
#define OMAP_GPIO_DEBOUNCE_EN		0x0150
#define OMAP_GPIO_DEBOUNCE_VAL		0x0154
#define OMAP_GPIO_CLEARIRQENABLE1	0x0160
#define OMAP_GPIO_SETIRQENABLE1		0x0164
#define OMAP_GPIO_CLEARWKUENA		0x0180
#define OMAP_GPIO_SETWKUENA		0x0184
#define OMAP_GPIO_CLEARDATAOUT		0x0190
#define OMAP_GPIO_SETDATAOUT		0x0194

/*
 * PRCM
 */

/* PRM */
#define PRM_BASE		0x4AE06000
#define PRM_DEVICE_BASE		(PRM_BASE + 0x1B00)

#define PRM_RSTCTRL		PRM_DEVICE_BASE
#define PRM_RSTCTRL_RESET	0x01
#define PRM_RSTST		(PRM_DEVICE_BASE + 0x4)
#define PRM_RSTST_WARM_RESET_MASK	0x7FEA

/* DRA7XX CPSW Config space */
#define CPSW_BASE			0x48484000
#define CPSW_MDIO_BASE			0x48485000

#endif /* _CPU_H */
Commit	Line	Data
508a58fa S	1	/*
	2	* (C) Copyright 2006-2010
	3	* Texas Instruments, <www.ti.com>
	4	*
	5	* Aneesh V <aneesh@ti.com>
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
508a58fa S	8	*/
	9
	10	#ifndef _CPU_H
	11	#define _CPU_H
	12
	13	#if !(defined(__KERNEL_STRICT_NAMES) \|\| defined(__ASSEMBLY__))
	14	#include <asm/types.h>
	15	#endif /* !(__KERNEL_STRICT_NAMES \|\| __ASSEMBLY__) */
	16
	17	#ifndef __KERNEL_STRICT_NAMES
	18	#ifndef __ASSEMBLY__
508a58fa S	19	struct gptimer {
	20	u32 tidr; /* 0x00 r */
	21	u8 res1[0xc];
	22	u32 tiocp_cfg; /* 0x10 rw */
	23	u8 res2[0x10];
	24	u32 tisr_raw; /* 0x24 r */
	25	u32 tisr; /* 0x28 rw */
	26	u32 tier; /* 0x2c rw */
	27	u32 ticr; /* 0x30 rw */
	28	u32 twer; /* 0x34 rw */
	29	u32 tclr; /* 0x38 rw */
	30	u32 tcrr; /* 0x3c rw */
	31	u32 tldr; /* 0x40 rw */
	32	u32 ttgr; /* 0x44 rw */
	33	u32 twpc; /* 0x48 r */
	34	u32 tmar; /* 0x4c rw */
	35	u32 tcar1; /* 0x50 r */
	36	u32 tcicr; /* 0x54 rw */
	37	u32 tcar2; /* 0x58 r */
	38	};
	39	#endif /* __ASSEMBLY__ */
	40	#endif /* __KERNEL_STRICT_NAMES */
	41
	42	/* enable sys_clk NO-prescale /1 */
	43	#define GPT_EN ((0x0 << 2) \| (0x1 << 1) \| (0x1 << 0))
	44
	45	/* Watchdog */
	46	#ifndef __KERNEL_STRICT_NAMES
	47	#ifndef __ASSEMBLY__
	48	struct watchdog {
	49	u8 res1[0x34];
	50	u32 wwps; /* 0x34 r */
	51	u8 res2[0x10];
	52	u32 wspr; /* 0x48 rw */
	53	};
	54	#endif /* __ASSEMBLY__ */
	55	#endif /* __KERNEL_STRICT_NAMES */
	56
b1e26e3b M	57	#define BIT(x) (1 << (x))
b1e26e3b M	58
508a58fa S	59	#define WD_UNLOCK1 0xAAAA
	60	#define WD_UNLOCK2 0x5555
	61
508a58fa S	62	#define TCLR_ST (0x1 << 0)
	63	#define TCLR_AR (0x1 << 1)
	64	#define TCLR_PRE (0x1 << 5)
	65
	66	/* GPMC BASE */
	67	#define GPMC_BASE (OMAP54XX_GPMC_BASE)
	68
	69	/* I2C base */
	70	#define I2C_BASE1 (OMAP54XX_L4_PER_BASE + 0x70000)
	71	#define I2C_BASE2 (OMAP54XX_L4_PER_BASE + 0x72000)
	72	#define I2C_BASE3 (OMAP54XX_L4_PER_BASE + 0x60000)
aebe7ff2 LP	73	#define I2C_BASE4 (OMAP54XX_L4_PER_BASE + 0x7A000)
aebe7ff2 LP	74	#define I2C_BASE5 (OMAP54XX_L4_PER_BASE + 0x7C000)
508a58fa S	75
	76	/* MUSB base */
	77	#define MUSB_BASE (OMAP54XX_L4_CORE_BASE + 0xAB000)
	78
	79	/* OMAP4 GPIO registers */
	80	#define OMAP_GPIO_REVISION 0x0000
	81	#define OMAP_GPIO_SYSCONFIG 0x0010
	82	#define OMAP_GPIO_SYSSTATUS 0x0114
	83	#define OMAP_GPIO_IRQSTATUS1 0x0118
	84	#define OMAP_GPIO_IRQSTATUS2 0x0128
	85	#define OMAP_GPIO_IRQENABLE2 0x012c
	86	#define OMAP_GPIO_IRQENABLE1 0x011c
	87	#define OMAP_GPIO_WAKE_EN 0x0120
	88	#define OMAP_GPIO_CTRL 0x0130
	89	#define OMAP_GPIO_OE 0x0134
	90	#define OMAP_GPIO_DATAIN 0x0138
	91	#define OMAP_GPIO_DATAOUT 0x013c
	92	#define OMAP_GPIO_LEVELDETECT0 0x0140
	93	#define OMAP_GPIO_LEVELDETECT1 0x0144
	94	#define OMAP_GPIO_RISINGDETECT 0x0148
	95	#define OMAP_GPIO_FALLINGDETECT 0x014c
	96	#define OMAP_GPIO_DEBOUNCE_EN 0x0150
	97	#define OMAP_GPIO_DEBOUNCE_VAL 0x0154
	98	#define OMAP_GPIO_CLEARIRQENABLE1 0x0160
	99	#define OMAP_GPIO_SETIRQENABLE1 0x0164
	100	#define OMAP_GPIO_CLEARWKUENA 0x0180
	101	#define OMAP_GPIO_SETWKUENA 0x0184
	102	#define OMAP_GPIO_CLEARDATAOUT 0x0190
	103	#define OMAP_GPIO_SETDATAOUT 0x0194
	104
d417d1db S	105	/*
	106	* PRCM
	107	*/
	108
	109	/* PRM */
	110	#define PRM_BASE 0x4AE06000
	111	#define PRM_DEVICE_BASE (PRM_BASE + 0x1B00)
	112
	113	#define PRM_RSTCTRL PRM_DEVICE_BASE
	114	#define PRM_RSTCTRL_RESET 0x01
70239507 LV	115	#define PRM_RSTST (PRM_DEVICE_BASE + 0x4)
70239507 LV	116	#define PRM_RSTST_WARM_RESET_MASK 0x7FEA
d417d1db	117
b1e26e3b M	118	/* DRA7XX CPSW Config space */
	119	#define CPSW_BASE 0x48484000
	120	#define CPSW_MDIO_BASE 0x48485000
	121
508a58fa	122	#endif /* _CPU_H */