projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| d34efc76 SS |
1 | /* |
| 2 | * (C) Copyright 2010 | |
| 3 | * Texas Instruments, <www.ti.com> | |
| 4 | * | |
| 5 | * Authors: | |
| 6 | * Aneesh V <aneesh@ti.com> | |
| 508a58fa | 7 | * Sricharan R <r.sricharan@ti.com> |
| d34efc76 | 8 | * |
| 1a459660 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
| d34efc76 SS |
10 | */ |
| 11 | ||
| 508a58fa S |
12 | #ifndef _OMAP5_H_ |
| 13 | #define _OMAP5_H_ | |
| d34efc76 SS |
14 | |
| 15 | #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) | |
| 16 | #include <asm/types.h> | |
| 17 | #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ | |
| 18 | ||
| fa2f81b0 TR |
19 | #include <linux/sizes.h> |
| 20 | ||
| d34efc76 SS |
21 | /* |
| 22 | * L4 Peripherals - L4 Wakeup and L4 Core now | |
| 23 | */ | |
| 508a58fa S |
24 | #define OMAP54XX_L4_CORE_BASE 0x4A000000 |
| 25 | #define OMAP54XX_L4_WKUP_BASE 0x4Ae00000 | |
| 26 | #define OMAP54XX_L4_PER_BASE 0x48000000 | |
| 7ca3f9c5 | 27 | |
| 4de28d79 LV |
28 | /* CONTROL ID CODE */ |
| 29 | #define CONTROL_CORE_ID_CODE 0x4A002204 | |
| 30 | #define CONTROL_WKUP_ID_CODE 0x4AE0C204 | |
| 31 | ||
| 3891a54f | 32 | #if defined(CONFIG_DRA7XX) |
| 4de28d79 LV |
33 | #define CONTROL_ID_CODE CONTROL_WKUP_ID_CODE |
| 34 | #else | |
| 35 | #define CONTROL_ID_CODE CONTROL_CORE_ID_CODE | |
| 36 | #endif | |
| ad577c8a | 37 | |
| 3891a54f | 38 | #if defined(CONFIG_DRA7XX) |
| a17188c1 KVA |
39 | #define DRA7_USB_OTG_SS1_BASE 0x48890000 |
| 40 | #define DRA7_USB_OTG_SS1_GLUE_BASE 0x48880000 | |
| 41 | #define DRA7_USB3_PHY1_PLL_CTRL 0x4A084C00 | |
| 42 | #define DRA7_USB3_PHY1_POWER 0x4A002370 | |
| 43 | #define DRA7_USB2_PHY1_POWER 0x4A002300 | |
| 44 | ||
| 45 | #define DRA7_USB_OTG_SS2_BASE 0x488D0000 | |
| 46 | #define DRA7_USB_OTG_SS2_GLUE_BASE 0x488C0000 | |
| 47 | #define DRA7_USB2_PHY2_POWER 0x4A002E74 | |
| 7ba792c0 KVA |
48 | #else |
| 49 | #define OMAP5XX_USB_OTG_SS_BASE 0x4A030000 | |
| 50 | #define OMAP5XX_USB_OTG_SS_GLUE_BASE 0x4A020000 | |
| 51 | #define OMAP5XX_USB3_PHY_PLL_CTRL 0x4A084C00 | |
| 52 | #define OMAP5XX_USB3_PHY_POWER 0x4A002370 | |
| 53 | #define OMAP5XX_USB2_PHY_POWER 0x4A002300 | |
| a17188c1 KVA |
54 | #endif |
| 55 | ||
| 508a58fa | 56 | /* To be verified */ |
| 0a0bf7b2 | 57 | #define OMAP5430_CONTROL_ID_CODE_ES1_0 0x0B94202F |
| eed7c0f7 | 58 | #define OMAP5430_CONTROL_ID_CODE_ES2_0 0x1B94202F |
| 0a0bf7b2 | 59 | #define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F |
| eed7c0f7 | 60 | #define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F |
| de62688b | 61 | #define DRA752_CONTROL_ID_CODE_ES1_0 0x0B99002F |
| 3ac8c0bf | 62 | #define DRA752_CONTROL_ID_CODE_ES1_1 0x1B99002F |
| c1ea3bec | 63 | #define DRA752_CONTROL_ID_CODE_ES2_0 0x2B99002F |
| ee77a238 | 64 | #define DRA722_CONTROL_ID_CODE_ES1_0 0x0B9BC02F |
| d851ad3a | 65 | #define DRA722_CONTROL_ID_CODE_ES2_0 0x1B9BC02F |
| ad577c8a | 66 | |
| d34efc76 | 67 | /* UART */ |
| 508a58fa S |
68 | #define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000) |
| 69 | #define UART2_BASE (OMAP54XX_L4_PER_BASE + 0x6c000) | |
| 70 | #define UART3_BASE (OMAP54XX_L4_PER_BASE + 0x20000) | |
| 4b5d3839 | 71 | #define UART4_BASE (OMAP54XX_L4_PER_BASE + 0x6e000) |
| d34efc76 SS |
72 | |
| 73 | /* General Purpose Timers */ | |
| 508a58fa S |
74 | #define GPT1_BASE (OMAP54XX_L4_WKUP_BASE + 0x18000) |
| 75 | #define GPT2_BASE (OMAP54XX_L4_PER_BASE + 0x32000) | |
| 76 | #define GPT3_BASE (OMAP54XX_L4_PER_BASE + 0x34000) | |
| d34efc76 SS |
77 | |
| 78 | /* Watchdog Timer2 - MPU watchdog */ | |
| 508a58fa | 79 | #define WDT2_BASE (OMAP54XX_L4_WKUP_BASE + 0x14000) |
| d34efc76 | 80 | |
| c97a9b32 MP |
81 | /* QSPI */ |
| 82 | #define QSPI_BASE 0x4B300000 | |
| 83 | ||
| 8ffcf74b RQ |
84 | /* SATA */ |
| 85 | #define DWC_AHSATA_BASE 0x4A140000 | |
| 86 | ||
| d34efc76 SS |
87 | /* |
| 88 | * Hardware Register Details | |
| 89 | */ | |
| 90 | ||
| 91 | /* Watchdog Timer */ | |
| 92 | #define WD_UNLOCK1 0xAAAA | |
| 93 | #define WD_UNLOCK2 0x5555 | |
| 94 | ||
| 95 | /* GP Timer */ | |
| 96 | #define TCLR_ST (0x1 << 0) | |
| 97 | #define TCLR_AR (0x1 << 1) | |
| 98 | #define TCLR_PRE (0x1 << 5) | |
| 99 | ||
| 4ecfcfaa A |
100 | /* Control Module */ |
| 101 | #define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5) | |
| 102 | #define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f | |
| 103 | #define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110 | |
| 104 | #define CONTROL_EFUSE_2_OVERRIDE 0x00084000 | |
| 105 | ||
| 106 | /* LPDDR2 IO regs */ | |
| 107 | #define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C | |
| 108 | #define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E | |
| 109 | #define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C | |
| 110 | #define LPDDR2IO_GR10_WD_MASK (3 << 17) | |
| 111 | #define CONTROL_LPDDR2IO_3_VAL 0xA0888C00 | |
| 112 | ||
| 113 | /* CONTROL_EFUSE_2 */ | |
| 114 | #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000 | |
| 115 | ||
| a5d439c2 | 116 | #define SDCARD_BIAS_PWRDNZ (1 << 27) |
| dd23e59d B |
117 | #define SDCARD_PWRDNZ (1 << 26) |
| 118 | #define SDCARD_BIAS_HIZ_MODE (1 << 25) | |
| dd23e59d | 119 | #define SDCARD_PBIASLITE_VMODE (1 << 21) |
| 14fa2dd0 | 120 | |
| d34efc76 SS |
121 | #ifndef __ASSEMBLY__ |
| 122 | ||
| 123 | struct s32ktimer { | |
| 124 | unsigned char res[0x10]; | |
| 125 | unsigned int s32k_cr; /* 0x10 */ | |
| 126 | }; | |
| 127 | ||
| c1fa3c37 S |
128 | #define DEVICE_TYPE_SHIFT 0x6 |
| 129 | #define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT) | |
| 130 | #define DEVICE_GP 0x3 | |
| 131 | ||
| 6ad8d67d S |
132 | /* Output impedance control */ |
| 133 | #define ds_120_ohm 0x0 | |
| 134 | #define ds_60_ohm 0x1 | |
| 135 | #define ds_45_ohm 0x2 | |
| 136 | #define ds_30_ohm 0x3 | |
| 137 | #define ds_mask 0x3 | |
| 138 | ||
| 139 | /* Slew rate control */ | |
| 140 | #define sc_slow 0x0 | |
| 141 | #define sc_medium 0x1 | |
| 142 | #define sc_fast 0x2 | |
| 143 | #define sc_na 0x3 | |
| 144 | #define sc_mask 0x3 | |
| 145 | ||
| 146 | /* Target capacitance control */ | |
| 147 | #define lb_5_12_pf 0x0 | |
| 148 | #define lb_12_25_pf 0x1 | |
| 149 | #define lb_25_50_pf 0x2 | |
| 150 | #define lb_50_80_pf 0x3 | |
| 151 | #define lb_mask 0x3 | |
| 152 | ||
| 153 | #define usb_i_mask 0x7 | |
| 154 | ||
| 155 | #define DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN 0x80828082 | |
| 156 | #define DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN 0x82828200 | |
| 157 | #define DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL 0x8421 | |
| 158 | #define DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL 0x8421084 | |
| 159 | #define DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL 0x8421000 | |
| 160 | ||
| eb4e18e8 LV |
161 | #define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL 0x7C7C7C6C |
| 162 | #define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL 0x64646464 | |
| 163 | #define DDR_IO_0_VREF_CELLS_DDR3_VALUE 0xBAE8C631 | |
| 164 | #define DDR_IO_1_VREF_CELLS_DDR3_VALUE 0xBC6318DC | |
| 165 | #define DDR_IO_2_VREF_CELLS_DDR3_VALUE 0x0 | |
| 166 | ||
| 9100edec | 167 | #define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x7C7C7C7C |
| 42d4f37b | 168 | #define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64646464 |
| 9100edec | 169 | #define DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2 0xBAE8C631 |
| 42d4f37b | 170 | #define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xBC6318DC |
| 9100edec LV |
171 | #define DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2 0x84210000 |
| 172 | ||
| 6ad8d67d S |
173 | #define EFUSE_1 0x45145100 |
| 174 | #define EFUSE_2 0x45145100 | |
| 175 | #define EFUSE_3 0x45145100 | |
| 176 | #define EFUSE_4 0x45145100 | |
| d34efc76 SS |
177 | #endif /* __ASSEMBLY__ */ |
| 178 | ||
| c3799fce TR |
179 | /* |
| 180 | * In all cases, the TRM defines the RAM Memory Map for the processor | |
| 181 | * and indicates the area for the downloaded image. We use all of that | |
| 182 | * space for download and once up and running may use other parts of the | |
| 183 | * map for our needs. We set a scratch space that is at the end of the | |
| 184 | * OMAP5 download area, but within the DRA7xx download area (as it is | |
| 185 | * much larger) and do not, at this time, make use of the additional | |
| 186 | * space. | |
| 187 | */ | |
| 3891a54f | 188 | #if defined(CONFIG_DRA7XX) |
| 81ede187 S |
189 | #define NON_SECURE_SRAM_START 0x40300000 |
| 190 | #define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */ | |
| fa2f81b0 | 191 | #define NON_SECURE_SRAM_IMG_END 0x4037E000 |
| 81ede187 | 192 | #else |
| 47c50143 | 193 | #define NON_SECURE_SRAM_START 0x40300000 |
| 508a58fa | 194 | #define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */ |
| fa2f81b0 | 195 | #define NON_SECURE_SRAM_IMG_END 0x4031E000 |
| 81ede187 | 196 | #endif |
| fa2f81b0 | 197 | #define SRAM_SCRATCH_SPACE_ADDR (NON_SECURE_SRAM_IMG_END - SZ_1K) |
| 81ede187 | 198 | |
| d34efc76 | 199 | /* base address for indirect vectors (internal boot mode) */ |
| 508a58fa | 200 | #define SRAM_ROM_VECT_BASE 0x4031F000 |
| 508a58fa | 201 | |
| d4d986ee LV |
202 | /* CONTROL_SRCOMP_XXX_SIDE */ |
| 203 | #define OVERRIDE_XS_SHIFT 30 | |
| 204 | #define OVERRIDE_XS_MASK (1 << 30) | |
| 205 | #define SRCODE_READ_XS_SHIFT 12 | |
| 206 | #define SRCODE_READ_XS_MASK (0xff << 12) | |
| 207 | #define PWRDWN_XS_SHIFT 11 | |
| 208 | #define PWRDWN_XS_MASK (1 << 11) | |
| 209 | #define DIVIDE_FACTOR_XS_SHIFT 4 | |
| 210 | #define DIVIDE_FACTOR_XS_MASK (0x7f << 4) | |
| 211 | #define MULTIPLY_FACTOR_XS_SHIFT 1 | |
| 212 | #define MULTIPLY_FACTOR_XS_MASK (0x7 << 1) | |
| 213 | #define SRCODE_OVERRIDE_SEL_XS_SHIFT 0 | |
| 214 | #define SRCODE_OVERRIDE_SEL_XS_MASK (1 << 0) | |
| 215 | ||
| 4d0df9c1 AT |
216 | /* ABB settings */ |
| 217 | #define OMAP_ABB_SETTLING_TIME 50 | |
| 218 | #define OMAP_ABB_CLOCK_CYCLES 16 | |
| 219 | ||
| 220 | /* ABB tranxdone mask */ | |
| 221 | #define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 7) | |
| a818097a | 222 | #define OMAP_ABB_MM_TXDONE_MASK (0x1 << 31) |
| e52e334e NM |
223 | #define OMAP_ABB_IVA_TXDONE_MASK (0x1 << 30) |
| 224 | #define OMAP_ABB_EVE_TXDONE_MASK (0x1 << 29) | |
| 225 | #define OMAP_ABB_GPU_TXDONE_MASK (0x1 << 28) | |
| 4d0df9c1 AT |
226 | |
| 227 | /* ABB efuse masks */ | |
| 228 | #define OMAP5_ABB_FUSE_VSET_MASK (0x1F << 24) | |
| 229 | #define OMAP5_ABB_FUSE_ENABLE_MASK (0x1 << 29) | |
| 194dd74a NM |
230 | #define DRA7_ABB_FUSE_VSET_MASK (0x1F << 20) |
| 231 | #define DRA7_ABB_FUSE_ENABLE_MASK (0x1 << 25) | |
| 4d0df9c1 AT |
232 | #define OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK (0x1 << 10) |
| 233 | #define OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK (0x1f << 0) | |
| 234 | ||
| 78f455c0 | 235 | #ifndef __ASSEMBLY__ |
| d4d986ee LV |
236 | struct srcomp_params { |
| 237 | s8 divide_factor; | |
| 238 | s8 multiply_factor; | |
| 239 | }; | |
| 240 | ||
| ef1697e9 LV |
241 | struct ctrl_ioregs { |
| 242 | u32 ctrl_ddrch; | |
| 243 | u32 ctrl_lpddr2ch; | |
| 244 | u32 ctrl_ddr3ch; | |
| 245 | u32 ctrl_ddrio_0; | |
| 246 | u32 ctrl_ddrio_1; | |
| 247 | u32 ctrl_ddrio_2; | |
| 248 | u32 ctrl_emif_sdram_config_ext; | |
| 6c70935d | 249 | u32 ctrl_emif_sdram_config_ext_final; |
| 92b0482c | 250 | u32 ctrl_ddr_ctrl_ext_0; |
| ef1697e9 | 251 | }; |
| b1e26e3b | 252 | |
| 76cff2b1 NM |
253 | void clrset_spare_register(u8 spare_type, u32 clear_bits, u32 set_bits); |
| 254 | ||
| 78f455c0 | 255 | #endif /* __ASSEMBLY__ */ |
| 60c7c30a PK |
256 | |
| 257 | /* Boot parameters */ | |
| 258 | #ifndef __ASSEMBLY__ | |
| 259 | struct omap_boot_parameters { | |
| 260 | unsigned int boot_message; | |
| 261 | unsigned int boot_device_descriptor; | |
| 262 | unsigned char boot_device; | |
| 263 | unsigned char reset_reason; | |
| 264 | unsigned char ch_flags; | |
| 265 | }; | |
| 266 | #endif | |
| 267 | ||
| d34efc76 | 268 | #endif |