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bd0550fc NI |
1 | /* |
2 | * arch/arm/include/asm/arch-rmobile/r8a7791.h | |
bd0550fc NI |
3 | * |
4 | * Copyright (C) 2013 Renesas Electronics Corporation | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0 | |
7 | */ | |
8 | ||
9 | #ifndef __ASM_ARCH_R8A7791_H | |
10 | #define __ASM_ARCH_R8A7791_H | |
11 | ||
12 | /* | |
13 | * R8A7791 I/O Addresses | |
14 | */ | |
15 | #define RWDT_BASE 0xE6020000 | |
16 | #define SWDT_BASE 0xE6030000 | |
17 | #define LBSC_BASE 0xFEC00200 | |
18 | #define DBSC3_0_BASE 0xE6790000 | |
19 | #define DBSC3_1_BASE 0xE67A0000 | |
20 | #define TMU_BASE 0xE61E0000 | |
21 | #define GPIO5_BASE 0xE6055000 | |
82852762 | 22 | #define SH_QSPI_BASE 0xE6B10000 |
bd0550fc NI |
23 | |
24 | #define S3C_BASE 0xE6784000 | |
25 | #define S3C_INT_BASE 0xE6784A00 | |
26 | #define S3C_MEDIA_BASE 0xE6784B00 | |
27 | ||
28 | #define S3C_QOS_DCACHE_BASE 0xE6784BDC | |
29 | #define S3C_QOS_CCI0_BASE 0xE6784C00 | |
30 | #define S3C_QOS_CCI1_BASE 0xE6784C24 | |
31 | #define S3C_QOS_MXI_BASE 0xE6784C48 | |
32 | #define S3C_QOS_AXI_BASE 0xE6784C6C | |
33 | ||
34 | #define DBSC3_0_QOS_R0_BASE 0xE6791000 | |
35 | #define DBSC3_0_QOS_R1_BASE 0xE6791100 | |
36 | #define DBSC3_0_QOS_R2_BASE 0xE6791200 | |
37 | #define DBSC3_0_QOS_R3_BASE 0xE6791300 | |
38 | #define DBSC3_0_QOS_R4_BASE 0xE6791400 | |
39 | #define DBSC3_0_QOS_R5_BASE 0xE6791500 | |
40 | #define DBSC3_0_QOS_R6_BASE 0xE6791600 | |
41 | #define DBSC3_0_QOS_R7_BASE 0xE6791700 | |
42 | #define DBSC3_0_QOS_R8_BASE 0xE6791800 | |
43 | #define DBSC3_0_QOS_R9_BASE 0xE6791900 | |
44 | #define DBSC3_0_QOS_R10_BASE 0xE6791A00 | |
45 | #define DBSC3_0_QOS_R11_BASE 0xE6791B00 | |
46 | #define DBSC3_0_QOS_R12_BASE 0xE6791C00 | |
47 | #define DBSC3_0_QOS_R13_BASE 0xE6791D00 | |
48 | #define DBSC3_0_QOS_R14_BASE 0xE6791E00 | |
49 | #define DBSC3_0_QOS_R15_BASE 0xE6791F00 | |
50 | #define DBSC3_0_QOS_W0_BASE 0xE6792000 | |
51 | #define DBSC3_0_QOS_W1_BASE 0xE6792100 | |
52 | #define DBSC3_0_QOS_W2_BASE 0xE6792200 | |
53 | #define DBSC3_0_QOS_W3_BASE 0xE6792300 | |
54 | #define DBSC3_0_QOS_W4_BASE 0xE6792400 | |
55 | #define DBSC3_0_QOS_W5_BASE 0xE6792500 | |
56 | #define DBSC3_0_QOS_W6_BASE 0xE6792600 | |
57 | #define DBSC3_0_QOS_W7_BASE 0xE6792700 | |
58 | #define DBSC3_0_QOS_W8_BASE 0xE6792800 | |
59 | #define DBSC3_0_QOS_W9_BASE 0xE6792900 | |
60 | #define DBSC3_0_QOS_W10_BASE 0xE6792A00 | |
61 | #define DBSC3_0_QOS_W11_BASE 0xE6792B00 | |
62 | #define DBSC3_0_QOS_W12_BASE 0xE6792C00 | |
63 | #define DBSC3_0_QOS_W13_BASE 0xE6792D00 | |
64 | #define DBSC3_0_QOS_W14_BASE 0xE6792E00 | |
65 | #define DBSC3_0_QOS_W15_BASE 0xE6792F00 | |
66 | ||
1251e490 NI |
67 | #define DBSC3_1_QOS_R0_BASE 0xE67A1000 |
68 | #define DBSC3_1_QOS_R1_BASE 0xE67A1100 | |
69 | #define DBSC3_1_QOS_R2_BASE 0xE67A1200 | |
70 | #define DBSC3_1_QOS_R3_BASE 0xE67A1300 | |
71 | #define DBSC3_1_QOS_R4_BASE 0xE67A1400 | |
72 | #define DBSC3_1_QOS_R5_BASE 0xE67A1500 | |
73 | #define DBSC3_1_QOS_R6_BASE 0xE67A1600 | |
74 | #define DBSC3_1_QOS_R7_BASE 0xE67A1700 | |
75 | #define DBSC3_1_QOS_R8_BASE 0xE67A1800 | |
76 | #define DBSC3_1_QOS_R9_BASE 0xE67A1900 | |
77 | #define DBSC3_1_QOS_R10_BASE 0xE67A1A00 | |
78 | #define DBSC3_1_QOS_R11_BASE 0xE67A1B00 | |
79 | #define DBSC3_1_QOS_R12_BASE 0xE67A1C00 | |
80 | #define DBSC3_1_QOS_R13_BASE 0xE67A1D00 | |
81 | #define DBSC3_1_QOS_R14_BASE 0xE67A1E00 | |
82 | #define DBSC3_1_QOS_R15_BASE 0xE67A1F00 | |
83 | #define DBSC3_1_QOS_W0_BASE 0xE67A2000 | |
84 | #define DBSC3_1_QOS_W1_BASE 0xE67A2100 | |
85 | #define DBSC3_1_QOS_W2_BASE 0xE67A2200 | |
86 | #define DBSC3_1_QOS_W3_BASE 0xE67A2300 | |
87 | #define DBSC3_1_QOS_W4_BASE 0xE67A2400 | |
88 | #define DBSC3_1_QOS_W5_BASE 0xE67A2500 | |
89 | #define DBSC3_1_QOS_W6_BASE 0xE67A2600 | |
90 | #define DBSC3_1_QOS_W7_BASE 0xE67A2700 | |
91 | #define DBSC3_1_QOS_W8_BASE 0xE67A2800 | |
92 | #define DBSC3_1_QOS_W9_BASE 0xE67A2900 | |
93 | #define DBSC3_1_QOS_W10_BASE 0xE67A2A00 | |
94 | #define DBSC3_1_QOS_W11_BASE 0xE67A2B00 | |
95 | #define DBSC3_1_QOS_W12_BASE 0xE67A2C00 | |
96 | #define DBSC3_1_QOS_W13_BASE 0xE67A2D00 | |
97 | #define DBSC3_1_QOS_W14_BASE 0xE67A2E00 | |
98 | #define DBSC3_1_QOS_W15_BASE 0xE67A2F00 | |
99 | ||
100 | #define DBSC3_0_DBADJ2 0xE67900C8 | |
101 | ||
bd0550fc NI |
102 | #define CCI_400_MAXOT_1 0xF0091110 |
103 | #define CCI_400_MAXOT_2 0xF0092110 | |
104 | #define CCI_400_QOSCNTL_1 0xF009110C | |
105 | #define CCI_400_QOSCNTL_2 0xF009210C | |
106 | ||
107 | #define MXI_BASE 0xFE960000 | |
1251e490 | 108 | #define MXI_QOS_BASE 0xFE960300 |
bd0550fc NI |
109 | |
110 | #define SYS_AXI_SYX64TO128_BASE 0xFF800300 | |
111 | #define SYS_AXI_AVB_BASE 0xFF800340 | |
112 | #define SYS_AXI_G2D_BASE 0xFF800540 | |
113 | #define SYS_AXI_IMP0_BASE 0xFF800580 | |
114 | #define SYS_AXI_IMP1_BASE 0xFF8005C0 | |
115 | #define SYS_AXI_IMUX0_BASE 0xFF800600 | |
116 | #define SYS_AXI_IMUX1_BASE 0xFF800640 | |
117 | #define SYS_AXI_IMUX2_BASE 0xFF800680 | |
118 | #define SYS_AXI_LBS_BASE 0xFF8006C0 | |
119 | #define SYS_AXI_MMUDS_BASE 0xFF800700 | |
120 | #define SYS_AXI_MMUM_BASE 0xFF800740 | |
121 | #define SYS_AXI_MMUR_BASE 0xFF800780 | |
122 | #define SYS_AXI_MMUS0_BASE 0xFF8007C0 | |
123 | #define SYS_AXI_MMUS1_BASE 0xFF800800 | |
124 | #define SYS_AXI_MTSB0_BASE 0xFF800880 | |
125 | #define SYS_AXI_MTSB1_BASE 0xFF8008C0 | |
126 | #define SYS_AXI_PCI_BASE 0xFF800900 | |
127 | #define SYS_AXI_RTX_BASE 0xFF800940 | |
128 | #define SYS_AXI_SDS0_BASE 0xFF800A80 | |
129 | #define SYS_AXI_SDS1_BASE 0xFF800AC0 | |
130 | #define SYS_AXI_USB20_BASE 0xFF800C00 | |
131 | #define SYS_AXI_USB21_BASE 0xFF800C40 | |
132 | #define SYS_AXI_USB22_BASE 0xFF800C80 | |
133 | #define SYS_AXI_USB30_BASE 0xFF800CC0 | |
1251e490 NI |
134 | #define SYS_AXI_AX2M_BASE 0xFF800380 |
135 | #define SYS_AXI_CC50_BASE 0xFF8003C0 | |
136 | #define SYS_AXI_CCI_BASE 0xFF800440 | |
137 | #define SYS_AXI_CS_BASE 0xFF800480 | |
138 | #define SYS_AXI_DDM_BASE 0xFF8004C0 | |
139 | #define SYS_AXI_ETH_BASE 0xFF800500 | |
140 | #define SYS_AXI_MPXM_BASE 0xFF800840 | |
141 | #define SYS_AXI_SAT0_BASE 0xFF800980 | |
142 | #define SYS_AXI_SAT1_BASE 0xFF8009C0 | |
143 | #define SYS_AXI_SDM0_BASE 0xFF800A00 | |
144 | #define SYS_AXI_SDM1_BASE 0xFF800A40 | |
145 | #define SYS_AXI_TRAB_BASE 0xFF800B00 | |
146 | #define SYS_AXI_UDM0_BASE 0xFF800B80 | |
147 | #define SYS_AXI_UDM1_BASE 0xFF800BC0 | |
bd0550fc NI |
148 | |
149 | #define RT_AXI_SHX_BASE 0xFF810100 | |
1251e490 NI |
150 | #define RT_AXI_DBG_BASE 0xFF810140 |
151 | #define RT_AXI_RDM_BASE 0xFF810180 | |
bd0550fc NI |
152 | #define RT_AXI_RDS_BASE 0xFF8101C0 |
153 | #define RT_AXI_RTX64TO128_BASE 0xFF810200 | |
154 | #define RT_AXI_STPRO_BASE 0xFF810240 | |
1251e490 | 155 | #define RT_AXI_SY2RT_BASE 0xFF810280 |
bd0550fc NI |
156 | |
157 | #define MP_AXI_ADSP_BASE 0xFF820100 | |
158 | #define MP_AXI_ASDS0_BASE 0xFF8201C0 | |
159 | #define MP_AXI_ASDS1_BASE 0xFF820200 | |
160 | #define MP_AXI_MLP_BASE 0xFF820240 | |
161 | #define MP_AXI_MMUMP_BASE 0xFF820280 | |
162 | #define MP_AXI_SPU_BASE 0xFF8202C0 | |
163 | #define MP_AXI_SPUC_BASE 0xFF820300 | |
164 | ||
165 | #define SYS_AXI256_AXI128TO256_BASE 0xFF860100 | |
166 | #define SYS_AXI256_SYX_BASE 0xFF860140 | |
167 | #define SYS_AXI256_MPX_BASE 0xFF860180 | |
168 | #define SYS_AXI256_MXI_BASE 0xFF8601C0 | |
169 | ||
170 | #define CCI_AXI_MMUS0_BASE 0xFF880100 | |
171 | #define CCI_AXI_SYX2_BASE 0xFF880140 | |
172 | #define CCI_AXI_MMUR_BASE 0xFF880180 | |
173 | #define CCI_AXI_MMUDS_BASE 0xFF8801C0 | |
174 | #define CCI_AXI_MMUM_BASE 0xFF880200 | |
175 | #define CCI_AXI_MXI_BASE 0xFF880240 | |
176 | #define CCI_AXI_MMUS1_BASE 0xFF880280 | |
177 | #define CCI_AXI_MMUMP_BASE 0xFF8802C0 | |
178 | ||
1251e490 NI |
179 | #define MEDIA_AXI_MXR_BASE 0xFE960080 |
180 | #define MEDIA_AXI_MXW_BASE 0xFE9600C0 | |
bd0550fc NI |
181 | #define MEDIA_AXI_JPR_BASE 0xFE964100 |
182 | #define MEDIA_AXI_JPW_BASE 0xFE966100 | |
183 | #define MEDIA_AXI_GCU0R_BASE 0xFE964140 | |
184 | #define MEDIA_AXI_GCU0W_BASE 0xFE966140 | |
185 | #define MEDIA_AXI_GCU1R_BASE 0xFE964180 | |
186 | #define MEDIA_AXI_GCU1W_BASE 0xFE966180 | |
187 | #define MEDIA_AXI_TDMR_BASE 0xFE964500 | |
188 | #define MEDIA_AXI_TDMW_BASE 0xFE966500 | |
189 | #define MEDIA_AXI_VSP0CR_BASE 0xFE964540 | |
190 | #define MEDIA_AXI_VSP0CW_BASE 0xFE966540 | |
191 | #define MEDIA_AXI_VSP1CR_BASE 0xFE964580 | |
192 | #define MEDIA_AXI_VSP1CW_BASE 0xFE966580 | |
193 | #define MEDIA_AXI_VSPDU0CR_BASE 0xFE9645C0 | |
194 | #define MEDIA_AXI_VSPDU0CW_BASE 0xFE9665C0 | |
195 | #define MEDIA_AXI_VSPDU1CR_BASE 0xFE964600 | |
196 | #define MEDIA_AXI_VSPDU1CW_BASE 0xFE966600 | |
197 | #define MEDIA_AXI_VIN0W_BASE 0xFE966900 | |
198 | #define MEDIA_AXI_VSP0R_BASE 0xFE964D00 | |
199 | #define MEDIA_AXI_VSP0W_BASE 0xFE966D00 | |
200 | #define MEDIA_AXI_FDP0R_BASE 0xFE964D40 | |
201 | #define MEDIA_AXI_FDP0W_BASE 0xFE966D40 | |
202 | #define MEDIA_AXI_IMSR_BASE 0xFE964D80 | |
203 | #define MEDIA_AXI_IMSW_BASE 0xFE966D80 | |
204 | #define MEDIA_AXI_VSP1R_BASE 0xFE965100 | |
205 | #define MEDIA_AXI_VSP1W_BASE 0xFE967100 | |
206 | #define MEDIA_AXI_FDP1R_BASE 0xFE965140 | |
207 | #define MEDIA_AXI_FDP1W_BASE 0xFE967140 | |
208 | #define MEDIA_AXI_IMRR_BASE 0xFE965180 | |
209 | #define MEDIA_AXI_IMRW_BASE 0xFE967180 | |
210 | #define MEDIA_AXI_FDP2R_BASE 0xFE9651C0 | |
211 | #define MEDIA_AXI_FDP2W_BASE 0xFE966DC0 | |
212 | #define MEDIA_AXI_VSPD0R_BASE 0xFE965500 | |
213 | #define MEDIA_AXI_VSPD0W_BASE 0xFE967500 | |
214 | #define MEDIA_AXI_VSPD1R_BASE 0xFE965540 | |
215 | #define MEDIA_AXI_VSPD1W_BASE 0xFE967540 | |
216 | #define MEDIA_AXI_DU0R_BASE 0xFE965580 | |
217 | #define MEDIA_AXI_DU0W_BASE 0xFE967580 | |
218 | #define MEDIA_AXI_DU1R_BASE 0xFE9655C0 | |
219 | #define MEDIA_AXI_DU1W_BASE 0xFE9675C0 | |
220 | #define MEDIA_AXI_VCP0CR_BASE 0xFE965900 | |
221 | #define MEDIA_AXI_VCP0CW_BASE 0xFE967900 | |
222 | #define MEDIA_AXI_VCP0VR_BASE 0xFE965940 | |
223 | #define MEDIA_AXI_VCP0VW_BASE 0xFE967940 | |
224 | #define MEDIA_AXI_VPC0R_BASE 0xFE965980 | |
225 | #define MEDIA_AXI_VCP1CR_BASE 0xFE965D00 | |
226 | #define MEDIA_AXI_VCP1CW_BASE 0xFE967D00 | |
227 | #define MEDIA_AXI_VCP1VR_BASE 0xFE965D40 | |
228 | #define MEDIA_AXI_VCP1VW_BASE 0xFE967D40 | |
229 | #define MEDIA_AXI_VPC1R_BASE 0xFE965D80 | |
230 | ||
231 | #define SYS_AXI_AVBDMSCR 0xFF802000 | |
232 | #define SYS_AXI_SYX2DMSCR 0xFF802004 | |
233 | #define SYS_AXI_CC50DMSCR 0xFF802008 | |
234 | #define SYS_AXI_CC51DMSCR 0xFF80200C | |
235 | #define SYS_AXI_CCIDMSCR 0xFF802010 | |
236 | #define SYS_AXI_CSDMSCR 0xFF802014 | |
237 | #define SYS_AXI_DDMDMSCR 0xFF802018 | |
238 | #define SYS_AXI_ETHDMSCR 0xFF80201C | |
239 | #define SYS_AXI_G2DDMSCR 0xFF802020 | |
240 | #define SYS_AXI_IMP0DMSCR 0xFF802024 | |
241 | #define SYS_AXI_IMP1DMSCR 0xFF802028 | |
242 | #define SYS_AXI_LBSDMSCR 0xFF80202C | |
243 | #define SYS_AXI_MMUDSDMSCR 0xFF802030 | |
244 | #define SYS_AXI_MMUMXDMSCR 0xFF802034 | |
245 | #define SYS_AXI_MMURDDMSCR 0xFF802038 | |
246 | #define SYS_AXI_MMUS0DMSCR 0xFF80203C | |
247 | #define SYS_AXI_MMUS1DMSCR 0xFF802040 | |
248 | #define SYS_AXI_MPXDMSCR 0xFF802044 | |
249 | #define SYS_AXI_MTSB0DMSCR 0xFF802048 | |
250 | #define SYS_AXI_MTSB1DMSCR 0xFF80204C | |
251 | #define SYS_AXI_PCIDMSCR 0xFF802050 | |
252 | #define SYS_AXI_RTXDMSCR 0xFF802054 | |
253 | #define SYS_AXI_SAT0DMSCR 0xFF802058 | |
254 | #define SYS_AXI_SAT1DMSCR 0xFF80205C | |
255 | #define SYS_AXI_SDM0DMSCR 0xFF802060 | |
256 | #define SYS_AXI_SDM1DMSCR 0xFF802064 | |
257 | #define SYS_AXI_SDS0DMSCR 0xFF802068 | |
258 | #define SYS_AXI_SDS1DMSCR 0xFF80206C | |
259 | #define SYS_AXI_ETRABDMSCR 0xFF802070 | |
260 | #define SYS_AXI_ETRKFDMSCR 0xFF802074 | |
261 | #define SYS_AXI_UDM0DMSCR 0xFF802078 | |
262 | #define SYS_AXI_UDM1DMSCR 0xFF80207C | |
263 | #define SYS_AXI_USB20DMSCR 0xFF802080 | |
264 | #define SYS_AXI_USB21DMSCR 0xFF802084 | |
265 | #define SYS_AXI_USB22DMSCR 0xFF802088 | |
266 | #define SYS_AXI_USB30DMSCR 0xFF80208C | |
267 | #define SYS_AXI_X128TO64SLVDMSCR 0xFF802100 | |
268 | #define SYS_AXI_X64TO128SLVDMSCR 0xFF802104 | |
269 | #define SYS_AXI_AVBSLVDMSCR 0xFF802108 | |
270 | #define SYS_AXI_SYX2SLVDMSCR 0xFF80210C | |
271 | #define SYS_AXI_ETHSLVDMSCR 0xFF802110 | |
272 | #define SYS_AXI_GICSLVDMSCR 0xFF802114 | |
273 | #define SYS_AXI_IMPSLVDMSCR 0xFF802118 | |
274 | #define SYS_AXI_IMX0SLVDMSCR 0xFF80211C | |
275 | #define SYS_AXI_IMX1SLVDMSCR 0xFF802120 | |
276 | #define SYS_AXI_IMX2SLVDMSCR 0xFF802124 | |
277 | #define SYS_AXI_LBSSLVDMSCR 0xFF802128 | |
278 | #define SYS_AXI_MMC0SLVDMSCR 0xFF80212C | |
279 | #define SYS_AXI_MMC1SLVDMSCR 0xFF802130 | |
280 | #define SYS_AXI_MPXSLVDMSCR 0xFF802134 | |
281 | #define SYS_AXI_MTSB0SLVDMSCR 0xFF802138 | |
282 | #define SYS_AXI_MTSB1SLVDMSCR 0xFF80213C | |
283 | #define SYS_AXI_MXTSLVDMSCR 0xFF802140 | |
284 | #define SYS_AXI_PCISLVDMSCR 0xFF802144 | |
285 | #define SYS_AXI_SYAPBSLVDMSCR 0xFF802148 | |
286 | #define SYS_AXI_QSAPBSLVDMSCR 0xFF80214C | |
287 | #define SYS_AXI_RTXSLVDMSCR 0xFF802150 | |
288 | #define SYS_AXI_SAT0SLVDMSCR 0xFF802168 | |
289 | #define SYS_AXI_SAT1SLVDMSCR 0xFF80216C | |
290 | #define SYS_AXI_SDAP0SLVDMSCR 0xFF802170 | |
291 | #define SYS_AXI_SDAP1SLVDMSCR 0xFF802174 | |
292 | #define SYS_AXI_SDAP2SLVDMSCR 0xFF802178 | |
293 | #define SYS_AXI_SDAP3SLVDMSCR 0xFF80217C | |
294 | #define SYS_AXI_SGXSLVDMSCR 0xFF802180 | |
295 | #define SYS_AXI_STBSLVDMSCR 0xFF802188 | |
296 | #define SYS_AXI_STMSLVDMSCR 0xFF80218C | |
297 | #define SYS_AXI_TSPL0SLVDMSCR 0xFF802194 | |
298 | #define SYS_AXI_TSPL1SLVDMSCR 0xFF802198 | |
299 | #define SYS_AXI_TSPL2SLVDMSCR 0xFF80219C | |
300 | #define SYS_AXI_USB20SLVDMSCR 0xFF8021A0 | |
301 | #define SYS_AXI_USB21SLVDMSCR 0xFF8021A4 | |
302 | #define SYS_AXI_USB22SLVDMSCR 0xFF8021A8 | |
303 | #define SYS_AXI_USB30SLVDMSCR 0xFF8021AC | |
304 | ||
305 | #define RT_AXI_CBMDMSCR 0xFF812000 | |
306 | #define RT_AXI_DBDMSCR 0xFF812004 | |
307 | #define RT_AXI_RDMDMSCR 0xFF812008 | |
308 | #define RT_AXI_RDSDMSCR 0xFF81200C | |
309 | #define RT_AXI_STRDMSCR 0xFF812010 | |
310 | #define RT_AXI_SY2RTDMSCR 0xFF812014 | |
311 | #define RT_AXI_CBSSLVDMSCR 0xFF812100 | |
312 | #define RT_AXI_DBSSLVDMSCR 0xFF812104 | |
313 | #define RT_AXI_RTAP1SLVDMSCR 0xFF812108 | |
314 | #define RT_AXI_RTAP2SLVDMSCR 0xFF81210C | |
315 | #define RT_AXI_RTAP3SLVDMSCR 0xFF812110 | |
316 | #define RT_AXI_RT2SYSLVDMSCR 0xFF812114 | |
317 | #define RT_AXI_A128TO64SLVDMSCR 0xFF812118 | |
318 | #define RT_AXI_A64TO128SLVDMSCR 0xFF81211C | |
319 | #define RT_AXI_A64TO128CSLVDMSCR 0xFF812120 | |
320 | #define RT_AXI_UTLBRSLVDMSCR 0xFF812128 | |
321 | ||
322 | #define MP_AXI_ADSPDMSCR 0xFF822000 | |
323 | #define MP_AXI_ASDM0DMSCR 0xFF822004 | |
324 | #define MP_AXI_ASDM1DMSCR 0xFF822008 | |
325 | #define MP_AXI_ASDS0DMSCR 0xFF82200C | |
326 | #define MP_AXI_ASDS1DMSCR 0xFF822010 | |
327 | #define MP_AXI_MLPDMSCR 0xFF822014 | |
328 | #define MP_AXI_MMUMPDMSCR 0xFF822018 | |
329 | #define MP_AXI_SPUDMSCR 0xFF82201C | |
330 | #define MP_AXI_SPUCDMSCR 0xFF822020 | |
331 | #define MP_AXI_SY2MPDMSCR 0xFF822024 | |
332 | #define MP_AXI_ADSPSLVDMSCR 0xFF822100 | |
333 | #define MP_AXI_MLMSLVDMSCR 0xFF822104 | |
334 | #define MP_AXI_MPAP4SLVDMSCR 0xFF822108 | |
335 | #define MP_AXI_MPAP5SLVDMSCR 0xFF82210C | |
336 | #define MP_AXI_MPAP6SLVDMSCR 0xFF822110 | |
337 | #define MP_AXI_MPAP7SLVDMSCR 0xFF822114 | |
338 | #define MP_AXI_MP2SYSLVDMSCR 0xFF822118 | |
339 | #define MP_AXI_MP2SY2SLVDMSCR 0xFF82211C | |
340 | #define MP_AXI_MPXAPSLVDMSCR 0xFF822124 | |
341 | #define MP_AXI_SPUSLVDMSCR 0xFF822128 | |
342 | #define MP_AXI_UTLBMPSLVDMSCR 0xFF82212C | |
343 | ||
344 | #define ADM_AXI_ASDM0DMSCR 0xFF842000 | |
345 | #define ADM_AXI_ASDM1DMSCR 0xFF842004 | |
346 | #define ADM_AXI_MPAP1SLVDMSCR 0xFF842104 | |
347 | #define ADM_AXI_MPAP2SLVDMSCR 0xFF842108 | |
348 | #define ADM_AXI_MPAP3SLVDMSCR 0xFF84210C | |
349 | ||
350 | #define DM_AXI_RDMDMSCR 0xFF852000 | |
351 | #define DM_AXI_SDM0DMSCR 0xFF852004 | |
352 | #define DM_AXI_SDM1DMSCR 0xFF852008 | |
353 | #define DM_AXI_MMAP0SLVDMSCR 0xFF852100 | |
354 | #define DM_AXI_MMAP1SLVDMSCR 0xFF852104 | |
355 | #define DM_AXI_QSPAPSLVDMSCR 0xFF852108 | |
356 | #define DM_AXI_RAP4SLVDMSCR 0xFF85210C | |
357 | #define DM_AXI_RAP5SLVDMSCR 0xFF852110 | |
358 | #define DM_AXI_SAP4SLVDMSCR 0xFF852114 | |
359 | #define DM_AXI_SAP5SLVDMSCR 0xFF852118 | |
360 | #define DM_AXI_SAP6SLVDMSCR 0xFF85211C | |
361 | #define DM_AXI_SAP65SLVDMSCR 0xFF852120 | |
362 | #define DM_AXI_SDAP0SLVDMSCR 0xFF852124 | |
363 | #define DM_AXI_SDAP1SLVDMSCR 0xFF852128 | |
364 | #define DM_AXI_SDAP2SLVDMSCR 0xFF85212C | |
365 | #define DM_AXI_SDAP3SLVDMSCR 0xFF852130 | |
366 | ||
367 | #define SYS_AXI256_SYXDMSCR 0xFF862000 | |
368 | #define SYS_AXI256_MPXDMSCR 0xFF862004 | |
369 | #define SYS_AXI256_MXIDMSCR 0xFF862008 | |
370 | #define SYS_AXI256_X128TO256SLVDMSCR 0xFF862100 | |
371 | #define SYS_AXI256_X256TO128SLVDMSCR 0xFF862104 | |
372 | #define SYS_AXI256_SYXSLVDMSCR 0xFF862108 | |
373 | #define SYS_AXI256_CCXSLVDMSCR 0xFF86210C | |
374 | #define SYS_AXI256_S3CSLVDMSCR 0xFF862110 | |
375 | ||
376 | #define MXT_SYXDMSCR 0xFF872000 | |
377 | #define MXT_CMM0SLVDMSCR 0xFF872100 | |
378 | #define MXT_CMM1SLVDMSCR 0xFF872104 | |
379 | #define MXT_CMM2SLVDMSCR 0xFF872108 | |
380 | #define MXT_FDPSLVDMSCR 0xFF87210C | |
381 | #define MXT_IMRSLVDMSCR 0xFF872110 | |
382 | #define MXT_VINSLVDMSCR 0xFF872114 | |
383 | #define MXT_VPC0SLVDMSCR 0xFF872118 | |
384 | #define MXT_VPC1SLVDMSCR 0xFF87211C | |
385 | #define MXT_VSP0SLVDMSCR 0xFF872120 | |
386 | #define MXT_VSP1SLVDMSCR 0xFF872124 | |
387 | #define MXT_VSPD0SLVDMSCR 0xFF872128 | |
388 | #define MXT_VSPD1SLVDMSCR 0xFF87212C | |
389 | #define MXT_MAP1SLVDMSCR 0xFF872130 | |
390 | #define MXT_MAP2SLVDMSCR 0xFF872134 | |
391 | ||
392 | #define CCI_AXI_MMUS0DMSCR 0xFF882000 | |
393 | #define CCI_AXI_SYX2DMSCR 0xFF882004 | |
394 | #define CCI_AXI_MMURDMSCR 0xFF882008 | |
395 | #define CCI_AXI_MMUDSDMSCR 0xFF88200C | |
396 | #define CCI_AXI_MMUMDMSCR 0xFF882010 | |
397 | #define CCI_AXI_MXIDMSCR 0xFF882014 | |
398 | #define CCI_AXI_MMUS1DMSCR 0xFF882018 | |
399 | #define CCI_AXI_MMUMPDMSCR 0xFF88201C | |
400 | #define CCI_AXI_DVMDMSCR 0xFF882020 | |
401 | #define CCI_AXI_CCISLVDMSCR 0xFF882100 | |
402 | ||
403 | #define CCI_AXI_IPMMUIDVMCR 0xFF880400 | |
404 | #define CCI_AXI_IPMMURDVMCR 0xFF880404 | |
405 | #define CCI_AXI_IPMMUS0DVMCR 0xFF880408 | |
406 | #define CCI_AXI_IPMMUS1DVMCR 0xFF88040C | |
407 | #define CCI_AXI_IPMMUMPDVMCR 0xFF880410 | |
408 | #define CCI_AXI_IPMMUDSDVMCR 0xFF880414 | |
409 | #define CCI_AXI_AX2ADDRMASK 0xFF88041C | |
410 | ||
411 | #ifndef __ASSEMBLY__ | |
412 | #include <asm/types.h> | |
413 | ||
414 | /* RWDT */ | |
415 | struct r8a7791_rwdt { | |
416 | u32 rwtcnt; /* 0x00 */ | |
417 | u32 rwtcsra; /* 0x04 */ | |
418 | u16 rwtcsrb; /* 0x08 */ | |
419 | }; | |
420 | ||
421 | /* SWDT */ | |
422 | struct r8a7791_swdt { | |
423 | u32 swtcnt; /* 0x00 */ | |
424 | u32 swtcsra; /* 0x04 */ | |
425 | u16 swtcsrb; /* 0x08 */ | |
426 | }; | |
427 | ||
428 | /* LBSC */ | |
429 | struct r8a7791_lbsc { | |
430 | u32 cs0ctrl; | |
431 | u32 cs1ctrl; | |
432 | u32 ecs0ctrl; | |
433 | u32 ecs1ctrl; | |
434 | u32 ecs2ctrl; | |
435 | u32 ecs3ctrl; | |
436 | u32 ecs4ctrl; | |
437 | u32 ecs5ctrl; | |
438 | u32 dummy0[4]; /* 0x20 .. 0x2C */ | |
439 | u32 cswcr0; | |
440 | u32 cswcr1; | |
441 | u32 ecswcr0; | |
442 | u32 ecswcr1; | |
443 | u32 ecswcr2; | |
444 | u32 ecswcr3; | |
445 | u32 ecswcr4; | |
446 | u32 ecswcr5; | |
447 | u32 exdmawcr0; | |
448 | u32 exdmawcr1; | |
449 | u32 exdmawcr2; | |
450 | u32 dummy1[9]; /* 0x5C .. 0x7C */ | |
451 | u32 cspwcr0; | |
452 | u32 cspwcr1; | |
453 | u32 ecspwcr0; | |
454 | u32 ecspwcr1; | |
455 | u32 ecspwcr2; | |
456 | u32 ecspwcr3; | |
457 | u32 ecspwcr4; | |
458 | u32 ecspwcr5; | |
459 | u32 exwtsync; | |
460 | u32 dummy2[3]; /* 0xA4 .. 0xAC */ | |
461 | u32 cs0bstctl; | |
462 | u32 cs0btph; | |
463 | u32 dummy3[2]; /* 0xB8 .. 0xBC */ | |
464 | u32 cs1gdst; | |
465 | u32 ecs0gdst; | |
466 | u32 ecs1gdst; | |
467 | u32 ecs2gdst; | |
468 | u32 ecs3gdst; | |
469 | u32 ecs4gdst; | |
470 | u32 ecs5gdst; | |
471 | u32 dummy4[5]; /* 0xDC .. 0xEC */ | |
472 | u32 exdmaset0; | |
473 | u32 exdmaset1; | |
474 | u32 exdmaset2; | |
475 | u32 dummy5[5]; /* 0xFC .. 0x10C */ | |
476 | u32 exdmcr0; | |
477 | u32 exdmcr1; | |
478 | u32 exdmcr2; | |
479 | u32 dummy6[5]; /* 0x11C .. 0x12C */ | |
480 | u32 bcintsr; | |
481 | u32 bcintcr; | |
482 | u32 bcintmr; | |
483 | u32 dummy7; /* 0x13C */ | |
484 | u32 exbatlv; | |
485 | u32 exwtsts; | |
486 | u32 dummy8[14]; /* 0x148 .. 0x17C */ | |
487 | u32 atacsctrl; | |
488 | u32 dummy9[15]; /* 0x184 .. 0x1BC */ | |
489 | u32 exbct; | |
490 | u32 extct; | |
491 | }; | |
492 | ||
493 | /* DBSC3 */ | |
494 | struct r8a7791_dbsc3 { | |
495 | u32 dummy0[3]; /* 0x00 .. 0x08 */ | |
496 | u32 dbstate1; | |
497 | u32 dbacen; | |
498 | u32 dbrfen; | |
499 | u32 dbcmd; | |
500 | u32 dbwait; | |
501 | u32 dbkind; | |
502 | u32 dbconf0; | |
503 | u32 dummy1[2]; /* 0x28 .. 0x2C */ | |
504 | u32 dbphytype; | |
505 | u32 dummy2[3]; /* 0x34 .. 0x3C */ | |
506 | u32 dbtr0; | |
507 | u32 dbtr1; | |
508 | u32 dbtr2; | |
509 | u32 dummy3; /* 0x4C */ | |
510 | u32 dbtr3; | |
511 | u32 dbtr4; | |
512 | u32 dbtr5; | |
513 | u32 dbtr6; | |
514 | u32 dbtr7; | |
515 | u32 dbtr8; | |
516 | u32 dbtr9; | |
517 | u32 dbtr10; | |
518 | u32 dbtr11; | |
519 | u32 dbtr12; | |
520 | u32 dbtr13; | |
521 | u32 dbtr14; | |
522 | u32 dbtr15; | |
523 | u32 dbtr16; | |
524 | u32 dbtr17; | |
525 | u32 dbtr18; | |
526 | u32 dbtr19; | |
527 | u32 dummy4[7]; /* 0x94 .. 0xAC */ | |
528 | u32 dbbl; | |
529 | u32 dummy5[3]; /* 0xB4 .. 0xBC */ | |
530 | u32 dbadj0; | |
531 | u32 dummy6; /* 0xC4 */ | |
532 | u32 dbadj2; | |
533 | u32 dummy7[5]; /* 0xCC .. 0xDC */ | |
534 | u32 dbrfcnf0; | |
535 | u32 dbrfcnf1; | |
536 | u32 dbrfcnf2; | |
537 | u32 dummy8[2]; /* 0xEC .. 0xF0 */ | |
538 | u32 dbcalcnf; | |
539 | u32 dbcaltr; | |
540 | u32 dummy9; /* 0xFC */ | |
541 | u32 dbrnk0; | |
542 | u32 dummy10[31]; /* 0x104 .. 0x17C */ | |
543 | u32 dbpdncnf; | |
544 | u32 dummy11[47]; /* 0x184 ..0x23C */ | |
545 | u32 dbdfistat; | |
546 | u32 dbdficnt; | |
547 | u32 dummy12[14]; /* 0x248 .. 0x27C */ | |
548 | u32 dbpdlck; | |
549 | u32 dummy13[3]; /* 0x284 .. 0x28C */ | |
550 | u32 dbpdrga; | |
551 | u32 dummy14[3]; /* 0x294 .. 0x29C */ | |
552 | u32 dbpdrgd; | |
553 | u32 dummy15[24]; /* 0x2A4 .. 0x300 */ | |
554 | u32 dbbs0cnt1; | |
555 | u32 dummy16[30]; /* 0x308 .. 0x37C */ | |
556 | u32 dbwt0cnf0; | |
557 | u32 dbwt0cnf1; | |
558 | u32 dbwt0cnf2; | |
559 | u32 dbwt0cnf3; | |
560 | u32 dbwt0cnf4; | |
561 | }; | |
562 | ||
563 | /* GPIO */ | |
564 | struct r8a7791_gpio { | |
565 | u32 iointsel; | |
566 | u32 inoutsel; | |
567 | u32 outdt; | |
568 | u32 indt; | |
569 | u32 intdt; | |
570 | u32 intclr; | |
571 | u32 intmsk; | |
572 | u32 posneg; | |
573 | u32 edglevel; | |
574 | u32 filonoff; | |
575 | u32 intmsks; | |
576 | u32 mskclrs; | |
577 | u32 outdtsel; | |
578 | u32 outdth; | |
579 | u32 outdtl; | |
580 | u32 bothedge; | |
581 | }; | |
582 | ||
583 | /* S3C(QoS) */ | |
584 | struct r8a7791_s3c { | |
585 | u32 s3cexcladdmsk; | |
586 | u32 s3cexclidmsk; | |
587 | u32 s3cadsplcr; | |
588 | u32 s3cmaar; | |
589 | u32 dummy0; /* 0x10 */ | |
590 | u32 s3crorr; | |
591 | u32 s3cworr; | |
592 | u32 s3carcr22; | |
593 | u32 dummy1[2]; /* 0x20 .. 0x24 */ | |
594 | u32 s3cmctr; | |
595 | u32 dummy2; /* 0x2C */ | |
596 | u32 cconf0; | |
597 | u32 cconf1; | |
598 | u32 cconf2; | |
599 | u32 cconf3; | |
600 | }; | |
601 | ||
602 | struct r8a7791_s3c_qos { | |
603 | u32 s3cqos0; | |
604 | u32 s3cqos1; | |
605 | u32 s3cqos2; | |
606 | u32 s3cqos3; | |
607 | u32 s3cqos4; | |
608 | u32 s3cqos5; | |
609 | u32 s3cqos6; | |
610 | u32 s3cqos7; | |
611 | u32 s3cqos8; | |
612 | }; | |
613 | ||
614 | /* DBSC(QoS) */ | |
615 | struct r8a7791_dbsc3_qos { | |
616 | u32 dblgcnt; | |
617 | u32 dbtmval0; | |
618 | u32 dbtmval1; | |
619 | u32 dbtmval2; | |
620 | u32 dbtmval3; | |
621 | u32 dbrqctr; | |
622 | u32 dbthres0; | |
623 | u32 dbthres1; | |
624 | u32 dbthres2; | |
1251e490 | 625 | u32 dummy0; /* 0x24 */ |
bd0550fc NI |
626 | u32 dblgqon; |
627 | }; | |
628 | ||
629 | /* MXI(QoS) */ | |
630 | struct r8a7791_mxi { | |
1251e490 NI |
631 | u32 mxsaar0; |
632 | u32 mxsaar1; | |
633 | u32 dummy0[8]; /* 0x08 .. 0x24 */ | |
bd0550fc | 634 | u32 mxs3cracr; |
1251e490 NI |
635 | u32 dummy1[3]; /* 0x2C .. 0x34 */ |
636 | u32 mxs3cwacr; | |
637 | u32 dummy2; /* 0x3C */ | |
bd0550fc NI |
638 | u32 mxrtcr; |
639 | u32 mxwtcr; | |
640 | }; | |
641 | ||
1251e490 NI |
642 | struct r8a7791_mxi_qos { |
643 | u32 vspdu0; | |
644 | u32 vspdu1; | |
645 | u32 du0; | |
646 | u32 du1; | |
647 | }; | |
648 | ||
bd0550fc NI |
649 | /* AXI(QoS) */ |
650 | struct r8a7791_axi_qos { | |
651 | u32 qosconf; | |
652 | u32 qosctset0; | |
653 | u32 qosctset1; | |
654 | u32 qosctset2; | |
655 | u32 qosctset3; | |
656 | u32 qosreqctr; | |
657 | u32 qosthres0; | |
658 | u32 qosthres1; | |
659 | u32 qosthres2; | |
660 | u32 qosqon; | |
661 | }; | |
662 | ||
663 | #endif | |
664 | ||
665 | #endif /* __ASM_ARCH_R8A7791_H */ |