[thirdparty/u-boot.git] / arch / arm / include / asm / arch-rockchip / cru_rk3036.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * (C) Copyright 2015 Rockchip Electronics Co., Ltd
 */
#ifndef _ASM_ARCH_CRU_RK3036_H
#define _ASM_ARCH_CRU_RK3036_H

#include <common.h>

#define OSC_HZ		(24 * 1000 * 1000)

#define APLL_HZ		(600 * 1000000)
#define GPLL_HZ		(594 * 1000000)

#define CORE_PERI_HZ	150000000
#define CORE_ACLK_HZ	300000000

#define BUS_ACLK_HZ	148500000
#define BUS_HCLK_HZ	148500000
#define BUS_PCLK_HZ	74250000

#define PERI_ACLK_HZ	148500000
#define PERI_HCLK_HZ	148500000
#define PERI_PCLK_HZ	74250000

/* Private data for the clock driver - used by rockchip_get_cru() */
struct rk3036_clk_priv {
	struct rk3036_cru *cru;
	ulong rate;
};

struct rk3036_cru {
	struct rk3036_pll {
		unsigned int con0;
		unsigned int con1;
		unsigned int con2;
		unsigned int con3;
	} pll[4];
	unsigned int cru_mode_con;
	unsigned int cru_clksel_con[35];
	unsigned int cru_clkgate_con[11];
	unsigned int reserved;
	unsigned int cru_glb_srst_fst_value;
	unsigned int cru_glb_srst_snd_value;
	unsigned int reserved1[2];
	unsigned int cru_softrst_con[9];
	unsigned int cru_misc_con;
	unsigned int reserved2[2];
	unsigned int cru_glb_cnt_th;
	unsigned int cru_sdmmc_con[2];
	unsigned int cru_sdio_con[2];
	unsigned int cru_emmc_con[2];
	unsigned int reserved3;
	unsigned int cru_rst_st;
	unsigned int reserved4[0x23];
	unsigned int cru_pll_mask_con;
};
check_member(rk3036_cru, cru_pll_mask_con, 0x01f0);

struct pll_div {
	u32 refdiv;
	u32 fbdiv;
	u32 postdiv1;
	u32 postdiv2;
	u32 frac;
};

enum {
	/* PLLCON0*/
	PLL_POSTDIV1_SHIFT	= 12,
	PLL_POSTDIV1_MASK	= 7 << PLL_POSTDIV1_SHIFT,
	PLL_FBDIV_SHIFT		= 0,
	PLL_FBDIV_MASK		= 0xfff,

	/* PLLCON1 */
	PLL_RST_SHIFT		= 14,
	PLL_DSMPD_SHIFT		= 12,
	PLL_DSMPD_MASK		= 1 << PLL_DSMPD_SHIFT,
	PLL_LOCK_STATUS_SHIFT	= 10,
	PLL_LOCK_STATUS_MASK	= 1 << PLL_LOCK_STATUS_SHIFT,
	PLL_POSTDIV2_SHIFT	= 6,
	PLL_POSTDIV2_MASK	= 7 << PLL_POSTDIV2_SHIFT,
	PLL_REFDIV_SHIFT	= 0,
	PLL_REFDIV_MASK		= 0x3f,

	/* CRU_MODE */
	GPLL_MODE_SHIFT		= 12,
	GPLL_MODE_MASK		= 3 << GPLL_MODE_SHIFT,
	GPLL_MODE_SLOW		= 0,
	GPLL_MODE_NORM,
	GPLL_MODE_DEEP,
	DPLL_MODE_SHIFT		= 4,
	DPLL_MODE_MASK		= 1 << DPLL_MODE_SHIFT,
	DPLL_MODE_SLOW		= 0,
	DPLL_MODE_NORM,
	APLL_MODE_SHIFT		= 0,
	APLL_MODE_MASK		= 1 << APLL_MODE_SHIFT,
	APLL_MODE_SLOW		= 0,
	APLL_MODE_NORM,

	/* CRU_CLK_SEL0_CON */
	BUS_ACLK_PLL_SEL_SHIFT	= 14,
	BUS_ACLK_PLL_SEL_MASK	= 3 << BUS_ACLK_PLL_SEL_SHIFT,
	BUS_ACLK_PLL_SEL_APLL	= 0,
	BUS_ACLK_PLL_SEL_DPLL,
	BUS_ACLK_PLL_SEL_GPLL,
	BUS_ACLK_DIV_SHIFT	= 8,
	BUS_ACLK_DIV_MASK	= 0x1f << BUS_ACLK_DIV_SHIFT,
	CORE_CLK_PLL_SEL_SHIFT	= 7,
	CORE_CLK_PLL_SEL_MASK	= 1 << CORE_CLK_PLL_SEL_SHIFT,
	CORE_CLK_PLL_SEL_APLL	= 0,
	CORE_CLK_PLL_SEL_GPLL,
	CORE_DIV_CON_SHIFT	= 0,
	CORE_DIV_CON_MASK	= 0x1f << CORE_DIV_CON_SHIFT,

	/* CRU_CLK_SEL1_CON */
	BUS_PCLK_DIV_SHIFT	= 12,
	BUS_PCLK_DIV_MASK	= 7 << BUS_PCLK_DIV_SHIFT,
	BUS_HCLK_DIV_SHIFT	= 8,
	BUS_HCLK_DIV_MASK	= 3 << BUS_HCLK_DIV_SHIFT,
	CORE_ACLK_DIV_SHIFT	= 4,
	CORE_ACLK_DIV_MASK	= 7 << CORE_ACLK_DIV_SHIFT,
	CORE_PERI_DIV_SHIFT	= 0,
	CORE_PERI_DIV_MASK	= 0xf << CORE_PERI_DIV_SHIFT,

	/* CRU_CLKSEL10_CON */
	PERI_PLL_SEL_SHIFT	= 14,
	PERI_PLL_SEL_MASK	= 3 << PERI_PLL_SEL_SHIFT,
	PERI_PLL_APLL		= 0,
	PERI_PLL_DPLL,
	PERI_PLL_GPLL,
	PERI_PCLK_DIV_SHIFT	= 12,
	PERI_PCLK_DIV_MASK	= 3 << PERI_PCLK_DIV_SHIFT,
	PERI_HCLK_DIV_SHIFT	= 8,
	PERI_HCLK_DIV_MASK	= 3 << PERI_HCLK_DIV_SHIFT,
	PERI_ACLK_DIV_SHIFT	= 0,
	PERI_ACLK_DIV_MASK	= 0x1f << PERI_ACLK_DIV_SHIFT,

	/* CRU_CLKSEL11_CON */
	SDIO_DIV_SHIFT		= 8,
	SDIO_DIV_MASK		= 0x7f << SDIO_DIV_SHIFT,
	MMC0_DIV_SHIFT		= 0,
	MMC0_DIV_MASK		= 0x7f << MMC0_DIV_SHIFT,

	/* CRU_CLKSEL12_CON */
	EMMC_PLL_SHIFT		= 12,
	EMMC_PLL_MASK		= 3 << EMMC_PLL_SHIFT,
	EMMC_SEL_APLL		= 0,
	EMMC_SEL_DPLL,
	EMMC_SEL_GPLL,
	EMMC_SEL_24M,
	SDIO_PLL_SHIFT		= 10,
	SDIO_PLL_MASK		= 3 << SDIO_PLL_SHIFT,
	SDIO_SEL_APLL		= 0,
	SDIO_SEL_DPLL,
	SDIO_SEL_GPLL,
	SDIO_SEL_24M,
	MMC0_PLL_SHIFT		= 8,
	MMC0_PLL_MASK		= 3 << MMC0_PLL_SHIFT,
	MMC0_SEL_APLL		= 0,
	MMC0_SEL_DPLL,
	MMC0_SEL_GPLL,
	MMC0_SEL_24M,
	EMMC_DIV_SHIFT		= 0,
	EMMC_DIV_MASK		= 0x7f << EMMC_DIV_SHIFT,

	/* CRU_SOFTRST5_CON */
	DDRCTRL_PSRST_SHIFT	= 11,
	DDRCTRL_SRST_SHIFT	= 10,
	DDRPHY_PSRST_SHIFT	= 9,
	DDRPHY_SRST_SHIFT	= 8,
};
#endif
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
3f2ef139	2	/*
3f2ef139	3	* (C) Copyright 2015 Rockchip Electronics Co., Ltd
3f2ef139	4	*/
	5	#ifndef _ASM_ARCH_CRU_RK3036_H
	6	#define _ASM_ARCH_CRU_RK3036_H
	7
	8	#include <common.h>
	9
	10	#define OSC_HZ (24 * 1000 * 1000)
	11
	12	#define APLL_HZ (600 * 1000000)
	13	#define GPLL_HZ (594 * 1000000)
	14
	15	#define CORE_PERI_HZ 150000000
	16	#define CORE_ACLK_HZ 300000000
	17
1960b010 KY	18	#define BUS_ACLK_HZ 148500000
	19	#define BUS_HCLK_HZ 148500000
	20	#define BUS_PCLK_HZ 74250000
3f2ef139	21
	22	#define PERI_ACLK_HZ 148500000
	23	#define PERI_HCLK_HZ 148500000
	24	#define PERI_PCLK_HZ 74250000
	25
92ac73e4 SG	26	/* Private data for the clock driver - used by rockchip_get_cru() */
	27	struct rk3036_clk_priv {
	28	struct rk3036_cru *cru;
	29	ulong rate;
	30	};
	31
3f2ef139	32	struct rk3036_cru {
	33	struct rk3036_pll {
	34	unsigned int con0;
	35	unsigned int con1;
	36	unsigned int con2;
	37	unsigned int con3;
	38	} pll[4];
	39	unsigned int cru_mode_con;
	40	unsigned int cru_clksel_con[35];
	41	unsigned int cru_clkgate_con[11];
	42	unsigned int reserved;
	43	unsigned int cru_glb_srst_fst_value;
	44	unsigned int cru_glb_srst_snd_value;
	45	unsigned int reserved1[2];
	46	unsigned int cru_softrst_con[9];
	47	unsigned int cru_misc_con;
	48	unsigned int reserved2[2];
	49	unsigned int cru_glb_cnt_th;
	50	unsigned int cru_sdmmc_con[2];
	51	unsigned int cru_sdio_con[2];
	52	unsigned int cru_emmc_con[2];
	53	unsigned int reserved3;
	54	unsigned int cru_rst_st;
	55	unsigned int reserved4[0x23];
	56	unsigned int cru_pll_mask_con;
	57	};
	58	check_member(rk3036_cru, cru_pll_mask_con, 0x01f0);
	59
	60	struct pll_div {
	61	u32 refdiv;
	62	u32 fbdiv;
	63	u32 postdiv1;
	64	u32 postdiv2;
	65	u32 frac;
	66	};
	67
	68	enum {
	69	/* PLLCON0*/
3f2ef139	70	PLL_POSTDIV1_SHIFT = 12,
37943aae	71	PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT,
3f2ef139	72	PLL_FBDIV_SHIFT = 0,
37943aae	73	PLL_FBDIV_MASK = 0xfff,
3f2ef139	74
3f2ef139	75	/* PLLCON1 */
37943aae	76	PLL_RST_SHIFT = 14,
3f2ef139	77	PLL_DSMPD_SHIFT = 12,
37943aae	78	PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT,
3f2ef139	79	PLL_LOCK_STATUS_SHIFT = 10,
37943aae	80	PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT,
3f2ef139	81	PLL_POSTDIV2_SHIFT = 6,
37943aae	82	PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT,
3f2ef139	83	PLL_REFDIV_SHIFT = 0,
37943aae	84	PLL_REFDIV_MASK = 0x3f,
3f2ef139	85
3f2ef139	86	/* CRU_MODE */
3f2ef139	87	GPLL_MODE_SHIFT = 12,
37943aae	88	GPLL_MODE_MASK = 3 << GPLL_MODE_SHIFT,
3f2ef139	89	GPLL_MODE_SLOW = 0,
	90	GPLL_MODE_NORM,
	91	GPLL_MODE_DEEP,
3f2ef139	92	DPLL_MODE_SHIFT = 4,
37943aae	93	DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT,
3f2ef139	94	DPLL_MODE_SLOW = 0,
3f2ef139	95	DPLL_MODE_NORM,
3f2ef139	96	APLL_MODE_SHIFT = 0,
37943aae	97	APLL_MODE_MASK = 1 << APLL_MODE_SHIFT,
3f2ef139	98	APLL_MODE_SLOW = 0,
	99	APLL_MODE_NORM,
	100
	101	/* CRU_CLK_SEL0_CON */
37943aae KY	102	BUS_ACLK_PLL_SEL_SHIFT = 14,
	103	BUS_ACLK_PLL_SEL_MASK = 3 << BUS_ACLK_PLL_SEL_SHIFT,
	104	BUS_ACLK_PLL_SEL_APLL = 0,
	105	BUS_ACLK_PLL_SEL_DPLL,
	106	BUS_ACLK_PLL_SEL_GPLL,
	107	BUS_ACLK_DIV_SHIFT = 8,
	108	BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT,
3f2ef139	109	CORE_CLK_PLL_SEL_SHIFT = 7,
37943aae	110	CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT,
3f2ef139	111	CORE_CLK_PLL_SEL_APLL = 0,
3f2ef139	112	CORE_CLK_PLL_SEL_GPLL,
3f2ef139	113	CORE_DIV_CON_SHIFT = 0,
37943aae	114	CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT,
3f2ef139	115
3f2ef139	116	/* CRU_CLK_SEL1_CON */
37943aae KY	117	BUS_PCLK_DIV_SHIFT = 12,
	118	BUS_PCLK_DIV_MASK = 7 << BUS_PCLK_DIV_SHIFT,
	119	BUS_HCLK_DIV_SHIFT = 8,
	120	BUS_HCLK_DIV_MASK = 3 << BUS_HCLK_DIV_SHIFT,
3f2ef139	121	CORE_ACLK_DIV_SHIFT = 4,
37943aae	122	CORE_ACLK_DIV_MASK = 7 << CORE_ACLK_DIV_SHIFT,
3f2ef139	123	CORE_PERI_DIV_SHIFT = 0,
37943aae	124	CORE_PERI_DIV_MASK = 0xf << CORE_PERI_DIV_SHIFT,
3f2ef139	125
3f2ef139	126	/* CRU_CLKSEL10_CON */
3f2ef139	127	PERI_PLL_SEL_SHIFT = 14,
37943aae	128	PERI_PLL_SEL_MASK = 3 << PERI_PLL_SEL_SHIFT,
3f2ef139	129	PERI_PLL_APLL = 0,
	130	PERI_PLL_DPLL,
	131	PERI_PLL_GPLL,
3f2ef139	132	PERI_PCLK_DIV_SHIFT = 12,
37943aae	133	PERI_PCLK_DIV_MASK = 3 << PERI_PCLK_DIV_SHIFT,
3f2ef139	134	PERI_HCLK_DIV_SHIFT = 8,
37943aae	135	PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT,
3f2ef139	136	PERI_ACLK_DIV_SHIFT = 0,
37943aae	137	PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT,
3f2ef139	138
3f2ef139	139	/* CRU_CLKSEL11_CON */
3f2ef139	140	SDIO_DIV_SHIFT = 8,
37943aae	141	SDIO_DIV_MASK = 0x7f << SDIO_DIV_SHIFT,
3f2ef139	142	MMC0_DIV_SHIFT = 0,
37943aae	143	MMC0_DIV_MASK = 0x7f << MMC0_DIV_SHIFT,
3f2ef139	144
3f2ef139	145	/* CRU_CLKSEL12_CON */
3f2ef139	146	EMMC_PLL_SHIFT = 12,
37943aae	147	EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT,
3f2ef139	148	EMMC_SEL_APLL = 0,
	149	EMMC_SEL_DPLL,
	150	EMMC_SEL_GPLL,
	151	EMMC_SEL_24M,
3f2ef139	152	SDIO_PLL_SHIFT = 10,
37943aae	153	SDIO_PLL_MASK = 3 << SDIO_PLL_SHIFT,
3f2ef139	154	SDIO_SEL_APLL = 0,
	155	SDIO_SEL_DPLL,
	156	SDIO_SEL_GPLL,
	157	SDIO_SEL_24M,
3f2ef139	158	MMC0_PLL_SHIFT = 8,
37943aae	159	MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT,
3f2ef139	160	MMC0_SEL_APLL = 0,
	161	MMC0_SEL_DPLL,
	162	MMC0_SEL_GPLL,
	163	MMC0_SEL_24M,
3f2ef139	164	EMMC_DIV_SHIFT = 0,
37943aae	165	EMMC_DIV_MASK = 0x7f << EMMC_DIV_SHIFT,
3f2ef139	166
	167	/* CRU_SOFTRST5_CON */
	168	DDRCTRL_PSRST_SHIFT = 11,
	169	DDRCTRL_SRST_SHIFT = 10,
	170	DDRPHY_PSRST_SHIFT = 9,
	171	DDRPHY_SRST_SHIFT = 8,
	172	};
	173	#endif