[people/ms/u-boot.git] / arch / arm / include / asm / arch-rockchip / cru_rk3368.h

/*
 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
 * Author: Andy Yan <andy.yan@rock-chips.com>
 * SPDX-License-Identifier:     GPL-2.0+
 */
#ifndef _ASM_ARCH_CRU_RK3368_H
#define _ASM_ARCH_CRU_RK3368_H

#include <common.h>


/* RK3368 clock numbers */
enum rk3368_pll_id {
	APLLB,
	APLLL,
	DPLL,
	CPLL,
	GPLL,
	NPLL,
	PLL_COUNT,
};

struct rk3368_cru {
	struct rk3368_pll {
		unsigned int con0;
		unsigned int con1;
		unsigned int con2;
		unsigned int con3;
	} pll[6];
	unsigned int reserved[0x28];
	unsigned int clksel_con[56];
	unsigned int reserved1[8];
	unsigned int clkgate_con[25];
	unsigned int reserved2[7];
	unsigned int glb_srst_fst_val;
	unsigned int glb_srst_snd_val;
	unsigned int reserved3[0x1e];
	unsigned int softrst_con[15];
	unsigned int reserved4[0x11];
	unsigned int misc_con;
	unsigned int glb_cnt_th;
	unsigned int glb_rst_con;
	unsigned int glb_rst_st;
	unsigned int reserved5[0x1c];
	unsigned int sdmmc_con[2];
	unsigned int sdio0_con[2];
	unsigned int sdio1_con[2];
	unsigned int emmc_con[2];
};
check_member(rk3368_cru, emmc_con[1], 0x41c);

struct rk3368_clk_priv {
	struct rk3368_cru *cru;
};

enum {
	/* PLL CON0 */
	PLL_NR_SHIFT			= 8,
	PLL_NR_MASK			= GENMASK(13, 8),
	PLL_OD_SHIFT			= 0,
	PLL_OD_MASK			= GENMASK(3, 0),

	/* PLL CON1 */
	PLL_LOCK_STA			= BIT(31),
	PLL_NF_SHIFT			= 0,
	PLL_NF_MASK			= GENMASK(12, 0),

	/* PLL CON2 */
	PLL_BWADJ_SHIFT			= 0,
	PLL_BWADJ_MASK			= GENMASK(11, 0),

	/* PLL CON3 */
	PLL_MODE_SHIFT			= 8,
	PLL_MODE_MASK			= GENMASK(9, 8),
	PLL_MODE_SLOW			= 0,
	PLL_MODE_NORMAL			= 1,
	PLL_MODE_DEEP_SLOW		= 3,
	PLL_RESET_SHIFT			= 5,
	PLL_RESET			= 1,
	PLL_RESET_MASK			= GENMASK(5, 5),

	/* CLKSEL12_CON */
	MCU_STCLK_DIV_SHIFT		= 8,
	MCU_STCLK_DIV_MASK		= GENMASK(10, 8),
	MCU_PLL_SEL_SHIFT		= 7,
	MCU_PLL_SEL_MASK		= BIT(7),
	MCU_PLL_SEL_CPLL		= 0,
	MCU_PLL_SEL_GPLL		= 1,
	MCU_CLK_DIV_SHIFT		= 0,
	MCU_CLK_DIV_MASK		= GENMASK(4, 0),

	/* CLKSEL_CON25 */
	CLK_SARADC_DIV_CON_SHIFT	= 8,
	CLK_SARADC_DIV_CON_MASK		= GENMASK(15, 8),
	CLK_SARADC_DIV_CON_WIDTH	= 8,

	/* CLKSEL43_CON */
	GMAC_MUX_SEL_EXTCLK             = BIT(8),

	/* CLKSEL51_CON */
	MMC_PLL_SEL_SHIFT		= 8,
	MMC_PLL_SEL_MASK		= GENMASK(9, 8),
	MMC_PLL_SEL_CPLL		= (0 << MMC_PLL_SEL_SHIFT),
	MMC_PLL_SEL_GPLL                = (1 << MMC_PLL_SEL_SHIFT),
	MMC_PLL_SEL_USBPHY_480M         = (2 << MMC_PLL_SEL_SHIFT),
	MMC_PLL_SEL_24M                 = (3 << MMC_PLL_SEL_SHIFT),
	MMC_CLK_DIV_SHIFT		= 0,
	MMC_CLK_DIV_MASK		= GENMASK(6, 0),

	/* SOFTRST1_CON */
	MCU_PO_SRST_MASK		= BIT(13),
	MCU_SYS_SRST_MASK		= BIT(12),
	DMA1_SRST_REQ                   = BIT(2),

	/* SOFTRST4_CON */
	DMA2_SRST_REQ                   = BIT(0),

	/* GLB_RST_CON */
	PMU_GLB_SRST_CTRL_SHIFT		= 2,
	PMU_GLB_SRST_CTRL_MASK		= GENMASK(3, 2),
	PMU_RST_BY_FST_GLB_SRST 	= 0,
	PMU_RST_BY_SND_GLB_SRST 	= 1,
	PMU_RST_DISABLE			= 2,
	WDT_GLB_SRST_CTRL_SHIFT		= 1,
	WDT_GLB_SRST_CTRL_MASK		= BIT(1),
	WDT_TRIGGER_SND_GLB_SRST 	= 0,
	WDT_TRIGGER_FST_GLB_SRST 	= 1,
	TSADC_GLB_SRST_CTRL_SHIFT 	= 0,
	TSADC_GLB_SRST_CTRL_MASK  	= BIT(0),
	TSADC_TRIGGER_SND_GLB_SRST 	= 0,
	TSADC_TRIGGER_FST_GLB_SRST 	= 1,

};
#endif
Commit	Line	Data
d1dcf852 AY	1	/*
	2	* (C) Copyright 2017 Rockchip Electronics Co., Ltd
	3	* Author: Andy Yan <andy.yan@rock-chips.com>
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6	#ifndef _ASM_ARCH_CRU_RK3368_H
	7	#define _ASM_ARCH_CRU_RK3368_H
	8
	9	#include <common.h>
	10
	11
	12	/* RK3368 clock numbers */
	13	enum rk3368_pll_id {
	14	APLLB,
	15	APLLL,
	16	DPLL,
	17	CPLL,
	18	GPLL,
	19	NPLL,
	20	PLL_COUNT,
	21	};
	22
	23	struct rk3368_cru {
	24	struct rk3368_pll {
	25	unsigned int con0;
	26	unsigned int con1;
	27	unsigned int con2;
	28	unsigned int con3;
	29	} pll[6];
	30	unsigned int reserved[0x28];
	31	unsigned int clksel_con[56];
	32	unsigned int reserved1[8];
	33	unsigned int clkgate_con[25];
	34	unsigned int reserved2[7];
	35	unsigned int glb_srst_fst_val;
	36	unsigned int glb_srst_snd_val;
	37	unsigned int reserved3[0x1e];
	38	unsigned int softrst_con[15];
	39	unsigned int reserved4[0x11];
	40	unsigned int misc_con;
	41	unsigned int glb_cnt_th;
	42	unsigned int glb_rst_con;
	43	unsigned int glb_rst_st;
	44	unsigned int reserved5[0x1c];
	45	unsigned int sdmmc_con[2];
	46	unsigned int sdio0_con[2];
	47	unsigned int sdio1_con[2];
	48	unsigned int emmc_con[2];
	49	};
	50	check_member(rk3368_cru, emmc_con[1], 0x41c);
	51
	52	struct rk3368_clk_priv {
	53	struct rk3368_cru *cru;
d1dcf852 AY	54	};
	55
	56	enum {
	57	/* PLL CON0 */
	58	PLL_NR_SHIFT = 8,
	59	PLL_NR_MASK = GENMASK(13, 8),
	60	PLL_OD_SHIFT = 0,
	61	PLL_OD_MASK = GENMASK(3, 0),
	62
	63	/* PLL CON1 */
	64	PLL_LOCK_STA = BIT(31),
	65	PLL_NF_SHIFT = 0,
	66	PLL_NF_MASK = GENMASK(12, 0),
	67
	68	/* PLL CON2 */
	69	PLL_BWADJ_SHIFT = 0,
	70	PLL_BWADJ_MASK = GENMASK(11, 0),
	71
	72	/* PLL CON3 */
	73	PLL_MODE_SHIFT = 8,
	74	PLL_MODE_MASK = GENMASK(9, 8),
	75	PLL_MODE_SLOW = 0,
	76	PLL_MODE_NORMAL = 1,
	77	PLL_MODE_DEEP_SLOW = 3,
	78	PLL_RESET_SHIFT = 5,
	79	PLL_RESET = 1,
	80	PLL_RESET_MASK = GENMASK(5, 5),
	81
	82	/* CLKSEL12_CON */
	83	MCU_STCLK_DIV_SHIFT = 8,
	84	MCU_STCLK_DIV_MASK = GENMASK(10, 8),
	85	MCU_PLL_SEL_SHIFT = 7,
	86	MCU_PLL_SEL_MASK = BIT(7),
	87	MCU_PLL_SEL_CPLL = 0,
	88	MCU_PLL_SEL_GPLL = 1,
	89	MCU_CLK_DIV_SHIFT = 0,
	90	MCU_CLK_DIV_MASK = GENMASK(4, 0),
df0ae000	91
615514c1 DW	92	/* CLKSEL_CON25 */
	93	CLK_SARADC_DIV_CON_SHIFT = 8,
	94	CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8),
	95	CLK_SARADC_DIV_CON_WIDTH = 8,
	96
df0ae000 PT	97	/* CLKSEL43_CON */
df0ae000 PT	98	GMAC_MUX_SEL_EXTCLK = BIT(8),
d1dcf852 AY	99
	100	/* CLKSEL51_CON */
	101	MMC_PLL_SEL_SHIFT = 8,
	102	MMC_PLL_SEL_MASK = GENMASK(9, 8),
f5a43295 PT	103	MMC_PLL_SEL_CPLL = (0 << MMC_PLL_SEL_SHIFT),
	104	MMC_PLL_SEL_GPLL = (1 << MMC_PLL_SEL_SHIFT),
	105	MMC_PLL_SEL_USBPHY_480M = (2 << MMC_PLL_SEL_SHIFT),
	106	MMC_PLL_SEL_24M = (3 << MMC_PLL_SEL_SHIFT),
d1dcf852 AY	107	MMC_CLK_DIV_SHIFT = 0,
	108	MMC_CLK_DIV_MASK = GENMASK(6, 0),
	109
	110	/* SOFTRST1_CON */
	111	MCU_PO_SRST_MASK = BIT(13),
	112	MCU_SYS_SRST_MASK = BIT(12),
05c57e12 PT	113	DMA1_SRST_REQ = BIT(2),
	114
	115	/* SOFTRST4_CON */
	116	DMA2_SRST_REQ = BIT(0),
d1dcf852 AY	117
	118	/* GLB_RST_CON */
	119	PMU_GLB_SRST_CTRL_SHIFT = 2,
	120	PMU_GLB_SRST_CTRL_MASK = GENMASK(3, 2),
	121	PMU_RST_BY_FST_GLB_SRST = 0,
	122	PMU_RST_BY_SND_GLB_SRST = 1,
	123	PMU_RST_DISABLE = 2,
	124	WDT_GLB_SRST_CTRL_SHIFT = 1,
	125	WDT_GLB_SRST_CTRL_MASK = BIT(1),
	126	WDT_TRIGGER_SND_GLB_SRST = 0,
	127	WDT_TRIGGER_FST_GLB_SRST = 1,
	128	TSADC_GLB_SRST_CTRL_SHIFT = 0,
	129	TSADC_GLB_SRST_CTRL_MASK = BIT(0),
	130	TSADC_TRIGGER_SND_GLB_SRST = 0,
	131	TSADC_TRIGGER_FST_GLB_SRST = 1,
	132
	133	};
	134	#endif