[people/ms/u-boot.git] / arch / arm / include / asm / arch-rockchip / grf_rk3368.h

/*
 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
 * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
 *
 * SPDX-License-Identifier:     GPL-2.0+
 */
#ifndef _ASM_ARCH_GRF_RK3368_H
#define _ASM_ARCH_GRF_RK3368_H

#include <common.h>

struct rk3368_grf {
	u32 gpio1a_iomux;
	u32 gpio1b_iomux;
	u32 gpio1c_iomux;
	u32 gpio1d_iomux;
	u32 gpio2a_iomux;
	u32 gpio2b_iomux;
	u32 gpio2c_iomux;
	u32 gpio2d_iomux;
	u32 gpio3a_iomux;
	u32 gpio3b_iomux;
	u32 gpio3c_iomux;
	u32 gpio3d_iomux;
	u32 reserved[0x34];
	u32 gpio1a_pull;
	u32 gpio1b_pull;
	u32 gpio1c_pull;
	u32 gpio1d_pull;
	u32 gpio2a_pull;
	u32 gpio2b_pull;
	u32 gpio2c_pull;
	u32 gpio2d_pull;
	u32 gpio3a_pull;
	u32 gpio3b_pull;
	u32 gpio3c_pull;
	u32 gpio3d_pull;
	u32 reserved1[0x34];
	u32 gpio1a_drv;
	u32 gpio1b_drv;
	u32 gpio1c_drv;
	u32 gpio1d_drv;
	u32 gpio2a_drv;
	u32 gpio2b_drv;
	u32 gpio2c_drv;
	u32 gpio2d_drv;
	u32 gpio3a_drv;
	u32 gpio3b_drv;
	u32 gpio3c_drv;
	u32 gpio3d_drv;
	u32 reserved2[0x34];
	u32 gpio1l_sr;
	u32 gpio1h_sr;
	u32 gpio2l_sr;
	u32 gpio2h_sr;
	u32 gpio3l_sr;
	u32 gpio3h_sr;
	u32 reserved3[0x1a];
	u32 gpio_smt;
	u32 reserved4[0x1f];
	u32 soc_con0;
	u32 soc_con1;
	u32 soc_con2;
	u32 soc_con3;
	u32 soc_con4;
	u32 soc_con5;
	u32 soc_con6;
	u32 soc_con7;
	u32 soc_con8;
	u32 soc_con9;
	u32 soc_con10;
	u32 soc_con11;
	u32 soc_con12;
	u32 soc_con13;
	u32 soc_con14;
	u32 soc_con15;
	u32 soc_con16;
	u32 soc_con17;
};
check_member(rk3368_grf, soc_con17, 0x444);

struct rk3368_pmu_grf {
	u32 gpio0a_iomux;
	u32 gpio0b_iomux;
	u32 gpio0c_iomux;
	u32 gpio0d_iomux;
	u32 gpio0a_pull;
	u32 gpio0b_pull;
	u32 gpio0c_pull;
	u32 gpio0d_pull;
	u32 gpio0a_drv;
	u32 gpio0b_drv;
	u32 gpio0c_drv;
	u32 gpio0d_drv;
	u32 gpio0l_sr;
	u32 gpio0h_sr;
	u32 reserved[0x72];
	u32 os_reg[4];
};
check_member(rk3368_pmu_grf, gpio0h_sr, 0x34);
check_member(rk3368_pmu_grf, os_reg[0], 0x200);

/*GRF_GPIO0C_IOMUX*/
enum {
	GPIO0C7_SHIFT           = 14,
	GPIO0C7_MASK	        = GENMASK(GPIO0C7_SHIFT + 1, GPIO0C7_SHIFT),
	GPIO0C7_GPIO	        = 0,
	GPIO0C7_LCDC_D19        = (1 << GPIO0C7_SHIFT),
	GPIO0C7_TRACE_D9        = (2 << GPIO0C7_SHIFT),
	GPIO0C7_UART1_RTSN      = (3 << GPIO0C7_SHIFT),

	GPIO0C6_SHIFT           = 12,
	GPIO0C6_MASK            = GENMASK(GPIO0C6_SHIFT + 1, GPIO0C6_SHIFT),
	GPIO0C6_GPIO            = 0,
	GPIO0C6_LCDC_D18        = (1 << GPIO0C6_SHIFT),
	GPIO0C6_TRACE_D8        = (2 << GPIO0C6_SHIFT),
	GPIO0C6_UART1_CTSN      = (3 << GPIO0C6_SHIFT),

	GPIO0C5_SHIFT           = 10,
	GPIO0C5_MASK            = GENMASK(GPIO0C5_SHIFT + 1, GPIO0C5_SHIFT),
	GPIO0C5_GPIO            = 0,
	GPIO0C5_LCDC_D17        = (1 << GPIO0C5_SHIFT),
	GPIO0C5_TRACE_D7        = (2 << GPIO0C5_SHIFT),
	GPIO0C5_UART1_SOUT      = (3 << GPIO0C5_SHIFT),

	GPIO0C4_SHIFT           = 8,
	GPIO0C4_MASK            = GENMASK(GPIO0C4_SHIFT + 1, GPIO0C4_SHIFT),
	GPIO0C4_GPIO            = 0,
	GPIO0C4_LCDC_D16        = (1 << GPIO0C4_SHIFT),
	GPIO0C4_TRACE_D6        = (2 << GPIO0C4_SHIFT),
	GPIO0C4_UART1_SIN       = (3 << GPIO0C4_SHIFT),

	GPIO0C3_SHIFT           = 6,
	GPIO0C3_MASK            = GENMASK(GPIO0C3_SHIFT + 1, GPIO0C3_SHIFT),
	GPIO0C3_GPIO            = 0,
	GPIO0C3_LCDC_D15        = (1 << GPIO0C3_SHIFT),
	GPIO0C3_TRACE_D5        = (2 << GPIO0C3_SHIFT),
	GPIO0C3_MCU_JTAG_TDO    = (3 << GPIO0C3_SHIFT),

	GPIO0C2_SHIFT           = 4,
	GPIO0C2_MASK            = GENMASK(GPIO0C2_SHIFT + 1, GPIO0C2_SHIFT),
	GPIO0C2_GPIO            = 0,
	GPIO0C2_LCDC_D14        = (1 << GPIO0C2_SHIFT),
	GPIO0C2_TRACE_D4        = (2 << GPIO0C2_SHIFT),
	GPIO0C2_MCU_JTAG_TDI    = (3 << GPIO0C2_SHIFT),

	GPIO0C1_SHIFT           = 2,
	GPIO0C1_MASK            = GENMASK(GPIO0C1_SHIFT + 1, GPIO0C1_SHIFT),
	GPIO0C1_GPIO            = 0,
	GPIO0C1_LCDC_D13        = (1 << GPIO0C1_SHIFT),
	GPIO0C1_TRACE_D3        = (2 << GPIO0C1_SHIFT),
	GPIO0C1_MCU_JTAG_TRTSN  = (3 << GPIO0C1_SHIFT),

	GPIO0C0_SHIFT           = 0,
	GPIO0C0_MASK            = GENMASK(GPIO0C0_SHIFT + 1, GPIO0C0_SHIFT),
	GPIO0C0_GPIO            = 0,
	GPIO0C0_LCDC_D12        = (1 << GPIO0C0_SHIFT),
	GPIO0C0_TRACE_D2        = (2 << GPIO0C0_SHIFT),
	GPIO0C0_MCU_JTAG_TDO    = (3 << GPIO0C0_SHIFT),
};

/*GRF_GPIO0D_IOMUX*/
enum {
	GPIO0D7_SHIFT           = 14,
	GPIO0D7_MASK            = GENMASK(GPIO0D7_SHIFT + 1, GPIO0D7_SHIFT),
	GPIO0D7_GPIO            = 0,
	GPIO0D7_LCDC_DCLK       = (1 << GPIO0D7_SHIFT),
	GPIO0D7_TRACE_CTL       = (2 << GPIO0D7_SHIFT),
	GPIO0D7_PMU_DEBUG5      = (3 << GPIO0D7_SHIFT),

	GPIO0D6_SHIFT           = 12,
	GPIO0D6_MASK            = GENMASK(GPIO0D6_SHIFT + 1, GPIO0D6_SHIFT),
	GPIO0D6_GPIO            = 0,
	GPIO0D6_LCDC_DEN        = (1 << GPIO0D6_SHIFT),
	GPIO0D6_TRACE_CLK       = (2 << GPIO0D6_SHIFT),
	GPIO0D6_PMU_DEBUG4      = (3 << GPIO0D6_SHIFT),

	GPIO0D5_SHIFT           = 10,
	GPIO0D5_MASK            = GENMASK(GPIO0D5_SHIFT + 1, GPIO0D5_SHIFT),
	GPIO0D5_GPIO            = 0,
	GPIO0D5_LCDC_VSYNC      = (1 << GPIO0D5_SHIFT),
	GPIO0D5_TRACE_D15       = (2 << GPIO0D5_SHIFT),
	GPIO0D5_PMU_DEBUG3      = (3 << GPIO0D5_SHIFT),

	GPIO0D4_SHIFT           = 8,
	GPIO0D4_MASK            = GENMASK(GPIO0D4_SHIFT + 1, GPIO0D4_SHIFT),
	GPIO0D4_GPIO            = 0,
	GPIO0D4_LCDC_HSYNC      = (1 << GPIO0D4_SHIFT),
	GPIO0D4_TRACE_D14       = (2 << GPIO0D4_SHIFT),
	GPIO0D4_PMU_DEBUG2      = (3 << GPIO0D4_SHIFT),

	GPIO0D3_SHIFT           = 6,
	GPIO0D3_MASK            = GENMASK(GPIO0D3_SHIFT + 1, GPIO0D3_SHIFT),
	GPIO0D3_GPIO            = 0,
	GPIO0D3_LCDC_D23        = (1 << GPIO0D3_SHIFT),
	GPIO0D3_TRACE_D13       = (2 << GPIO0D3_SHIFT),
	GPIO0D3_UART4_SIN       = (3 << GPIO0D3_SHIFT),

	GPIO0D2_SHIFT           = 4,
	GPIO0D2_MASK            = GENMASK(GPIO0D2_SHIFT + 1, GPIO0D2_SHIFT),
	GPIO0D2_GPIO            = 0,
	GPIO0D2_LCDC_D22        = (1 << GPIO0D2_SHIFT),
	GPIO0D2_TRACE_D12       = (2 << GPIO0D2_SHIFT),
	GPIO0D2_UART4_SOUT      = (3 << GPIO0D2_SHIFT),

	GPIO0D1_SHIFT           = 2,
	GPIO0D1_MASK            = GENMASK(GPIO0D1_SHIFT + 1, GPIO0D1_SHIFT),
	GPIO0D1_GPIO            = 0,
	GPIO0D1_LCDC_D21        = (1 << GPIO0D1_SHIFT),
	GPIO0D1_TRACE_D11       = (2 << GPIO0D1_SHIFT),
	GPIO0D1_UART4_RTSN      = (3 << GPIO0D1_SHIFT),

	GPIO0D0_SHIFT           = 0,
	GPIO0D0_MASK            = GENMASK(GPIO0D0_SHIFT + 1, GPIO0D0_SHIFT),
	GPIO0D0_GPIO            = 0,
	GPIO0D0_LCDC_D20        = (1 << GPIO0D0_SHIFT),
	GPIO0D0_TRACE_D10       = (2 << GPIO0D0_SHIFT),
	GPIO0D0_UART4_CTSN      = (3 << GPIO0D0_SHIFT),
};

/*GRF_GPIO2A_IOMUX*/
enum {
	GPIO2A7_SHIFT           = 14,
	GPIO2A7_MASK            = GENMASK(GPIO2A7_SHIFT + 1, GPIO2A7_SHIFT),
	GPIO2A7_GPIO            = 0,
	GPIO2A7_SDMMC0_D2       = (1 << GPIO2A7_SHIFT),
	GPIO2A7_JTAG_TCK        = (2 << GPIO2A7_SHIFT),

	GPIO2A6_SHIFT           = 12,
	GPIO2A6_MASK            = GENMASK(GPIO2A6_SHIFT + 1, GPIO2A6_SHIFT),
	GPIO2A6_GPIO            = 0,
	GPIO2A6_SDMMC0_D1       = (1 << GPIO2A6_SHIFT),
	GPIO2A6_UART2_SIN       = (2 << GPIO2A6_SHIFT),

	GPIO2A5_SHIFT           = 10,
	GPIO2A5_MASK            = GENMASK(GPIO2A5_SHIFT + 1, GPIO2A5_SHIFT),
	GPIO2A5_GPIO            = 0,
	GPIO2A5_SDMMC0_D0       = (1 << GPIO2A5_SHIFT),
	GPIO2A5_UART2_SOUT      = (2 << GPIO2A5_SHIFT),

	GPIO2A4_SHIFT           = 8,
	GPIO2A4_MASK            = GENMASK(GPIO2A4_SHIFT + 1, GPIO2A4_SHIFT),
	GPIO2A4_GPIO            = 0,
	GPIO2A4_FLASH_DQS       = (1 << GPIO2A4_SHIFT),
	GPIO2A4_EMMC_CLKOUT     = (2 << GPIO2A4_SHIFT),

	GPIO2A3_SHIFT           = 6,
	GPIO2A3_MASK            = GENMASK(GPIO2A3_SHIFT + 1, GPIO2A3_SHIFT),
	GPIO2A3_GPIO            = 0,
	GPIO2A3_FLASH_CSN3      = (1 << GPIO2A3_SHIFT),
	GPIO2A3_EMMC_RSTNOUT    = (2 << GPIO2A3_SHIFT),

	GPIO2A2_SHIFT           = 4,
	GPIO2A2_MASK            = GENMASK(GPIO2A2_SHIFT + 1, GPIO2A2_SHIFT),
	GPIO2A2_GPIO            = 0,
	GPIO2A2_FLASH_CSN2      = (1 << GPIO2A2_SHIFT),

	GPIO2A1_SHIFT           = 2,
	GPIO2A1_MASK            = GENMASK(GPIO2A1_SHIFT + 1, GPIO2A1_SHIFT),
	GPIO2A1_GPIO            = 0,
	GPIO2A1_FLASH_CSN1      = (1 << GPIO2A1_SHIFT),

	GPIO2A0_SHIFT           = 0,
	GPIO2A0_MASK            = GENMASK(GPIO2A0_SHIFT + 1, GPIO2A0_SHIFT),
	GPIO2A0_GPIO            = 0,
	GPIO2A0_FLASH_CSN0      = (1 << GPIO2A0_SHIFT),
};

/*GRF_GPIO2D_IOMUX*/
enum {
	GPIO2D7_SHIFT           = 14,
	GPIO2D7_MASK            = GENMASK(GPIO2D7_SHIFT + 1, GPIO2D7_SHIFT),
	GPIO2D7_GPIO            = 0,
	GPIO2D7_SDIO0_D3        = (1 << GPIO2D7_SHIFT),

	GPIO2D6_SHIFT           = 12,
	GPIO2D6_MASK            = GENMASK(GPIO2D6_SHIFT + 1, GPIO2D6_SHIFT),
	GPIO2D6_GPIO            = 0,
	GPIO2D6_SDIO0_D2        = (1 << GPIO2D6_SHIFT),

	GPIO2D5_SHIFT           = 10,
	GPIO2D5_MASK            = GENMASK(GPIO2D5_SHIFT + 1, GPIO2D5_SHIFT),
	GPIO2D5_GPIO            = 0,
	GPIO2D5_SDIO0_D1        = (1 << GPIO2D5_SHIFT),

	GPIO2D4_SHIFT           = 8,
	GPIO2D4_MASK            = GENMASK(GPIO2D4_SHIFT + 1, GPIO2D4_SHIFT),
	GPIO2D4_GPIO            = 0,
	GPIO2D4_SDIO0_D0        = (1 << GPIO2D4_SHIFT),

	GPIO2D3_SHIFT           = 6,
	GPIO2D3_MASK            = GENMASK(GPIO2D3_SHIFT + 1, GPIO2D3_SHIFT),
	GPIO2D3_GPIO            = 0,
	GPIO2D3_UART0_RTS0      = (1 << GPIO2D3_SHIFT),

	GPIO2D2_SHIFT           = 4,
	GPIO2D2_MASK            = GENMASK(GPIO2D2_SHIFT + 1, GPIO2D2_SHIFT),
	GPIO2D2_GPIO            = 0,
	GPIO2D2_UART0_CTS0      = (1 << GPIO2D2_SHIFT),

	GPIO2D1_SHIFT           = 2,
	GPIO2D1_MASK            = GENMASK(GPIO2D1_SHIFT + 1, GPIO2D1_SHIFT),
	GPIO2D1_GPIO            = 0,
	GPIO2D1_UART0_SOUT      = (1 << GPIO2D1_SHIFT),

	GPIO2D0_SHIFT           = 0,
	GPIO2D0_MASK            = GENMASK(GPIO2D0_SHIFT + 1, GPIO2D0_SHIFT),
	GPIO2D0_GPIO            = 0,
	GPIO2D0_UART0_SIN       = (1 << GPIO2D0_SHIFT),
};

/* GRF_GPIO1C_IOMUX */
enum {
	GPIO1C7_SHIFT           = 14,
	GPIO1C7_MASK            = GENMASK(GPIO1C7_SHIFT + 1, GPIO1C7_SHIFT),
	GPIO1C7_GPIO            = 0,
	GPIO1C7_EMMC_DATA5      = (2 << GPIO1C7_SHIFT),

	GPIO1C6_SHIFT           = 12,
	GPIO1C6_MASK            = GENMASK(GPIO1C6_SHIFT + 1, GPIO1C6_SHIFT),
	GPIO1C6_GPIO            = 0,
	GPIO1C6_EMMC_DATA4      = (2 << GPIO1C6_SHIFT),

	GPIO1C5_SHIFT           = 10,
	GPIO1C5_MASK            = GENMASK(GPIO1C5_SHIFT + 1, GPIO1C5_SHIFT),
	GPIO1C5_GPIO            = 0,
	GPIO1C5_EMMC_DATA3      = (2 << GPIO1C5_SHIFT),

	GPIO1C4_SHIFT           = 8,
	GPIO1C4_MASK            = GENMASK(GPIO1C4_SHIFT + 1, GPIO1C4_SHIFT),
	GPIO1C4_GPIO            = 0,
	GPIO1C4_EMMC_DATA2      = (2 << GPIO1C4_SHIFT),

	GPIO1C3_SHIFT           = 6,
	GPIO1C3_MASK            = GENMASK(GPIO1C3_SHIFT + 1, GPIO1C3_SHIFT),
	GPIO1C3_GPIO            = 0,
	GPIO1C3_EMMC_DATA1      = (2 << GPIO1C3_SHIFT),

	GPIO1C2_SHIFT           = 4,
	GPIO1C2_MASK            = GENMASK(GPIO1C2_SHIFT + 1, GPIO1C2_SHIFT),
	GPIO1C2_GPIO            = 0,
	GPIO1C2_EMMC_DATA0      = (2 << GPIO1C2_SHIFT),
};

/* GRF_GPIO1D_IOMUX*/
enum {
	GPIO1D3_SHIFT           = 6,
	GPIO1D3_MASK            = GENMASK(GPIO1D3_SHIFT + 1, GPIO1D3_SHIFT),
	GPIO1D3_GPIO            = 0,
	GPIO1D3_EMMC_PWREN      = (2 << GPIO1D3_SHIFT),

	GPIO1D2_SHIFT           = 4,
	GPIO1D2_MASK            = GENMASK(GPIO1D2_SHIFT + 1, GPIO1D2_SHIFT),
	GPIO1D2_GPIO            = 0,
	GPIO1D2_EMMC_CMD        = (2 << GPIO1D2_SHIFT),

	GPIO1D1_SHIFT           = 2,
	GPIO1D1_MASK            = GENMASK(GPIO1D1_SHIFT + 1, GPIO1D1_SHIFT),
	GPIO1D1_GPIO            = 0,
	GPIO1D1_EMMC_DATA7      = (2 << GPIO1D1_SHIFT),

	GPIO1D0_SHIFT           = 0,
	GPIO1D0_MASK            = GENMASK(GPIO1D0_SHIFT + 1, GPIO1D0_SHIFT),
	GPIO1D0_GPIO            = 0,
	GPIO1D0_EMMC_DATA6      = (2 << GPIO1D0_SHIFT),
};


/*GRF_GPIO3B_IOMUX*/
enum {
	GPIO3B7_SHIFT           = 14,
	GPIO3B7_MASK            = GENMASK(GPIO3B7_SHIFT + 1, GPIO3B7_SHIFT),
	GPIO3B7_GPIO            = 0,
	GPIO3B7_MAC_RXD0        = (1 << GPIO3B7_SHIFT),

	GPIO3B6_SHIFT           = 12,
	GPIO3B6_MASK            = GENMASK(GPIO3B6_SHIFT + 1, GPIO3B6_SHIFT),
	GPIO3B6_GPIO            = 0,
	GPIO3B6_MAC_TXD3        = (1 << GPIO3B6_SHIFT),

	GPIO3B5_SHIFT           = 10,
	GPIO3B5_MASK            = GENMASK(GPIO3B5_SHIFT + 1, GPIO3B5_SHIFT),
	GPIO3B5_GPIO            = 0,
	GPIO3B5_MAC_TXEN        = (1 << GPIO3B5_SHIFT),

	GPIO3B4_SHIFT           = 8,
	GPIO3B4_MASK            = GENMASK(GPIO3B4_SHIFT + 1, GPIO3B4_SHIFT),
	GPIO3B4_GPIO            = 0,
	GPIO3B4_MAC_COL         = (1 << GPIO3B4_SHIFT),

	GPIO3B3_SHIFT           = 6,
	GPIO3B3_MASK            = GENMASK(GPIO3B3_SHIFT + 1, GPIO3B3_SHIFT),
	GPIO3B3_GPIO            = 0,
	GPIO3B3_MAC_CRS         = (1 << GPIO3B3_SHIFT),

	GPIO3B2_SHIFT           = 4,
	GPIO3B2_MASK            = GENMASK(GPIO3B2_SHIFT + 1, GPIO3B2_SHIFT),
	GPIO3B2_GPIO            = 0,
	GPIO3B2_MAC_TXD2        = (1 << GPIO3B2_SHIFT),

	GPIO3B1_SHIFT           = 2,
	GPIO3B1_MASK            = GENMASK(GPIO3B1_SHIFT + 1, GPIO3B1_SHIFT),
	GPIO3B1_GPIO            = 0,
	GPIO3B1_MAC_TXD1        = (1 << GPIO3B1_SHIFT),

	GPIO3B0_SHIFT           = 0,
	GPIO3B0_MASK            = GENMASK(GPIO3B0_SHIFT + 1, GPIO3B0_SHIFT),
	GPIO3B0_GPIO            = 0,
	GPIO3B0_MAC_TXD0        = (1 << GPIO3B0_SHIFT),
	GPIO3B0_PWM0            = (2 << GPIO3B0_SHIFT),
};

/*GRF_GPIO3C_IOMUX*/
enum {
	GPIO3C6_SHIFT           = 12,
	GPIO3C6_MASK            = GENMASK(GPIO3C6_SHIFT + 1, GPIO3C6_SHIFT),
	GPIO3C6_GPIO            = 0,
	GPIO3C6_MAC_CLK         = (1 << GPIO3C6_SHIFT),

	GPIO3C5_SHIFT           = 10,
	GPIO3C5_MASK            = GENMASK(GPIO3C5_SHIFT + 1, GPIO3C5_SHIFT),
	GPIO3C5_GPIO            = 0,
	GPIO3C5_MAC_RXEN        = (1 << GPIO3C5_SHIFT),

	GPIO3C4_SHIFT           = 8,
	GPIO3C4_MASK            = GENMASK(GPIO3C4_SHIFT + 1, GPIO3C4_SHIFT),
	GPIO3C4_GPIO            = 0,
	GPIO3C4_MAC_RXDV        = (1 << GPIO3C4_SHIFT),

	GPIO3C3_SHIFT           = 6,
	GPIO3C3_MASK            = GENMASK(GPIO3C3_SHIFT + 1, GPIO3C3_SHIFT),
	GPIO3C3_GPIO            = 0,
	GPIO3C3_MAC_MDC         = (1 << GPIO3C3_SHIFT),

	GPIO3C2_SHIFT           = 4,
	GPIO3C2_MASK            = GENMASK(GPIO3C2_SHIFT + 1, GPIO3C2_SHIFT),
	GPIO3C2_GPIO            = 0,
	GPIO3C2_MAC_RXD3        = (1 << GPIO3C2_SHIFT),

	GPIO3C1_SHIFT           = 2,
	GPIO3C1_MASK            = GENMASK(GPIO3C1_SHIFT + 1, GPIO3C1_SHIFT),
	GPIO3C1_GPIO            = 0,
	GPIO3C1_MAC_RXD2        = (1 << GPIO3C1_SHIFT),

	GPIO3C0_SHIFT           = 0,
	GPIO3C0_MASK            = GENMASK(GPIO3C0_SHIFT + 1, GPIO3C0_SHIFT),
	GPIO3C0_GPIO            = 0,
	GPIO3C0_MAC_RXD1        = (1 << GPIO3C0_SHIFT),
};

/*GRF_GPIO3D_IOMUX*/
enum {
	GPIO3D4_SHIFT           = 8,
	GPIO3D4_MASK            = GENMASK(GPIO3D4_SHIFT + 1, GPIO3D4_SHIFT),
	GPIO3D4_GPIO            = 0,
	GPIO3D4_MAC_TXCLK       = (1 << GPIO3D4_SHIFT),

	GPIO3D1_SHIFT           = 2,
	GPIO3D1_MASK            = GENMASK(GPIO3D1_SHIFT + 1, GPIO3D1_SHIFT),
	GPIO3D1_GPIO            = 0,
	GPIO3D1_MAC_RXCLK       = (1 << GPIO3D1_SHIFT),

	GPIO3D0_SHIFT           = 0,
	GPIO3D0_MASK            = GENMASK(GPIO3D0_SHIFT + 1, GPIO3D0_SHIFT),
	GPIO3D0_GPIO            = 0,
	GPIO3D0_MAC_MDIO        = (1 << GPIO3D0_SHIFT),
};

/* GRF_SOC_CON0 */
enum {
	NOC_RSP_ERR_STALL = BIT(9),
	MOBILE_DDR_SEL = BIT(4),
	DDR0_16BIT_EN = BIT(3),
	MSCH0_MAINDDR3_DDR3 = BIT(2),
	MSCH0_MAINPARTIALPOP = BIT(1),
	UPCTL_C_ACTIVE = BIT(0),
};

/*GRF_SOC_CON11/12/13*/
enum {
	MCU_SRAM_BASE_BIT27_BIT12_SHIFT	= 0,
	MCU_SRAM_BASE_BIT27_BIT12_MASK	= GENMASK(15, 0),
};

/*GRF_SOC_CON12*/
enum {
	MCU_EXSRAM_BASE_BIT27_BIT12_SHIFT  = 0,
	MCU_EXSRAM_BASE_BIT27_BIT12_MASK   = GENMASK(15, 0),
};

/*GRF_SOC_CON13*/
enum {
	MCU_EXPERI_BASE_BIT27_BIT12_SHIFT  = 0,
	MCU_EXPERI_BASE_BIT27_BIT12_MASK   = GENMASK(15, 0),
};

/*GRF_SOC_CON14*/
enum {
	MCU_EXPERI_BASE_BIT31_BIT28_SHIFT	= 12,
	MCU_EXPERI_BASE_BIT31_BIT28_MASK	= GENMASK(15, 12),
	MCU_EXSRAM_BASE_BIT31_BIT28_SHIFT	= 8,
	MCU_EXSRAM_BASE_BIT31_BIT28_MASK	= GENMASK(11, 8),
	MCU_SRAM_BASE_BIT31_BIT28_SHIFT		= 4,
	MCU_SRAM_BASE_BIT31_BIT28_MASK		= GENMASK(7, 4),
	MCU_CODE_BASE_BIT31_BIT28_SHIFT		= 0,
	MCU_CODE_BASE_BIT31_BIT28_MASK		= GENMASK(3, 0),
};
#endif
Commit	Line	Data
c1828cf7 PT	1	/*
	2	* (C) Copyright 2016 Rockchip Electronics Co., Ltd
	3	* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
27600a58 AY	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7	#ifndef _ASM_ARCH_GRF_RK3368_H
	8	#define _ASM_ARCH_GRF_RK3368_H
	9
	10	#include <common.h>
	11
	12	struct rk3368_grf {
	13	u32 gpio1a_iomux;
	14	u32 gpio1b_iomux;
	15	u32 gpio1c_iomux;
	16	u32 gpio1d_iomux;
	17	u32 gpio2a_iomux;
	18	u32 gpio2b_iomux;
	19	u32 gpio2c_iomux;
	20	u32 gpio2d_iomux;
	21	u32 gpio3a_iomux;
	22	u32 gpio3b_iomux;
	23	u32 gpio3c_iomux;
	24	u32 gpio3d_iomux;
	25	u32 reserved[0x34];
	26	u32 gpio1a_pull;
	27	u32 gpio1b_pull;
	28	u32 gpio1c_pull;
	29	u32 gpio1d_pull;
	30	u32 gpio2a_pull;
	31	u32 gpio2b_pull;
	32	u32 gpio2c_pull;
	33	u32 gpio2d_pull;
	34	u32 gpio3a_pull;
	35	u32 gpio3b_pull;
	36	u32 gpio3c_pull;
	37	u32 gpio3d_pull;
	38	u32 reserved1[0x34];
	39	u32 gpio1a_drv;
	40	u32 gpio1b_drv;
	41	u32 gpio1c_drv;
	42	u32 gpio1d_drv;
	43	u32 gpio2a_drv;
	44	u32 gpio2b_drv;
	45	u32 gpio2c_drv;
	46	u32 gpio2d_drv;
	47	u32 gpio3a_drv;
	48	u32 gpio3b_drv;
	49	u32 gpio3c_drv;
	50	u32 gpio3d_drv;
	51	u32 reserved2[0x34];
	52	u32 gpio1l_sr;
	53	u32 gpio1h_sr;
	54	u32 gpio2l_sr;
	55	u32 gpio2h_sr;
	56	u32 gpio3l_sr;
	57	u32 gpio3h_sr;
	58	u32 reserved3[0x1a];
	59	u32 gpio_smt;
	60	u32 reserved4[0x1f];
	61	u32 soc_con0;
	62	u32 soc_con1;
	63	u32 soc_con2;
	64	u32 soc_con3;
	65	u32 soc_con4;
	66	u32 soc_con5;
	67	u32 soc_con6;
68	u32 soc_con7;
69	u32 soc_con8;
70	u32 soc_con9;
71	u32 soc_con10;
72	u32 soc_con11;
73	u32 soc_con12;
74	u32 soc_con13;
75	u32 soc_con14;
76	u32 soc_con15;
77	u32 soc_con16;
78	u32 soc_con17;
79	};
80	check_member(rk3368_grf, soc_con17, 0x444);
81
82	struct rk3368_pmu_grf {
83	u32 gpio0a_iomux;
84	u32 gpio0b_iomux;
85	u32 gpio0c_iomux;
86	u32 gpio0d_iomux;
87	u32 gpio0a_pull;
88	u32 gpio0b_pull;
89	u32 gpio0c_pull;
90	u32 gpio0d_pull;
91	u32 gpio0a_drv;
92	u32 gpio0b_drv;
93	u32 gpio0c_drv;
94	u32 gpio0d_drv;
95	u32 gpio0l_sr;
96	u32 gpio0h_sr;
525a8c8f	97	u32 reserved[0x72];
cc89369f	98	u32 os_reg[4];
27600a58	99	};
525a8c8f PT	100	check_member(rk3368_pmu_grf, gpio0h_sr, 0x34);
525a8c8f PT	101	check_member(rk3368_pmu_grf, os_reg[0], 0x200);
27600a58 AY	102
	103	/GRF_GPIO0C_IOMUX/
	104	enum {
c1828cf7 PT	105	GPIO0C7_SHIFT = 14,
	106	GPIO0C7_MASK = GENMASK(GPIO0C7_SHIFT + 1, GPIO0C7_SHIFT),
	107	GPIO0C7_GPIO = 0,
	108	GPIO0C7_LCDC_D19 = (1 << GPIO0C7_SHIFT),
	109	GPIO0C7_TRACE_D9 = (2 << GPIO0C7_SHIFT),
	110	GPIO0C7_UART1_RTSN = (3 << GPIO0C7_SHIFT),
27600a58 AY	111
27600a58 AY	112	GPIO0C6_SHIFT = 12,
c1828cf7	113	GPIO0C6_MASK = GENMASK(GPIO0C6_SHIFT + 1, GPIO0C6_SHIFT),
27600a58	114	GPIO0C6_GPIO = 0,
c1828cf7 PT	115	GPIO0C6_LCDC_D18 = (1 << GPIO0C6_SHIFT),
	116	GPIO0C6_TRACE_D8 = (2 << GPIO0C6_SHIFT),
	117	GPIO0C6_UART1_CTSN = (3 << GPIO0C6_SHIFT),
27600a58 AY	118
27600a58 AY	119	GPIO0C5_SHIFT = 10,
c1828cf7	120	GPIO0C5_MASK = GENMASK(GPIO0C5_SHIFT + 1, GPIO0C5_SHIFT),
27600a58	121	GPIO0C5_GPIO = 0,
c1828cf7 PT	122	GPIO0C5_LCDC_D17 = (1 << GPIO0C5_SHIFT),
	123	GPIO0C5_TRACE_D7 = (2 << GPIO0C5_SHIFT),
	124	GPIO0C5_UART1_SOUT = (3 << GPIO0C5_SHIFT),
27600a58 AY	125
27600a58 AY	126	GPIO0C4_SHIFT = 8,
c1828cf7	127	GPIO0C4_MASK = GENMASK(GPIO0C4_SHIFT + 1, GPIO0C4_SHIFT),
27600a58	128	GPIO0C4_GPIO = 0,
c1828cf7 PT	129	GPIO0C4_LCDC_D16 = (1 << GPIO0C4_SHIFT),
	130	GPIO0C4_TRACE_D6 = (2 << GPIO0C4_SHIFT),
	131	GPIO0C4_UART1_SIN = (3 << GPIO0C4_SHIFT),
27600a58 AY	132
27600a58 AY	133	GPIO0C3_SHIFT = 6,
c1828cf7	134	GPIO0C3_MASK = GENMASK(GPIO0C3_SHIFT + 1, GPIO0C3_SHIFT),
27600a58	135	GPIO0C3_GPIO = 0,
c1828cf7 PT	136	GPIO0C3_LCDC_D15 = (1 << GPIO0C3_SHIFT),
	137	GPIO0C3_TRACE_D5 = (2 << GPIO0C3_SHIFT),
	138	GPIO0C3_MCU_JTAG_TDO = (3 << GPIO0C3_SHIFT),
27600a58 AY	139
27600a58 AY	140	GPIO0C2_SHIFT = 4,
c1828cf7	141	GPIO0C2_MASK = GENMASK(GPIO0C2_SHIFT + 1, GPIO0C2_SHIFT),
27600a58	142	GPIO0C2_GPIO = 0,
c1828cf7 PT	143	GPIO0C2_LCDC_D14 = (1 << GPIO0C2_SHIFT),
	144	GPIO0C2_TRACE_D4 = (2 << GPIO0C2_SHIFT),
	145	GPIO0C2_MCU_JTAG_TDI = (3 << GPIO0C2_SHIFT),
27600a58 AY	146
27600a58 AY	147	GPIO0C1_SHIFT = 2,
c1828cf7	148	GPIO0C1_MASK = GENMASK(GPIO0C1_SHIFT + 1, GPIO0C1_SHIFT),
27600a58	149	GPIO0C1_GPIO = 0,
c1828cf7 PT	150	GPIO0C1_LCDC_D13 = (1 << GPIO0C1_SHIFT),
	151	GPIO0C1_TRACE_D3 = (2 << GPIO0C1_SHIFT),
	152	GPIO0C1_MCU_JTAG_TRTSN = (3 << GPIO0C1_SHIFT),
27600a58 AY	153
27600a58 AY	154	GPIO0C0_SHIFT = 0,
c1828cf7	155	GPIO0C0_MASK = GENMASK(GPIO0C0_SHIFT + 1, GPIO0C0_SHIFT),
27600a58	156	GPIO0C0_GPIO = 0,
c1828cf7 PT	157	GPIO0C0_LCDC_D12 = (1 << GPIO0C0_SHIFT),
	158	GPIO0C0_TRACE_D2 = (2 << GPIO0C0_SHIFT),
	159	GPIO0C0_MCU_JTAG_TDO = (3 << GPIO0C0_SHIFT),
27600a58 AY	160	};
	161
	162	/GRF_GPIO0D_IOMUX/
	163	enum {
	164	GPIO0D7_SHIFT = 14,
c1828cf7	165	GPIO0D7_MASK = GENMASK(GPIO0D7_SHIFT + 1, GPIO0D7_SHIFT),
27600a58	166	GPIO0D7_GPIO = 0,
c1828cf7 PT	167	GPIO0D7_LCDC_DCLK = (1 << GPIO0D7_SHIFT),
	168	GPIO0D7_TRACE_CTL = (2 << GPIO0D7_SHIFT),
	169	GPIO0D7_PMU_DEBUG5 = (3 << GPIO0D7_SHIFT),
27600a58 AY	170
27600a58 AY	171	GPIO0D6_SHIFT = 12,
c1828cf7	172	GPIO0D6_MASK = GENMASK(GPIO0D6_SHIFT + 1, GPIO0D6_SHIFT),
27600a58	173	GPIO0D6_GPIO = 0,
c1828cf7 PT	174	GPIO0D6_LCDC_DEN = (1 << GPIO0D6_SHIFT),
	175	GPIO0D6_TRACE_CLK = (2 << GPIO0D6_SHIFT),
	176	GPIO0D6_PMU_DEBUG4 = (3 << GPIO0D6_SHIFT),
27600a58 AY	177
27600a58 AY	178	GPIO0D5_SHIFT = 10,
c1828cf7	179	GPIO0D5_MASK = GENMASK(GPIO0D5_SHIFT + 1, GPIO0D5_SHIFT),
27600a58	180	GPIO0D5_GPIO = 0,
c1828cf7 PT	181	GPIO0D5_LCDC_VSYNC = (1 << GPIO0D5_SHIFT),
	182	GPIO0D5_TRACE_D15 = (2 << GPIO0D5_SHIFT),
	183	GPIO0D5_PMU_DEBUG3 = (3 << GPIO0D5_SHIFT),
27600a58 AY	184
27600a58 AY	185	GPIO0D4_SHIFT = 8,
c1828cf7	186	GPIO0D4_MASK = GENMASK(GPIO0D4_SHIFT + 1, GPIO0D4_SHIFT),
27600a58	187	GPIO0D4_GPIO = 0,
c1828cf7 PT	188	GPIO0D4_LCDC_HSYNC = (1 << GPIO0D4_SHIFT),
	189	GPIO0D4_TRACE_D14 = (2 << GPIO0D4_SHIFT),
	190	GPIO0D4_PMU_DEBUG2 = (3 << GPIO0D4_SHIFT),
27600a58 AY	191
27600a58 AY	192	GPIO0D3_SHIFT = 6,
c1828cf7	193	GPIO0D3_MASK = GENMASK(GPIO0D3_SHIFT + 1, GPIO0D3_SHIFT),
27600a58	194	GPIO0D3_GPIO = 0,
c1828cf7 PT	195	GPIO0D3_LCDC_D23 = (1 << GPIO0D3_SHIFT),
	196	GPIO0D3_TRACE_D13 = (2 << GPIO0D3_SHIFT),
	197	GPIO0D3_UART4_SIN = (3 << GPIO0D3_SHIFT),
27600a58 AY	198
27600a58 AY	199	GPIO0D2_SHIFT = 4,
c1828cf7	200	GPIO0D2_MASK = GENMASK(GPIO0D2_SHIFT + 1, GPIO0D2_SHIFT),
27600a58	201	GPIO0D2_GPIO = 0,
c1828cf7 PT	202	GPIO0D2_LCDC_D22 = (1 << GPIO0D2_SHIFT),
	203	GPIO0D2_TRACE_D12 = (2 << GPIO0D2_SHIFT),
	204	GPIO0D2_UART4_SOUT = (3 << GPIO0D2_SHIFT),
27600a58 AY	205
27600a58 AY	206	GPIO0D1_SHIFT = 2,
c1828cf7	207	GPIO0D1_MASK = GENMASK(GPIO0D1_SHIFT + 1, GPIO0D1_SHIFT),
27600a58	208	GPIO0D1_GPIO = 0,
c1828cf7 PT	209	GPIO0D1_LCDC_D21 = (1 << GPIO0D1_SHIFT),
	210	GPIO0D1_TRACE_D11 = (2 << GPIO0D1_SHIFT),
	211	GPIO0D1_UART4_RTSN = (3 << GPIO0D1_SHIFT),
27600a58 AY	212
27600a58 AY	213	GPIO0D0_SHIFT = 0,
c1828cf7	214	GPIO0D0_MASK = GENMASK(GPIO0D0_SHIFT + 1, GPIO0D0_SHIFT),
27600a58	215	GPIO0D0_GPIO = 0,
c1828cf7 PT	216	GPIO0D0_LCDC_D20 = (1 << GPIO0D0_SHIFT),
	217	GPIO0D0_TRACE_D10 = (2 << GPIO0D0_SHIFT),
	218	GPIO0D0_UART4_CTSN = (3 << GPIO0D0_SHIFT),
27600a58 AY	219	};
	220
	221	/GRF_GPIO2A_IOMUX/
	222	enum {
	223	GPIO2A7_SHIFT = 14,
c1828cf7	224	GPIO2A7_MASK = GENMASK(GPIO2A7_SHIFT + 1, GPIO2A7_SHIFT),
27600a58	225	GPIO2A7_GPIO = 0,
c1828cf7 PT	226	GPIO2A7_SDMMC0_D2 = (1 << GPIO2A7_SHIFT),
c1828cf7 PT	227	GPIO2A7_JTAG_TCK = (2 << GPIO2A7_SHIFT),
27600a58 AY	228
27600a58 AY	229	GPIO2A6_SHIFT = 12,
c1828cf7	230	GPIO2A6_MASK = GENMASK(GPIO2A6_SHIFT + 1, GPIO2A6_SHIFT),
27600a58	231	GPIO2A6_GPIO = 0,
c1828cf7 PT	232	GPIO2A6_SDMMC0_D1 = (1 << GPIO2A6_SHIFT),
c1828cf7 PT	233	GPIO2A6_UART2_SIN = (2 << GPIO2A6_SHIFT),
27600a58 AY	234
27600a58 AY	235	GPIO2A5_SHIFT = 10,
c1828cf7	236	GPIO2A5_MASK = GENMASK(GPIO2A5_SHIFT + 1, GPIO2A5_SHIFT),
27600a58	237	GPIO2A5_GPIO = 0,
c1828cf7 PT	238	GPIO2A5_SDMMC0_D0 = (1 << GPIO2A5_SHIFT),
c1828cf7 PT	239	GPIO2A5_UART2_SOUT = (2 << GPIO2A5_SHIFT),
27600a58 AY	240
27600a58 AY	241	GPIO2A4_SHIFT = 8,
c1828cf7	242	GPIO2A4_MASK = GENMASK(GPIO2A4_SHIFT + 1, GPIO2A4_SHIFT),
27600a58	243	GPIO2A4_GPIO = 0,
c1828cf7 PT	244	GPIO2A4_FLASH_DQS = (1 << GPIO2A4_SHIFT),
c1828cf7 PT	245	GPIO2A4_EMMC_CLKOUT = (2 << GPIO2A4_SHIFT),
27600a58 AY	246
27600a58 AY	247	GPIO2A3_SHIFT = 6,
c1828cf7	248	GPIO2A3_MASK = GENMASK(GPIO2A3_SHIFT + 1, GPIO2A3_SHIFT),
27600a58	249	GPIO2A3_GPIO = 0,
c1828cf7 PT	250	GPIO2A3_FLASH_CSN3 = (1 << GPIO2A3_SHIFT),
c1828cf7 PT	251	GPIO2A3_EMMC_RSTNOUT = (2 << GPIO2A3_SHIFT),
27600a58 AY	252
27600a58 AY	253	GPIO2A2_SHIFT = 4,
c1828cf7 PT	254	GPIO2A2_MASK = GENMASK(GPIO2A2_SHIFT + 1, GPIO2A2_SHIFT),
	255	GPIO2A2_GPIO = 0,
	256	GPIO2A2_FLASH_CSN2 = (1 << GPIO2A2_SHIFT),
27600a58 AY	257
27600a58 AY	258	GPIO2A1_SHIFT = 2,
c1828cf7	259	GPIO2A1_MASK = GENMASK(GPIO2A1_SHIFT + 1, GPIO2A1_SHIFT),
27600a58	260	GPIO2A1_GPIO = 0,
c1828cf7	261	GPIO2A1_FLASH_CSN1 = (1 << GPIO2A1_SHIFT),
27600a58 AY	262
27600a58 AY	263	GPIO2A0_SHIFT = 0,
c1828cf7	264	GPIO2A0_MASK = GENMASK(GPIO2A0_SHIFT + 1, GPIO2A0_SHIFT),
27600a58	265	GPIO2A0_GPIO = 0,
c1828cf7	266	GPIO2A0_FLASH_CSN0 = (1 << GPIO2A0_SHIFT),
27600a58 AY	267	};
	268
	269	/GRF_GPIO2D_IOMUX/
	270	enum {
	271	GPIO2D7_SHIFT = 14,
c1828cf7	272	GPIO2D7_MASK = GENMASK(GPIO2D7_SHIFT + 1, GPIO2D7_SHIFT),
27600a58	273	GPIO2D7_GPIO = 0,
c1828cf7	274	GPIO2D7_SDIO0_D3 = (1 << GPIO2D7_SHIFT),
27600a58 AY	275
27600a58 AY	276	GPIO2D6_SHIFT = 12,
c1828cf7	277	GPIO2D6_MASK = GENMASK(GPIO2D6_SHIFT + 1, GPIO2D6_SHIFT),
27600a58	278	GPIO2D6_GPIO = 0,
c1828cf7	279	GPIO2D6_SDIO0_D2 = (1 << GPIO2D6_SHIFT),
27600a58 AY	280
27600a58 AY	281	GPIO2D5_SHIFT = 10,
c1828cf7	282	GPIO2D5_MASK = GENMASK(GPIO2D5_SHIFT + 1, GPIO2D5_SHIFT),
27600a58	283	GPIO2D5_GPIO = 0,
c1828cf7	284	GPIO2D5_SDIO0_D1 = (1 << GPIO2D5_SHIFT),
27600a58 AY	285
27600a58 AY	286	GPIO2D4_SHIFT = 8,
c1828cf7	287	GPIO2D4_MASK = GENMASK(GPIO2D4_SHIFT + 1, GPIO2D4_SHIFT),
27600a58	288	GPIO2D4_GPIO = 0,
c1828cf7	289	GPIO2D4_SDIO0_D0 = (1 << GPIO2D4_SHIFT),
27600a58 AY	290
27600a58 AY	291	GPIO2D3_SHIFT = 6,
c1828cf7	292	GPIO2D3_MASK = GENMASK(GPIO2D3_SHIFT + 1, GPIO2D3_SHIFT),
27600a58	293	GPIO2D3_GPIO = 0,
c1828cf7	294	GPIO2D3_UART0_RTS0 = (1 << GPIO2D3_SHIFT),
27600a58 AY	295
27600a58 AY	296	GPIO2D2_SHIFT = 4,
c1828cf7	297	GPIO2D2_MASK = GENMASK(GPIO2D2_SHIFT + 1, GPIO2D2_SHIFT),
27600a58	298	GPIO2D2_GPIO = 0,
c1828cf7	299	GPIO2D2_UART0_CTS0 = (1 << GPIO2D2_SHIFT),
27600a58 AY	300
27600a58 AY	301	GPIO2D1_SHIFT = 2,
c1828cf7	302	GPIO2D1_MASK = GENMASK(GPIO2D1_SHIFT + 1, GPIO2D1_SHIFT),
27600a58	303	GPIO2D1_GPIO = 0,
c1828cf7	304	GPIO2D1_UART0_SOUT = (1 << GPIO2D1_SHIFT),
27600a58 AY	305
27600a58 AY	306	GPIO2D0_SHIFT = 0,
c1828cf7	307	GPIO2D0_MASK = GENMASK(GPIO2D0_SHIFT + 1, GPIO2D0_SHIFT),
27600a58	308	GPIO2D0_GPIO = 0,
c1828cf7	309	GPIO2D0_UART0_SIN = (1 << GPIO2D0_SHIFT),
27600a58 AY	310	};
27600a58 AY	311
c1828cf7	312	/* GRF_GPIO1C_IOMUX */
27600a58	313	enum {
c1828cf7 PT	314	GPIO1C7_SHIFT = 14,
	315	GPIO1C7_MASK = GENMASK(GPIO1C7_SHIFT + 1, GPIO1C7_SHIFT),
	316	GPIO1C7_GPIO = 0,
	317	GPIO1C7_EMMC_DATA5 = (2 << GPIO1C7_SHIFT),
	318
	319	GPIO1C6_SHIFT = 12,
	320	GPIO1C6_MASK = GENMASK(GPIO1C6_SHIFT + 1, GPIO1C6_SHIFT),
	321	GPIO1C6_GPIO = 0,
	322	GPIO1C6_EMMC_DATA4 = (2 << GPIO1C6_SHIFT),
	323
	324	GPIO1C5_SHIFT = 10,
	325	GPIO1C5_MASK = GENMASK(GPIO1C5_SHIFT + 1, GPIO1C5_SHIFT),
	326	GPIO1C5_GPIO = 0,
	327	GPIO1C5_EMMC_DATA3 = (2 << GPIO1C5_SHIFT),
	328
	329	GPIO1C4_SHIFT = 8,
	330	GPIO1C4_MASK = GENMASK(GPIO1C4_SHIFT + 1, GPIO1C4_SHIFT),
	331	GPIO1C4_GPIO = 0,
	332	GPIO1C4_EMMC_DATA2 = (2 << GPIO1C4_SHIFT),
	333
	334	GPIO1C3_SHIFT = 6,
	335	GPIO1C3_MASK = GENMASK(GPIO1C3_SHIFT + 1, GPIO1C3_SHIFT),
	336	GPIO1C3_GPIO = 0,
	337	GPIO1C3_EMMC_DATA1 = (2 << GPIO1C3_SHIFT),
	338
	339	GPIO1C2_SHIFT = 4,
	340	GPIO1C2_MASK = GENMASK(GPIO1C2_SHIFT + 1, GPIO1C2_SHIFT),
	341	GPIO1C2_GPIO = 0,
	342	GPIO1C2_EMMC_DATA0 = (2 << GPIO1C2_SHIFT),
	343	};
	344
	345	/* GRF_GPIO1D_IOMUX*/
	346	enum {
	347	GPIO1D3_SHIFT = 6,
	348	GPIO1D3_MASK = GENMASK(GPIO1D3_SHIFT + 1, GPIO1D3_SHIFT),
	349	GPIO1D3_GPIO = 0,
	350	GPIO1D3_EMMC_PWREN = (2 << GPIO1D3_SHIFT),
	351
	352	GPIO1D2_SHIFT = 4,
	353	GPIO1D2_MASK = GENMASK(GPIO1D2_SHIFT + 1, GPIO1D2_SHIFT),
	354	GPIO1D2_GPIO = 0,
	355	GPIO1D2_EMMC_CMD = (2 << GPIO1D2_SHIFT),
	356
	357	GPIO1D1_SHIFT = 2,
	358	GPIO1D1_MASK = GENMASK(GPIO1D1_SHIFT + 1, GPIO1D1_SHIFT),
	359	GPIO1D1_GPIO = 0,
	360	GPIO1D1_EMMC_DATA7 = (2 << GPIO1D1_SHIFT),
	361
	362	GPIO1D0_SHIFT = 0,
	363	GPIO1D0_MASK = GENMASK(GPIO1D0_SHIFT + 1, GPIO1D0_SHIFT),
	364	GPIO1D0_GPIO = 0,
	365	GPIO1D0_EMMC_DATA6 = (2 << GPIO1D0_SHIFT),
	366	};
	367
	368
	369	/GRF_GPIO3B_IOMUX/
	370	enum {
	371	GPIO3B7_SHIFT = 14,
	372	GPIO3B7_MASK = GENMASK(GPIO3B7_SHIFT + 1, GPIO3B7_SHIFT),
	373	GPIO3B7_GPIO = 0,
	374	GPIO3B7_MAC_RXD0 = (1 << GPIO3B7_SHIFT),
	375
	376	GPIO3B6_SHIFT = 12,
	377	GPIO3B6_MASK = GENMASK(GPIO3B6_SHIFT + 1, GPIO3B6_SHIFT),
378	GPIO3B6_GPIO = 0,
379	GPIO3B6_MAC_TXD3 = (1 << GPIO3B6_SHIFT),
380
381	GPIO3B5_SHIFT = 10,
382	GPIO3B5_MASK = GENMASK(GPIO3B5_SHIFT + 1, GPIO3B5_SHIFT),
383	GPIO3B5_GPIO = 0,
384	GPIO3B5_MAC_TXEN = (1 << GPIO3B5_SHIFT),
385
386	GPIO3B4_SHIFT = 8,
387	GPIO3B4_MASK = GENMASK(GPIO3B4_SHIFT + 1, GPIO3B4_SHIFT),
388	GPIO3B4_GPIO = 0,
389	GPIO3B4_MAC_COL = (1 << GPIO3B4_SHIFT),
390
391	GPIO3B3_SHIFT = 6,
392	GPIO3B3_MASK = GENMASK(GPIO3B3_SHIFT + 1, GPIO3B3_SHIFT),
393	GPIO3B3_GPIO = 0,
394	GPIO3B3_MAC_CRS = (1 << GPIO3B3_SHIFT),
395
396	GPIO3B2_SHIFT = 4,
397	GPIO3B2_MASK = GENMASK(GPIO3B2_SHIFT + 1, GPIO3B2_SHIFT),
398	GPIO3B2_GPIO = 0,
399	GPIO3B2_MAC_TXD2 = (1 << GPIO3B2_SHIFT),
400
401	GPIO3B1_SHIFT = 2,
402	GPIO3B1_MASK = GENMASK(GPIO3B1_SHIFT + 1, GPIO3B1_SHIFT),
403	GPIO3B1_GPIO = 0,
404	GPIO3B1_MAC_TXD1 = (1 << GPIO3B1_SHIFT),
405
406	GPIO3B0_SHIFT = 0,
407	GPIO3B0_MASK = GENMASK(GPIO3B0_SHIFT + 1, GPIO3B0_SHIFT),
408	GPIO3B0_GPIO = 0,
409	GPIO3B0_MAC_TXD0 = (1 << GPIO3B0_SHIFT),
410	GPIO3B0_PWM0 = (2 << GPIO3B0_SHIFT),
411	};
27600a58	412
c1828cf7 PT	413	/GRF_GPIO3C_IOMUX/
c1828cf7 PT	414	enum {
27600a58	415	GPIO3C6_SHIFT = 12,
c1828cf7	416	GPIO3C6_MASK = GENMASK(GPIO3C6_SHIFT + 1, GPIO3C6_SHIFT),
27600a58	417	GPIO3C6_GPIO = 0,
c1828cf7	418	GPIO3C6_MAC_CLK = (1 << GPIO3C6_SHIFT),
27600a58 AY	419
27600a58 AY	420	GPIO3C5_SHIFT = 10,
c1828cf7	421	GPIO3C5_MASK = GENMASK(GPIO3C5_SHIFT + 1, GPIO3C5_SHIFT),
27600a58	422	GPIO3C5_GPIO = 0,
c1828cf7	423	GPIO3C5_MAC_RXEN = (1 << GPIO3C5_SHIFT),
27600a58 AY	424
27600a58 AY	425	GPIO3C4_SHIFT = 8,
c1828cf7	426	GPIO3C4_MASK = GENMASK(GPIO3C4_SHIFT + 1, GPIO3C4_SHIFT),
27600a58	427	GPIO3C4_GPIO = 0,
c1828cf7	428	GPIO3C4_MAC_RXDV = (1 << GPIO3C4_SHIFT),
27600a58 AY	429
27600a58 AY	430	GPIO3C3_SHIFT = 6,
c1828cf7	431	GPIO3C3_MASK = GENMASK(GPIO3C3_SHIFT + 1, GPIO3C3_SHIFT),
27600a58	432	GPIO3C3_GPIO = 0,
c1828cf7	433	GPIO3C3_MAC_MDC = (1 << GPIO3C3_SHIFT),
27600a58 AY	434
27600a58 AY	435	GPIO3C2_SHIFT = 4,
c1828cf7 PT	436	GPIO3C2_MASK = GENMASK(GPIO3C2_SHIFT + 1, GPIO3C2_SHIFT),
	437	GPIO3C2_GPIO = 0,
	438	GPIO3C2_MAC_RXD3 = (1 << GPIO3C2_SHIFT),
27600a58 AY	439
27600a58 AY	440	GPIO3C1_SHIFT = 2,
c1828cf7	441	GPIO3C1_MASK = GENMASK(GPIO3C1_SHIFT + 1, GPIO3C1_SHIFT),
27600a58	442	GPIO3C1_GPIO = 0,
c1828cf7	443	GPIO3C1_MAC_RXD2 = (1 << GPIO3C1_SHIFT),
27600a58 AY	444
27600a58 AY	445	GPIO3C0_SHIFT = 0,
c1828cf7	446	GPIO3C0_MASK = GENMASK(GPIO3C0_SHIFT + 1, GPIO3C0_SHIFT),
27600a58	447	GPIO3C0_GPIO = 0,
c1828cf7	448	GPIO3C0_MAC_RXD1 = (1 << GPIO3C0_SHIFT),
27600a58 AY	449	};
	450
	451	/GRF_GPIO3D_IOMUX/
	452	enum {
27600a58	453	GPIO3D4_SHIFT = 8,
c1828cf7	454	GPIO3D4_MASK = GENMASK(GPIO3D4_SHIFT + 1, GPIO3D4_SHIFT),
27600a58	455	GPIO3D4_GPIO = 0,
c1828cf7	456	GPIO3D4_MAC_TXCLK = (1 << GPIO3D4_SHIFT),
27600a58 AY	457
27600a58 AY	458	GPIO3D1_SHIFT = 2,
c1828cf7	459	GPIO3D1_MASK = GENMASK(GPIO3D1_SHIFT + 1, GPIO3D1_SHIFT),
27600a58	460	GPIO3D1_GPIO = 0,
c1828cf7	461	GPIO3D1_MAC_RXCLK = (1 << GPIO3D1_SHIFT),
27600a58 AY	462
27600a58 AY	463	GPIO3D0_SHIFT = 0,
c1828cf7	464	GPIO3D0_MASK = GENMASK(GPIO3D0_SHIFT + 1, GPIO3D0_SHIFT),
27600a58	465	GPIO3D0_GPIO = 0,
c1828cf7 PT	466	GPIO3D0_MAC_MDIO = (1 << GPIO3D0_SHIFT),
	467	};
	468
	469	/* GRF_SOC_CON0 */
	470	enum {
	471	NOC_RSP_ERR_STALL = BIT(9),
	472	MOBILE_DDR_SEL = BIT(4),
	473	DDR0_16BIT_EN = BIT(3),
	474	MSCH0_MAINDDR3_DDR3 = BIT(2),
	475	MSCH0_MAINPARTIALPOP = BIT(1),
	476	UPCTL_C_ACTIVE = BIT(0),
27600a58 AY	477	};
	478
	479	/GRF_SOC_CON11/12/13/
	480	enum {
	481	MCU_SRAM_BASE_BIT27_BIT12_SHIFT = 0,
	482	MCU_SRAM_BASE_BIT27_BIT12_MASK = GENMASK(15, 0),
	483	};
	484
	485	/GRF_SOC_CON12/
	486	enum {
	487	MCU_EXSRAM_BASE_BIT27_BIT12_SHIFT = 0,
	488	MCU_EXSRAM_BASE_BIT27_BIT12_MASK = GENMASK(15, 0),
	489	};
	490
	491	/GRF_SOC_CON13/
	492	enum {
	493	MCU_EXPERI_BASE_BIT27_BIT12_SHIFT = 0,
	494	MCU_EXPERI_BASE_BIT27_BIT12_MASK = GENMASK(15, 0),
	495	};
	496
	497	/GRF_SOC_CON14/
	498	enum {
	499	MCU_EXPERI_BASE_BIT31_BIT28_SHIFT = 12,
	500	MCU_EXPERI_BASE_BIT31_BIT28_MASK = GENMASK(15, 12),
	501	MCU_EXSRAM_BASE_BIT31_BIT28_SHIFT = 8,
	502	MCU_EXSRAM_BASE_BIT31_BIT28_MASK = GENMASK(11, 8),
	503	MCU_SRAM_BASE_BIT31_BIT28_SHIFT = 4,
	504	MCU_SRAM_BASE_BIT31_BIT28_MASK = GENMASK(7, 4),
	505	MCU_CODE_BASE_BIT31_BIT28_SHIFT = 0,
	506	MCU_CODE_BASE_BIT31_BIT28_MASK = GENMASK(3, 0),
	507	};
	508	#endif