projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 9702ec00 EP |
2 | /* |
| 3 | * (C) Copyright 2013-2016, Freescale Semiconductor, Inc. | |
| 9702ec00 EP |
4 | */ |
| 5 | ||
| 6 | #ifndef __ASM_ARCH_IMX_REGS_H__ | |
| 7 | #define __ASM_ARCH_IMX_REGS_H__ | |
| 8 | ||
| 9 | #define ARCH_MXC | |
| 10 | ||
| 11 | #define IRAM_BASE_ADDR 0x3E800000 /* internal ram */ | |
| 12 | #define IRAM_SIZE 0x00400000 /* 4MB */ | |
| 13 | ||
| 14 | #define AIPS0_BASE_ADDR (0x40000000UL) | |
| 15 | #define AIPS1_BASE_ADDR (0x40080000UL) | |
| 16 | ||
| 17 | /* AIPS 0 */ | |
| 18 | #define AXBS_BASE_ADDR (AIPS0_BASE_ADDR + 0x00000000) | |
| 19 | #define CSE3_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001000) | |
| 20 | #define EDMA_BASE_ADDR (AIPS0_BASE_ADDR + 0x00002000) | |
| 21 | #define XRDC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00004000) | |
| 22 | #define SWT0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000A000) | |
| 23 | #define SWT1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000B000) | |
| 24 | #define STM0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000D000) | |
| 25 | #define NIC301_BASE_ADDR (AIPS0_BASE_ADDR + 0x00010000) | |
| 26 | #define GC3000_BASE_ADDR (AIPS0_BASE_ADDR + 0x00020000) | |
| 27 | #define DEC200_DECODER_BASE_ADDR (AIPS0_BASE_ADDR + 0x00026000) | |
| 28 | #define DEC200_ENCODER_BASE_ADDR (AIPS0_BASE_ADDR + 0x00027000) | |
| 29 | #define TWOD_ACE_BASE_ADDR (AIPS0_BASE_ADDR + 0x00028000) | |
| 30 | #define MIPI_CSI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00030000) | |
| 31 | #define DMAMUX0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00031000) | |
| 32 | #define ENET_BASE_ADDR (AIPS0_BASE_ADDR + 0x00032000) | |
| 33 | #define FLEXRAY_BASE_ADDR (AIPS0_BASE_ADDR + 0x00034000) | |
| 34 | #define MMDC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00036000) | |
| 35 | #define MEW0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00037000) | |
| 36 | #define MONITOR_DDR0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00038000) | |
| 37 | #define MONITOR_CCI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00039000) | |
| 38 | #define PIT0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003A000) | |
| 39 | #define MC_CGM0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003C000) | |
| 40 | #define MC_CGM1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003F000) | |
| 41 | #define MC_CGM2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00042000) | |
| 42 | #define MC_CGM3_BASE_ADDR (AIPS0_BASE_ADDR + 0x00045000) | |
| 43 | #define MC_RGM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00048000) | |
| 44 | #define MC_ME_BASE_ADDR (AIPS0_BASE_ADDR + 0x0004A000) | |
| 45 | #define MC_PCU_BASE_ADDR (AIPS0_BASE_ADDR + 0x0004B000) | |
| 46 | #define ADC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0004D000) | |
| 47 | #define FLEXTIMER_BASE_ADDR (AIPS0_BASE_ADDR + 0x0004F000) | |
| 48 | #define I2C0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00051000) | |
| 49 | #define LINFLEXD0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00053000) | |
| 50 | #define FLEXCAN0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00055000) | |
| 51 | #define SPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00057000) | |
| 52 | #define SPI2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00059000) | |
| 53 | #define CRC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0005B000) | |
| 54 | #define USDHC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0005D000) | |
| 55 | #define OCOTP_CONTROLLER_BASE_ADDR (AIPS0_BASE_ADDR + 0x0005F000) | |
| 56 | #define WKPU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00063000) | |
| 57 | #define VIU0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00064000) | |
| 58 | #define HPSMI_SRAM_CONTROLLER_BASE_ADDR (AIPS0_BASE_ADDR + 0x00068000) | |
| 59 | #define SIUL2_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006C000) | |
| 60 | #define SIPI_BASE_ADDR (AIPS0_BASE_ADDR + 0x00074000) | |
| 61 | #define LFAST_BASE_ADDR (AIPS0_BASE_ADDR + 0x00078000) | |
| 62 | #define SSE_BASE_ADDR (AIPS0_BASE_ADDR + 0x00079000) | |
| 63 | #define SRC_SOC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0007C000) | |
| 64 | ||
| 65 | /* AIPS 1 */ | |
| 66 | #define ERM_BASE_ADDR (AIPS1_BASE_ADDR + 0X000000000) | |
| 67 | #define MSCM_BASE_ADDR (AIPS1_BASE_ADDR + 0X000001000) | |
| 68 | #define SEMA42_BASE_ADDR (AIPS1_BASE_ADDR + 0X000002000) | |
| 69 | #define INTC_MON_BASE_ADDR (AIPS1_BASE_ADDR + 0X000003000) | |
| 70 | #define SWT2_BASE_ADDR (AIPS1_BASE_ADDR + 0X000004000) | |
| 71 | #define SWT3_BASE_ADDR (AIPS1_BASE_ADDR + 0X000005000) | |
| 72 | #define SWT4_BASE_ADDR (AIPS1_BASE_ADDR + 0X000006000) | |
| 73 | #define STM1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000007000) | |
| 74 | #define EIM_BASE_ADDR (AIPS1_BASE_ADDR + 0X000008000) | |
| 75 | #define APB_BASE_ADDR (AIPS1_BASE_ADDR + 0X000009000) | |
| 76 | #define XBIC_BASE_ADDR (AIPS1_BASE_ADDR + 0X000012000) | |
| 77 | #define MIPI_BASE_ADDR (AIPS1_BASE_ADDR + 0X000020000) | |
| 78 | #define DMAMUX1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000021000) | |
| 79 | #define MMDC1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000022000) | |
| 80 | #define MEW1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000023000) | |
| 81 | #define DDR1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000024000) | |
| 82 | #define CCI1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000025000) | |
| 83 | #define QUADSPI0_BASE_ADDR (AIPS1_BASE_ADDR + 0X000026000) | |
| 84 | #define PIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0X00002A000) | |
| 85 | #define FCCU_BASE_ADDR (AIPS1_BASE_ADDR + 0X000030000) | |
| 86 | #define FLEXTIMER_FTM1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000036000) | |
| 87 | #define I2C1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000038000) | |
| 88 | #define I2C2_BASE_ADDR (AIPS1_BASE_ADDR + 0X00003A000) | |
| 89 | #define LINFLEXD1_BASE_ADDR (AIPS1_BASE_ADDR + 0X00003C000) | |
| 90 | #define FLEXCAN1_BASE_ADDR (AIPS1_BASE_ADDR + 0X00003E000) | |
| 91 | #define SPI1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000040000) | |
| 92 | #define SPI3_BASE_ADDR (AIPS1_BASE_ADDR + 0X000042000) | |
| 93 | #define IPL_BASE_ADDR (AIPS1_BASE_ADDR + 0X000043000) | |
| 94 | #define CGM_CMU_BASE_ADDR (AIPS1_BASE_ADDR + 0X000044000) | |
| 95 | #define PMC_BASE_ADDR (AIPS1_BASE_ADDR + 0X000048000) | |
| 96 | #define CRC1_BASE_ADDR (AIPS1_BASE_ADDR + 0X00004C000) | |
| 97 | #define TMU_BASE_ADDR (AIPS1_BASE_ADDR + 0X00004E000) | |
| 98 | #define VIU1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000050000) | |
| 99 | #define JPEG_BASE_ADDR (AIPS1_BASE_ADDR + 0X000054000) | |
| 100 | #define H264_DEC_BASE_ADDR (AIPS1_BASE_ADDR + 0X000058000) | |
| 101 | #define H264_ENC_BASE_ADDR (AIPS1_BASE_ADDR + 0X00005C000) | |
| 102 | #define MEMU_BASE_ADDR (AIPS1_BASE_ADDR + 0X000060000) | |
| 103 | #define STCU_BASE_ADDR (AIPS1_BASE_ADDR + 0X000064000) | |
| 104 | #define SLFTST_CTRL_BASE_ADDR (AIPS1_BASE_ADDR + 0X000066000) | |
| 105 | #define MCT_BASE_ADDR (AIPS1_BASE_ADDR + 0X000068000) | |
| 106 | #define REP_BASE_ADDR (AIPS1_BASE_ADDR + 0X00006A000) | |
| 107 | #define MBIST_CONTROLLER_BASE_ADDR (AIPS1_BASE_ADDR + 0X00006C000) | |
| 108 | #define BOOT_LOADER_BASE_ADDR (AIPS1_BASE_ADDR + 0X00006F000) | |
| 109 | ||
| 110 | /* TODO Remove this after the IOMUX framework is implemented */ | |
| 111 | #define IOMUXC_BASE_ADDR SIUL2_BASE_ADDR | |
| 112 | ||
| 113 | /* MUX mode and PAD ctrl are in one register */ | |
| 114 | #define CONFIG_IOMUX_SHARE_CONF_REG | |
| 115 | ||
| 116 | #define FEC_QUIRK_ENET_MAC | |
| 117 | #define I2C_QUIRK_REG | |
| 118 | ||
| 119 | /* MSCM interrupt router */ | |
| 120 | #define MSCM_IRSPRC_CPn_EN 3 | |
| 121 | #define MSCM_IRSPRC_NUM 176 | |
| 122 | #define MSCM_CPXTYPE_RYPZ_MASK 0xFF | |
| 123 | #define MSCM_CPXTYPE_RYPZ_OFFSET 0 | |
| 124 | #define MSCM_CPXTYPE_PERS_MASK 0xFFFFFF00 | |
| 125 | #define MSCM_CPXTYPE_PERS_OFFSET 8 | |
| 126 | #define MSCM_CPXTYPE_PERS_A53 0x413533 | |
| 127 | #define MSCM_CPXTYPE_PERS_CM4 0x434d34 | |
| 128 | ||
| 129 | #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) | |
| 130 | #include <asm/types.h> | |
| 131 | ||
| 132 | /* System Reset Controller (SRC) */ | |
| 133 | struct src { | |
| 134 | u32 bmr1; | |
| 135 | u32 bmr2; | |
| 136 | u32 gpr1_boot; | |
| 137 | u32 reserved_0x00C[61]; | |
| 138 | u32 gpr1; | |
| 139 | u32 gpr2; | |
| 140 | u32 gpr3; | |
| 141 | u32 gpr4; | |
| 142 | u32 gpr5; | |
| 143 | u32 gpr6; | |
| 144 | u32 gpr7; | |
| 145 | u32 reserved_0x11C[1]; | |
| 146 | u32 gpr9; | |
| 147 | u32 gpr10; | |
| 148 | u32 gpr11; | |
| 149 | u32 gpr12; | |
| 150 | u32 gpr13; | |
| 151 | u32 gpr14; | |
| 152 | u32 gpr15; | |
| 153 | u32 gpr16; | |
| 154 | u32 reserved_0x140[1]; | |
| 155 | u32 gpr17; | |
| 156 | u32 gpr18; | |
| 157 | u32 gpr19; | |
| 158 | u32 gpr20; | |
| 159 | u32 gpr21; | |
| 160 | u32 gpr22; | |
| 161 | u32 gpr23; | |
| 162 | u32 gpr24; | |
| 163 | u32 gpr25; | |
| 164 | u32 gpr26; | |
| 165 | u32 gpr27; | |
| 166 | u32 reserved_0x16C[5]; | |
| 167 | u32 pcie_config1; | |
| 168 | u32 ddr_self_ref_ctrl; | |
| 169 | u32 pcie_config0; | |
| 170 | u32 reserved_0x18C[4]; | |
| 171 | u32 soc_misc_config2; | |
| 172 | }; | |
| 173 | ||
| 174 | /* SRC registers definitions */ | |
| 175 | ||
| 176 | /* SRC_GPR1 */ | |
| 177 | #define SRC_GPR1_PLL_SOURCE(pll,val)( ((val) & SRC_GPR1_PLL_SOURCE_MASK) << \ | |
| 178 | (SRC_GPR1_PLL_OFFSET + (pll)) ) | |
| 179 | #define SRC_GPR1_PLL_SOURCE_MASK (0x1) | |
| 180 | ||
| 181 | #define SRC_GPR1_PLL_OFFSET (27) | |
| 182 | #define SRC_GPR1_FIRC_CLK_SOURCE (0x0) | |
| 183 | #define SRC_GPR1_XOSC_CLK_SOURCE (0x1) | |
| 184 | ||
| 185 | /* Periodic Interrupt Timer (PIT) */ | |
| 186 | struct pit_reg { | |
| 187 | u32 mcr; | |
| 188 | u32 recv0[55]; | |
| 189 | u32 ltmr64h; | |
| 190 | u32 ltmr64l; | |
| 191 | u32 recv1[6]; | |
| 192 | u32 ldval0; | |
| 193 | u32 cval0; | |
| 194 | u32 tctrl0; | |
| 195 | u32 tflg0; | |
| 196 | u32 ldval1; | |
| 197 | u32 cval1; | |
| 198 | u32 tctrl1; | |
| 199 | u32 tflg1; | |
| 200 | u32 ldval2; | |
| 201 | u32 cval2; | |
| 202 | u32 tctrl2; | |
| 203 | u32 tflg2; | |
| 204 | u32 ldval3; | |
| 205 | u32 cval3; | |
| 206 | u32 tctrl3; | |
| 207 | u32 tflg3; | |
| 208 | u32 ldval4; | |
| 209 | u32 cval4; | |
| 210 | u32 tctrl4; | |
| 211 | u32 tflg4; | |
| 212 | u32 ldval5; | |
| 213 | u32 cval5; | |
| 214 | u32 tctrl5; | |
| 215 | u32 tflg5; | |
| 216 | }; | |
| 217 | ||
| 218 | /* Watchdog Timer (WDOG) */ | |
| 219 | struct wdog_regs { | |
| 220 | u32 cr; | |
| 221 | u32 ir; | |
| 222 | u32 to; | |
| 223 | u32 wn; | |
| 224 | u32 sr; | |
| 225 | u32 co; | |
| 226 | u32 sk; | |
| 227 | }; | |
| 228 | ||
| 229 | /* UART */ | |
| 230 | struct linflex_fsl { | |
| 231 | u32 lincr1; | |
| 232 | u32 linier; | |
| 233 | u32 linsr; | |
| 234 | u32 linesr; | |
| 235 | u32 uartcr; | |
| 236 | u32 uartsr; | |
| 237 | u32 lintcsr; | |
| 238 | u32 linocr; | |
| 239 | u32 lintocr; | |
| 240 | u32 linfbrr; | |
| 241 | u32 linibrr; | |
| 242 | u32 lincfr; | |
| 243 | u32 lincr2; | |
| 244 | u32 bidr; | |
| 245 | u32 bdrl; | |
| 246 | u32 bdrm; | |
| 247 | u32 ifer; | |
| 248 | u32 ifmi; | |
| 249 | u32 ifmr; | |
| 250 | u32 ifcr0; | |
| 251 | u32 ifcr1; | |
| 252 | u32 ifcr2; | |
| 253 | u32 ifcr3; | |
| 254 | u32 ifcr4; | |
| 255 | u32 ifcr5; | |
| 256 | u32 ifcr6; | |
| 257 | u32 ifcr7; | |
| 258 | u32 ifcr8; | |
| 259 | u32 ifcr9; | |
| 260 | u32 ifcr10; | |
| 261 | u32 ifcr11; | |
| 262 | u32 ifcr12; | |
| 263 | u32 ifcr13; | |
| 264 | u32 ifcr14; | |
| 265 | u32 ifcr15; | |
| 266 | u32 gcr; | |
| 267 | u32 uartpto; | |
| 268 | u32 uartcto; | |
| 269 | u32 dmatxe; | |
| 270 | u32 dmarxe; | |
| 271 | }; | |
| 272 | ||
| 273 | /* MSCM Interrupt Router */ | |
| 274 | struct mscm_ir { | |
| 275 | u32 cpxtype; /* Processor x Type Register */ | |
| 276 | u32 cpxnum; /* Processor x Number Register */ | |
| 277 | u32 cpxmaster; /* Processor x Master Number Register */ | |
| 278 | u32 cpxcount; /* Processor x Count Register */ | |
| 279 | u32 cpxcfg0; /* Processor x Configuration 0 Register */ | |
| 280 | u32 cpxcfg1; /* Processor x Configuration 1 Register */ | |
| 281 | u32 cpxcfg2; /* Processor x Configuration 2 Register */ | |
| 282 | u32 cpxcfg3; /* Processor x Configuration 3 Register */ | |
| 283 | u32 cp0type; /* Processor 0 Type Register */ | |
| 284 | u32 cp0num; /* Processor 0 Number Register */ | |
| 285 | u32 cp0master; /* Processor 0 Master Number Register */ | |
| 286 | u32 cp0count; /* Processor 0 Count Register */ | |
| 287 | u32 cp0cfg0; /* Processor 0 Configuration 0 Register */ | |
| 288 | u32 cp0cfg1; /* Processor 0 Configuration 1 Register */ | |
| 289 | u32 cp0cfg2; /* Processor 0 Configuration 2 Register */ | |
| 290 | u32 cp0cfg3; /* Processor 0 Configuration 3 Register */ | |
| 291 | u32 cp1type; /* Processor 1 Type Register */ | |
| 292 | u32 cp1num; /* Processor 1 Number Register */ | |
| 293 | u32 cp1master; /* Processor 1 Master Number Register */ | |
| 294 | u32 cp1count; /* Processor 1 Count Register */ | |
| 295 | u32 cp1cfg0; /* Processor 1 Configuration 0 Register */ | |
| 296 | u32 cp1cfg1; /* Processor 1 Configuration 1 Register */ | |
| 297 | u32 cp1cfg2; /* Processor 1 Configuration 2 Register */ | |
| 298 | u32 cp1cfg3; /* Processor 1 Configuration 3 Register */ | |
| 299 | u32 reserved_0x060[232]; | |
| 300 | u32 ocmdr0; /* On-Chip Memory Descriptor Register */ | |
| 301 | u32 reserved_0x404[2]; | |
| 302 | u32 ocmdr3; /* On-Chip Memory Descriptor Register */ | |
| 303 | u32 reserved_0x410[28]; | |
| 304 | u32 tcmdr[4]; /* Generic Tightly Coupled Memory Descriptor Register */ | |
| 305 | u32 reserved_0x490[28]; | |
| 306 | u32 cpce0; /* Core Parity Checking Enable Register 0 */ | |
| 307 | u32 reserved_0x504[191]; | |
| 308 | u32 ircp0ir; /* Interrupt Router CP0 Interrupt Register */ | |
| 309 | u32 ircp1ir; /* Interrupt Router CP1 Interrupt Register */ | |
| 310 | u32 reserved_0x808[6]; | |
| 311 | u32 ircpgir; /* Interrupt Router CPU Generate Interrupt Register */ | |
| 312 | u32 reserved_0x824[23]; | |
| 313 | u16 irsprc[176]; /* Interrupt Router Shared Peripheral Routing Control Register */ | |
| 314 | u32 reserved_0x9e0[136]; | |
| 315 | u32 iahbbe0; /* Gasket Burst Enable Register */ | |
| 316 | u32 reserved_0xc04[63]; | |
| 317 | u32 ipcge; /* Interconnect Parity Checking Global Enable Register */ | |
| 318 | u32 reserved_0xd04[3]; | |
| 319 | u32 ipce[4]; /* Interconnect Parity Checking Enable Register */ | |
| 320 | u32 reserved_0xd20[8]; | |
| 321 | u32 ipcgie; /* Interconnect Parity Checking Global Injection Enable Register */ | |
| 322 | u32 reserved_0xd44[3]; | |
| 323 | u32 ipcie[4]; /* Interconnect Parity Checking Injection Enable Register */ | |
| 324 | }; | |
| 325 | ||
| 326 | #endif /* __ASSEMBLER__ */ | |
| 327 | ||
| 328 | #endif /* __ASM_ARCH_IMX_REGS_H__ */ |