[people/ms/u-boot.git] / arch / arm / include / asm / arch-socfpga / clock_manager.h

/*
 *  Copyright (C) 2013 Altera Corporation <www.altera.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef	_CLOCK_MANAGER_H_
#define	_CLOCK_MANAGER_H_

#ifndef __ASSEMBLER__
/* Clock speed accessors */
unsigned long cm_get_mpu_clk_hz(void);
unsigned long cm_get_sdram_clk_hz(void);
unsigned int cm_get_l4_sp_clk_hz(void);
unsigned int cm_get_mmc_controller_clk_hz(void);
unsigned int cm_get_qspi_controller_clk_hz(void);
#endif

typedef struct {
	/* main group */
	uint32_t main_vco_base;
	uint32_t mpuclk;
	uint32_t mainclk;
	uint32_t dbgatclk;
	uint32_t mainqspiclk;
	uint32_t mainnandsdmmcclk;
	uint32_t cfg2fuser0clk;
	uint32_t maindiv;
	uint32_t dbgdiv;
	uint32_t tracediv;
	uint32_t l4src;

	/* peripheral group */
	uint32_t peri_vco_base;
	uint32_t emac0clk;
	uint32_t emac1clk;
	uint32_t perqspiclk;
	uint32_t pernandsdmmcclk;
	uint32_t perbaseclk;
	uint32_t s2fuser1clk;
	uint32_t perdiv;
	uint32_t gpiodiv;
	uint32_t persrc;

	/* sdram pll group */
	uint32_t sdram_vco_base;
	uint32_t ddrdqsclk;
	uint32_t ddr2xdqsclk;
	uint32_t ddrdqclk;
	uint32_t s2fuser2clk;
} cm_config_t;

extern void cm_basic_init(const cm_config_t *cfg);

struct socfpga_clock_manager_main_pll {
	u32	vco;
	u32	misc;
	u32	mpuclk;
	u32	mainclk;
	u32	dbgatclk;
	u32	mainqspiclk;
	u32	mainnandsdmmcclk;
	u32	cfgs2fuser0clk;
	u32	en;
	u32	maindiv;
	u32	dbgdiv;
	u32	tracediv;
	u32	l4src;
	u32	stat;
	u32	_pad_0x38_0x40[2];
};

struct socfpga_clock_manager_per_pll {
	u32	vco;
	u32	misc;
	u32	emac0clk;
	u32	emac1clk;
	u32	perqspiclk;
	u32	pernandsdmmcclk;
	u32	perbaseclk;
	u32	s2fuser1clk;
	u32	en;
	u32	div;
	u32	gpiodiv;
	u32	src;
	u32	stat;
	u32	_pad_0x34_0x40[3];
};

struct socfpga_clock_manager_sdr_pll {
	u32	vco;
	u32	ctrl;
	u32	ddrdqsclk;
	u32	ddr2xdqsclk;
	u32	ddrdqclk;
	u32	s2fuser2clk;
	u32	en;
	u32	stat;
};

struct socfpga_clock_manager_altera {
	u32	mpuclk;
	u32	mainclk;
};

struct socfpga_clock_manager {
	u32	ctrl;
	u32	bypass;
	u32	inter;
	u32	intren;
	u32	dbctrl;
	u32	stat;
	u32	_pad_0x18_0x3f[10];
	struct socfpga_clock_manager_main_pll main_pll;
	struct socfpga_clock_manager_per_pll per_pll;
	struct socfpga_clock_manager_sdr_pll sdr_pll;
	struct socfpga_clock_manager_altera altera;
	u32	_pad_0xe8_0x200[70];
};

#define CLKMGR_CTRL_SAFEMODE				(1 << 0)
#define CLKMGR_CTRL_SAFEMODE_OFFSET			0

#define CLKMGR_BYPASS_PERPLLSRC				(1 << 4)
#define CLKMGR_BYPASS_PERPLLSRC_OFFSET			4
#define CLKMGR_BYPASS_PERPLL				(1 << 3)
#define CLKMGR_BYPASS_PERPLL_OFFSET			3
#define CLKMGR_BYPASS_SDRPLLSRC				(1 << 2)
#define CLKMGR_BYPASS_SDRPLLSRC_OFFSET			2
#define CLKMGR_BYPASS_SDRPLL				(1 << 1)
#define CLKMGR_BYPASS_SDRPLL_OFFSET			1
#define CLKMGR_BYPASS_MAINPLL				(1 << 0)
#define CLKMGR_BYPASS_MAINPLL_OFFSET			0

#define CLKMGR_INTER_SDRPLLLOCKED_MASK			0x00000100
#define CLKMGR_INTER_PERPLLLOCKED_MASK			0x00000080
#define CLKMGR_INTER_MAINPLLLOCKED_MASK			0x00000040
#define CLKMGR_INTER_PERPLLLOST_MASK			0x00000010
#define CLKMGR_INTER_SDRPLLLOST_MASK			0x00000020
#define CLKMGR_INTER_MAINPLLLOST_MASK			0x00000008

#define CLKMGR_STAT_BUSY				(1 << 0)

/* Main PLL */
#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN			(1 << 0)
#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_OFFSET		0
#define CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET		16
#define CLKMGR_MAINPLLGRP_VCO_DENOM_MASK		0x003f0000
#define CLKMGR_MAINPLLGRP_VCO_EN			(1 << 1)
#define CLKMGR_MAINPLLGRP_VCO_EN_OFFSET			1
#define CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET		3
#define CLKMGR_MAINPLLGRP_VCO_NUMER_MASK		0x0000fff8
#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK		0x01000000
#define CLKMGR_MAINPLLGRP_VCO_PWRDN			(1 << 2)
#define CLKMGR_MAINPLLGRP_VCO_PWRDN_OFFSET		2
#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK		0x80000000
#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE		0x8001000d

#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET		0
#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_MASK		0x000001ff

#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET		0
#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_MASK		0x000001ff

#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET		0
#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_MASK		0x000001ff

#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET	0
#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_MASK		0x000001ff

#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_OFFSET	0
#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_MASK	0x000001ff

#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET	0
#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_MASK	0x000001ff

#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK		0x00000010
#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK		0x00000020
#define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK		0x00000080
#define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK		0x00000040
#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK		0x00000004
#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK		0x00000200

#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET	0
#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_MASK		0x00000003
#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET	2
#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_MASK		0x0000000c
#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET	4
#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_MASK		0x00000070
#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET	7
#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK		0x00000380

#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET	0
#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_MASK		0x00000003
#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET		2
#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_MASK		0x0000000c

#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET	0
#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_MASK	0x00000007

#define CLKMGR_MAINPLLGRP_L4SRC_L4MP			(1 << 0)
#define CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET		0
#define CLKMGR_MAINPLLGRP_L4SRC_L4SP			(1 << 1)
#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET		1
#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE		0x00000000
#define CLKMGR_L4_SP_CLK_SRC_MAINPLL			0x0
#define CLKMGR_L4_SP_CLK_SRC_PERPLL			0x1

/* Per PLL */
#define CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET		16
#define CLKMGR_PERPLLGRP_VCO_DENOM_MASK			0x003f0000
#define CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET		3
#define CLKMGR_PERPLLGRP_VCO_NUMER_MASK			0x0000fff8
#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK		0x01000000
#define CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET		22
#define CLKMGR_PERPLLGRP_VCO_PSRC_MASK			0x00c00000
#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK		0x80000000
#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE		0x8001000d
#define CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET		22
#define CLKMGR_PERPLLGRP_VCO_SSRC_MASK			0x00c00000

#define CLKMGR_VCO_SSRC_EOSC1				0x0
#define CLKMGR_VCO_SSRC_EOSC2				0x1
#define CLKMGR_VCO_SSRC_F2S				0x2

#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET		0
#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_MASK		0x000001ff

#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET		0
#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_MASK		0x000001ff

#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET		0
#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_MASK		0x000001ff

#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET	0
#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_MASK	0x000001ff

#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET		0
#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_MASK		0x000001ff

#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET		0
#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_MASK		0x000001ff

#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK		0x00000400
#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK		0x00000100

#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET		6
#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_MASK		0x000001c0
#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET		9
#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_MASK		0x00000e00
#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET		3
#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET		3
#define CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET		0
#define CLKMGR_PERPLLGRP_DIV_USBCLK_MASK		0x00000007

#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET	0
#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_MASK		0x00ffffff

#define CLKMGR_PERPLLGRP_SRC_NAND_OFFSET		2
#define CLKMGR_PERPLLGRP_SRC_NAND_MASK			0x0000000c
#define CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET		4
#define CLKMGR_PERPLLGRP_SRC_QSPI_MASK			0x00000030
#define CLKMGR_PERPLLGRP_SRC_RESET_VALUE		0x00000015
#define CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET		0
#define CLKMGR_PERPLLGRP_SRC_SDMMC_MASK			0x00000003
#define CLKMGR_SDMMC_CLK_SRC_F2S			0x0
#define CLKMGR_SDMMC_CLK_SRC_MAIN			0x1
#define CLKMGR_SDMMC_CLK_SRC_PER			0x2
#define CLKMGR_QSPI_CLK_SRC_F2S				0x0
#define CLKMGR_QSPI_CLK_SRC_MAIN			0x1
#define CLKMGR_QSPI_CLK_SRC_PER				0x2

/* SDR PLL */
#define CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET		16
#define CLKMGR_SDRPLLGRP_VCO_DENOM_MASK			0x003f0000
#define CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET		3
#define CLKMGR_SDRPLLGRP_VCO_NUMER_MASK			0x0000fff8
#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL		(1 << 24)
#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_OFFSET		24
#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_OFFSET		25
#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK		0x7e000000
#define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK		0x80000000
#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE		0x8001000d
#define CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET		22
#define CLKMGR_SDRPLLGRP_VCO_SSRC_MASK			0x00c00000

#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET		0
#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK		0x000001ff
#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET		9
#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK		0x00000e00

#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET		0
#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK		0x000001ff
#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET	9
#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK		0x00000e00

#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET		0
#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK		0x000001ff
#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET		9
#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK		0x00000e00

#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET		0
#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK		0x000001ff
#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET	9
#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK		0x00000e00

#endif /* _CLOCK_MANAGER_H_ */
Commit	Line	Data
ddfeb0aa CLS	1	/*
	2	* Copyright (C) 2013 Altera Corporation <www.altera.com>
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef _CLOCK_MANAGER_H_
	8	#define _CLOCK_MANAGER_H_
	9
a832ddba PM	10	#ifndef __ASSEMBLER__
	11	/* Clock speed accessors */
	12	unsigned long cm_get_mpu_clk_hz(void);
	13	unsigned long cm_get_sdram_clk_hz(void);
	14	unsigned int cm_get_l4_sp_clk_hz(void);
	15	unsigned int cm_get_mmc_controller_clk_hz(void);
	16	unsigned int cm_get_qspi_controller_clk_hz(void);
	17	#endif
	18
ddfeb0aa CLS	19	typedef struct {
	20	/* main group */
	21	uint32_t main_vco_base;
	22	uint32_t mpuclk;
	23	uint32_t mainclk;
	24	uint32_t dbgatclk;
	25	uint32_t mainqspiclk;
	26	uint32_t mainnandsdmmcclk;
	27	uint32_t cfg2fuser0clk;
	28	uint32_t maindiv;
	29	uint32_t dbgdiv;
	30	uint32_t tracediv;
	31	uint32_t l4src;
	32
	33	/* peripheral group */
	34	uint32_t peri_vco_base;
	35	uint32_t emac0clk;
	36	uint32_t emac1clk;
	37	uint32_t perqspiclk;
	38	uint32_t pernandsdmmcclk;
	39	uint32_t perbaseclk;
	40	uint32_t s2fuser1clk;
	41	uint32_t perdiv;
	42	uint32_t gpiodiv;
	43	uint32_t persrc;
	44
	45	/* sdram pll group */
	46	uint32_t sdram_vco_base;
	47	uint32_t ddrdqsclk;
	48	uint32_t ddr2xdqsclk;
	49	uint32_t ddrdqclk;
	50	uint32_t s2fuser2clk;
	51	} cm_config_t;
	52
	53	extern void cm_basic_init(const cm_config_t *cfg);
	54
51fb455f PM	55	struct socfpga_clock_manager_main_pll {
	56	u32 vco;
	57	u32 misc;
	58	u32 mpuclk;
	59	u32 mainclk;
	60	u32 dbgatclk;
	61	u32 mainqspiclk;
	62	u32 mainnandsdmmcclk;
	63	u32 cfgs2fuser0clk;
	64	u32 en;
	65	u32 maindiv;
	66	u32 dbgdiv;
	67	u32 tracediv;
	68	u32 l4src;
	69	u32 stat;
	70	u32 _pad_0x38_0x40[2];
	71	};
	72
	73	struct socfpga_clock_manager_per_pll {
	74	u32 vco;
	75	u32 misc;
	76	u32 emac0clk;
	77	u32 emac1clk;
	78	u32 perqspiclk;
	79	u32 pernandsdmmcclk;
	80	u32 perbaseclk;
	81	u32 s2fuser1clk;
	82	u32 en;
	83	u32 div;
	84	u32 gpiodiv;
	85	u32 src;
	86	u32 stat;
	87	u32 _pad_0x34_0x40[3];
	88	};
	89
	90	struct socfpga_clock_manager_sdr_pll {
	91	u32 vco;
	92	u32 ctrl;
	93	u32 ddrdqsclk;
	94	u32 ddr2xdqsclk;
	95	u32 ddrdqclk;
	96	u32 s2fuser2clk;
	97	u32 en;
	98	u32 stat;
	99	};
	100
a832ddba PM	101	struct socfpga_clock_manager_altera {
	102	u32 mpuclk;
	103	u32 mainclk;
	104	};
	105
ddfeb0aa CLS	106	struct socfpga_clock_manager {
	107	u32 ctrl;
	108	u32 bypass;
	109	u32 inter;
	110	u32 intren;
	111	u32 dbctrl;
	112	u32 stat;
	113	u32 _pad_0x18_0x3f[10];
51fb455f PM	114	struct socfpga_clock_manager_main_pll main_pll;
	115	struct socfpga_clock_manager_per_pll per_pll;
	116	struct socfpga_clock_manager_sdr_pll sdr_pll;
a832ddba PM	117	struct socfpga_clock_manager_altera altera;
a832ddba PM	118	u32 _pad_0xe8_0x200[70];
ddfeb0aa CLS	119	};
ddfeb0aa CLS	120
44428ab6 MV	121	#define CLKMGR_CTRL_SAFEMODE (1 << 0)
	122	#define CLKMGR_CTRL_SAFEMODE_OFFSET 0
	123
	124	#define CLKMGR_BYPASS_PERPLLSRC (1 << 4)
	125	#define CLKMGR_BYPASS_PERPLLSRC_OFFSET 4
	126	#define CLKMGR_BYPASS_PERPLL (1 << 3)
	127	#define CLKMGR_BYPASS_PERPLL_OFFSET 3
	128	#define CLKMGR_BYPASS_SDRPLLSRC (1 << 2)
	129	#define CLKMGR_BYPASS_SDRPLLSRC_OFFSET 2
	130	#define CLKMGR_BYPASS_SDRPLL (1 << 1)
	131	#define CLKMGR_BYPASS_SDRPLL_OFFSET 1
	132	#define CLKMGR_BYPASS_MAINPLL (1 << 0)
	133	#define CLKMGR_BYPASS_MAINPLL_OFFSET 0
	134
	135	#define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100
	136	#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080
	137	#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040
036ba54f MV	138	#define CLKMGR_INTER_PERPLLLOST_MASK 0x00000010
	139	#define CLKMGR_INTER_SDRPLLLOST_MASK 0x00000020
	140	#define CLKMGR_INTER_MAINPLLLOST_MASK 0x00000008
44428ab6 MV	141
44428ab6 MV	142	#define CLKMGR_STAT_BUSY (1 << 0)
09f7e314 MV	143
09f7e314 MV	144	/* Main PLL */
44428ab6 MV	145	#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN (1 << 0)
	146	#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_OFFSET 0
	147	#define CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET 16
	148	#define CLKMGR_MAINPLLGRP_VCO_DENOM_MASK 0x003f0000
	149	#define CLKMGR_MAINPLLGRP_VCO_EN (1 << 1)
	150	#define CLKMGR_MAINPLLGRP_VCO_EN_OFFSET 1
	151	#define CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET 3
	152	#define CLKMGR_MAINPLLGRP_VCO_NUMER_MASK 0x0000fff8
	153	#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
	154	#define CLKMGR_MAINPLLGRP_VCO_PWRDN (1 << 2)
	155	#define CLKMGR_MAINPLLGRP_VCO_PWRDN_OFFSET 2
	156	#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
	157	#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d
	158
	159	#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET 0
	160	#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_MASK 0x000001ff
	161
	162	#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET 0
	163	#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_MASK 0x000001ff
	164
	165	#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET 0
	166	#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_MASK 0x000001ff
	167
	168	#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET 0
	169	#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_MASK 0x000001ff
	170
	171	#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_OFFSET 0
	172	#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_MASK 0x000001ff
	173
	174	#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET 0
	175	#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_MASK 0x000001ff
	176
	177	#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x00000010
	178	#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x00000020
	179	#define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK 0x00000080
	180	#define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK 0x00000040
	181	#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK 0x00000004
	182	#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200
	183
	184	#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET 0
	185	#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_MASK 0x00000003
	186	#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET 2
	187	#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_MASK 0x0000000c
	188	#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET 4
	189	#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_MASK 0x00000070
	190	#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET 7
	191	#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK 0x00000380
	192
	193	#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET 0
	194	#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_MASK 0x00000003
	195	#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET 2
	196	#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_MASK 0x0000000c
	197
	198	#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET 0
	199	#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_MASK 0x00000007
	200
	201	#define CLKMGR_MAINPLLGRP_L4SRC_L4MP (1 << 0)
	202	#define CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET 0
	203	#define CLKMGR_MAINPLLGRP_L4SRC_L4SP (1 << 1)
	204	#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET 1
	205	#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000
	206	#define CLKMGR_L4_SP_CLK_SRC_MAINPLL 0x0
	207	#define CLKMGR_L4_SP_CLK_SRC_PERPLL 0x1
09f7e314 MV	208
09f7e314 MV	209	/* Per PLL */
44428ab6 MV	210	#define CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET 16
	211	#define CLKMGR_PERPLLGRP_VCO_DENOM_MASK 0x003f0000
	212	#define CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET 3
	213	#define CLKMGR_PERPLLGRP_VCO_NUMER_MASK 0x0000fff8
	214	#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
	215	#define CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET 22
	216	#define CLKMGR_PERPLLGRP_VCO_PSRC_MASK 0x00c00000
	217	#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
	218	#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d
	219	#define CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET 22
	220	#define CLKMGR_PERPLLGRP_VCO_SSRC_MASK 0x00c00000
	221
	222	#define CLKMGR_VCO_SSRC_EOSC1 0x0
	223	#define CLKMGR_VCO_SSRC_EOSC2 0x1
	224	#define CLKMGR_VCO_SSRC_F2S 0x2
	225
	226	#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET 0
	227	#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_MASK 0x000001ff
	228
	229	#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET 0
	230	#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_MASK 0x000001ff
	231
	232	#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET 0
	233	#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_MASK 0x000001ff
	234
	235	#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET 0
	236	#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_MASK 0x000001ff
	237
	238	#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET 0
	239	#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_MASK 0x000001ff
	240
	241	#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET 0
	242	#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_MASK 0x000001ff
	243
	244	#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400
	245	#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000100
	246
	247	#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET 6
	248	#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_MASK 0x000001c0
	249	#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET 9
	250	#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_MASK 0x00000e00
	251	#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET 3
	252	#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET 3
	253	#define CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET 0
	254	#define CLKMGR_PERPLLGRP_DIV_USBCLK_MASK 0x00000007
	255
	256	#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET 0
	257	#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_MASK 0x00ffffff
	258
	259	#define CLKMGR_PERPLLGRP_SRC_NAND_OFFSET 2
	260	#define CLKMGR_PERPLLGRP_SRC_NAND_MASK 0x0000000c
	261	#define CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET 4
	262	#define CLKMGR_PERPLLGRP_SRC_QSPI_MASK 0x00000030
	263	#define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015
	264	#define CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET 0
	265	#define CLKMGR_PERPLLGRP_SRC_SDMMC_MASK 0x00000003
	266	#define CLKMGR_SDMMC_CLK_SRC_F2S 0x0
	267	#define CLKMGR_SDMMC_CLK_SRC_MAIN 0x1
	268	#define CLKMGR_SDMMC_CLK_SRC_PER 0x2
	269	#define CLKMGR_QSPI_CLK_SRC_F2S 0x0
	270	#define CLKMGR_QSPI_CLK_SRC_MAIN 0x1
	271	#define CLKMGR_QSPI_CLK_SRC_PER 0x2
09f7e314 MV	272
09f7e314 MV	273	/* SDR PLL */
44428ab6 MV	274	#define CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET 16
	275	#define CLKMGR_SDRPLLGRP_VCO_DENOM_MASK 0x003f0000
	276	#define CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET 3
	277	#define CLKMGR_SDRPLLGRP_VCO_NUMER_MASK 0x0000fff8
	278	#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL (1 << 24)
	279	#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_OFFSET 24
	280	#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_OFFSET 25
	281	#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000
	282	#define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
	283	#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d
	284	#define CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET 22
	285	#define CLKMGR_SDRPLLGRP_VCO_SSRC_MASK 0x00c00000
	286
	287	#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET 0
	288	#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff
	289	#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET 9
	290	#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x00000e00
	291
	292	#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET 0
	293	#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff
	294	#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET 9
	295	#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x00000e00
	296
	297	#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET 0
	298	#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff
	299	#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET 9
	300	#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x00000e00
	301
	302	#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET 0
	303	#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff
	304	#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET 9
	305	#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x00000e00
ddfeb0aa CLS	306
ddfeb0aa CLS	307	#endif /* _CLOCK_MANAGER_H_ */